JPH11298481A - Shaping circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the shaping circuit by requiring only a clock generating circuit section for a means to materialize shaping. SOLUTION: A control section 1 stores shaping speed information for each logical path. A clock generating circuit 14 generates a 2nd clock based on the shaping speed information. Receiving serial data 13 from a terminal with a 1st clock 15, a speed conversion section 11 replaces the 2nd clock 16 with serial data 13 and outputs the result to a cell processing circuit 12. The cell processing circuit 12 coverts serial data into an asynchronous transfer mode ATM cell format and outputs the converted data to a multiplexer/contention section 3. The multiplexer/contention section 3 extracts an ATM cell from a cell processing circuit that makes a fastest transmission request and sends the cell to an ATM network.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ATM-UNI.
(Asynchronous TransferMod
e-User Network Interface)
The present invention relates to a shaping circuit required when a terminal having no is connected to an ATM network.

[0002]

2. Description of the Related Art In an ATM network, a band to be used is specified for each logical path, and cells are transmitted and received. Therefore, if a cell is sent to the ATM network beyond the contract bandwidth, the cell is discarded. For this reason, when connecting a terminal having no ATM-UNI to an ATM network having a band limitation, it is necessary to perform shaping for adjusting the interval of serial data input to the cell circuit to be within the contract band.

An example of this type of conventional shaping method is described in Japanese Patent Application Laid-Open No. Hei 8-125668.
The technique described in this publication provides a shaping method capable of controlling a cell transmission interval for each logical path. That is, the input cells are temporarily stored in the buffer memory for each logical path, and the transmission time of the input cells is determined in accordance with the traffic condition previously declared corresponding to the identifier of the group to which the input cells belong. And comparing the transmission time of the cell with the transmission time assigned to the first-arrived cell. If the transmission times overlap, the transmission time determined in the first step is corrected, and then the transmission time is corrected. And a second step of storing a correspondence relationship between the cell identifier and the identification information of the input cell. Based on the correspondence relationship between the cell identifier and the transmission time stored in the second step, the cell stored in the buffer memory is stored. Read out in order of sending time,
And a third step of transmitting to an output line.

[0004]

However, in the above-described conventional shaping method, it is necessary to store time information and previous cell transmission time information and to perform transmission control for each cell, so that control is complicated. There is a point. Also, when the first arrival cell and the transmission time overlap, it is necessary to recalculate the transmission time again. Furthermore, there is a problem that the calculation amount of the transmission time increases in proportion to the number of logical paths, and the load on the control circuit increases.

An object of the present invention is to provide a simple shaping circuit.

[0006]

According to the present invention, a shaping circuit for connecting a terminal having no ATM user network interface to an ATM network generates a clock synchronized with a contract band for each logical path. It is characterized in that serial data carried on this clock is converted into cells.

A shaping circuit according to a preferred embodiment of the present invention comprises: a clock generating circuit for generating a second clock synchronized with a contract band for each logical path;
A speed converter for receiving serial data from the terminal at a first clock synchronized therewith and transmitting the serial data at the second clock; and a cell conversion circuit for converting the transmitted serial data into an ATM cell format. And

[0008] A shaping circuit according to a preferred embodiment of the present invention includes: a clock generating circuit that generates a second clock synchronized with a contract band for each logical path and supplies the second clock to the terminal; It is characterized by having a celling circuit for receiving the synchronized serial data and converting it to the ATM cell format.

[0009] A shaping circuit as a preferred embodiment of the present invention reads out the shaping speed information from the information table storing shaping speed information for the contracted bandwidth for each of the logical paths and sends it to the clock generation circuit. A control unit including a CPU is provided,
The clock generation circuit includes an offset setting register that sets and stores a count value for a contract bandwidth for each logical path, and a counter that counts only the count value and generates the second clock. The speed conversion unit detects a flag indicating the valid data range from the serial data and outputs an enable signal, and the serial data is input only while the enable signal is being input; And a FIFO which is output to the cell circuit in synchronization with two clocks.

[0010]

Next, an embodiment of the present invention will be described.

[0011] A shaping circuit according to the present invention is provided for a terminal having no ATM user network interface.
In a shaping circuit for connecting to a network, a clock synchronized with a contract band for each logical path is generated, and serial data carried on this clock is converted into cells.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. N clock generating circuits 14, 24,..., 34, N connected to a control unit 1 via a control unit 1 and a control bus 2 are shown.
, 31, 21... 31, N cell conversion circuits 1
2, 22,... 32 and the multiplexing / competition unit 3.
The speed conversion unit 11 and the like, the cell circuit 12 and the like, and the clock generation circuit 14 and the like correspond to N logic paths.

The speed converter 11 is a speed converter for transmitting serial data 13 from an existing terminal at a second clock 16 different from the received first clock 15. The celling circuit 12 converts the serial data sent from the speed converter 11 into an ATM cell format. The celling circuit 12 that has converted the serial data into cells also issues a transmission request to the multiplexing / competition unit 3. The multiplexing / competition unit 3 receiving the transmission request from the plurality of cell circuits picks up the ATM cell from the cell circuit 12 which has issued the earliest transmission request, and sends the ATM cell to the ATM network to form a unique shaping circuit. Is unnecessary. Further, the clock generation circuit 14 generates a second clock based on the contract bandwidth information and supplies the second clock to the speed conversion unit 11. It should be noted that the speed conversion unit 21 and the like, the cell conversion circuit 22 and the like, and the clock generation circuit 24 and the like corresponding to other logical paths also have the same functions as the above-described speed conversion unit 11, the cell conversion circuit 12 and the clock generation circuit 14.

FIG. 2 is a detailed block diagram of the speed converter 11, the cell circuit 12, the clock generator 14, and the controller 1 of FIG.

The shaping speed information for each logical path corresponding to the serial data 13, 23... 33 is stored in the table 101 of the control unit 1, and the CPU 102 stores the shaping speed information of the corresponding logical path from the information table 101. The offset setting register 1 of the clock generation circuit 14 is read and converted into the count value of the counter 141.
Write to 42.

The clock generation circuit 14 has an offset setting register 142 for holding a count value set by the CPU 102, and a counter 141 for counting the count value and generating a second clock having a constant period.

The speed converter 11 outputs the serial data 13, detects a flag indicating the valid data range from the serial data 13, and outputs an enable signal 113.
A flag detection circuit 111 for outputting the enable signal 1
The FIFO 112 is configured to receive the serial data 13 only while the data 13 is being input, and output the serial data 13 to the cell circuit 12 in synchronization with the second clock 16.

FIG. 3 shows the relationship between the first clock 15, the serial data 13, and the enable signal 113, and FIG. 4 shows the input (serial data 13) and output (FIFO) of the speed converter 11.
12 output). Serial data 1 in FIG.
3 is not limited to a fixed length, but is shown as a fixed length for convenience.
Also, in FIG. 4, it can be seen that the serial data 13 asynchronously input to the speed conversion unit 11 is arranged at regular intervals.

As described above, in this embodiment, the FIFO 11
2 for writing the first clock 15 and reading for the second clock 15.
By using a clock, writing and reading of the serial data 13 are performed asynchronously.

The celling circuit 12 includes a FIFO 112
And an S / P conversion circuit 121 for converting serial data read out of the data into parallel data, and a header generation circuit 122 for converting the parallel-converted data into a cell format.
Having.

Next, the operation of this embodiment will be described.

The information table 101 of the control section 1 stores shaping speed information for each logical path. CP
U 102 reads the shaping speed information from the information table 101, converts it into a count value, and writes it into each offset setting register 142. Counter 141
Counts the count value and outputs a second clock 16 having a constant period.

When the serial data 13 is input from the terminal to the speed converter 11 together with the first clock 15, the flag detection circuit 111 outputs the serial data 13 to the FIFO 112 and detects a flag indicating the valid data range of the serial data 13. Then, an enable signal 113 is generated. The FIFO 112 stores the input serial data 13
Are captured in synchronization with the falling edge of the first clock 15 during the time period in which the enable signal 113 is designated, and are output in the cycle of the second clock 16 in the capturing order. That is, the speed conversion unit 11 receives the first clock 15 synchronized with the serial data 13 for data reception.
Is received on the basis of the second clock 1 from the clock generation circuit 14 with respect to data transmission to the celling circuit 12.
At step 6, data is transmitted.

The cell conversion circuit 12 converts the received serial data into an ATM cell format. Multiplex / competition part 3
Outputs the data to the ATM network in synchronization with the network clock sequentially from the cell which has issued the earliest request among the cell transmission circuits 12, 22 and 32.

FIG. 5 is a block diagram showing another embodiment of the present invention. In this embodiment, the second clock 215 and the like generated by the clock generation circuit 214 and the like are supplied to the terminal. The second clock 215 is set at a constant period based on the shaping speed information for each logical path, similarly to the second clock 16 in FIG.

From the terminal side, serial data 213 synchronized with the second clock 215 is input to the celling circuit 212. That is, the serial data 213 is the second clock 2
15, the required clock rate has already been attained, so that the speed conversion unit 11 in FIG. 1 becomes unnecessary. Subsequent processing is the same as in the embodiment shown in FIG.

[0028]

According to the present invention, the serial data corresponding to each logical path is replaced by a clock synchronized with the contract band of the network at the time of reception.
Does not require a shaping function. As a result, by switching to a clock speed that can guarantee the band when receiving serial data, the cell generation interval is inevitably constant, so only the clock generation circuit is needed as a means for shaping. This has the effect of simplifying the shaping circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a detailed block diagram of a main part of the embodiment shown in FIG.

FIG. 3 is a diagram for explaining a function of an enable signal shown in FIG. 1;

FIG. 4 is a diagram showing input data and output data of a FIFO in the embodiment shown in FIG. 1;

FIG. 5 is a block diagram of another embodiment of the present invention.

[Explanation of symbols]

1,201 control unit 2,202 control bus 3,203 multiplexing / competition unit 11,21,31 speed conversion unit 12,22,32,212,222,232 celling circuit 13,23,33,213,223,233 Serial data 14, 24, 34, 214, 224, 234 Clock generation circuit 15, 25, 35, 225, 235 First clock 16, 215 Second clock 101 Information table 102 CPU 111 Flag detection circuit 112 FIFO 113 Enable signal 121 S / P conversion circuit 122 Cell header generation circuit 141 Counter 142 Offset setting register

Claims (6)

[Claims] 1. A shaping circuit for connecting a terminal having no ATM user network interface to an ATM network, generates a clock synchronized with a contract band for each logical path, and converts serial data carried on this clock into cells. A shaping circuit characterized in that: 2. A clock generating circuit for generating a second clock synchronized with a contract band for each logical path, and receiving serial data from the terminal with a first clock synchronized therewith and sending out the serial data with the second clock. 2. The shaping circuit according to claim 1, further comprising a speed conversion unit, and a cell conversion circuit for converting the transmitted serial data into an ATM cell format. 3. A clock generating circuit for generating a second clock synchronized with a contract band for each logical path and supplying the second clock to the terminal, receiving serial data synchronized with the second clock from the terminal, and generating an ATM cell format. 2. The shaping circuit according to claim 1, further comprising a cell conversion circuit for converting the data into a signal. 4. An information table storing shaping speed information for a contracted bandwidth for each logical path, and a control unit including a CPU for reading out the shaping speed information from the information table and sending it to the clock generation circuit. The shaping circuit according to claim 2 or 3, wherein 5. The clock generating circuit comprises an offset setting register for setting and storing a count value for a contract bandwidth for each logical path, and a counter for counting the count value and generating the second clock. The shaping circuit according to any one of claims 2 to 4, wherein the shaping is performed. 6. A flag detecting circuit for detecting a flag indicating a valid data range from the serial data and outputting an enable signal, the speed conversion unit receiving the serial data only while the enable signal is being input. FI that is output to the cell circuit in synchronization with the second clock
6. The shaping circuit according to claim 2, wherein the shaping circuit comprises an FO.