JP2521368B2 - Packet adapter device for ATM - Google Patents

Description

The present invention relates to a packet adapter device for ATM connected to an ATM (Asynchronous Transfer Mode) network, and to an improvement in transmission technology to the ATM network.

[Conventional technology]

As a multiplexing method in communication, there are a time division multiplexing method in which information is multiplexed in a time division manner such as circuit switching, and a statistical multiplexing method in which information is asynchronously multiplexed at an arbitrary timing. Recently, one of the latter methods, ATM ( A synchro
nous T ransfer M ode: asynchronous transfer mode) system has been attracting attention. As described above, the ATM system has a merit that it is efficient because it uses a line only when information is generated. However, only when information is generated, that is, when sending or multiplexing information in accordance with the amount of information generated, but when an infinite amount of information occurs, the ATM multiplexer or ATM switch that receives the information is I can not cope. Therefore, in reality, when setting up a call, the terminal declares the maximum throughput of the amount of data sent from the terminal itself (the maximum value of the amount of information per unit time), and the receiving side such as the ATM switch side processes the throughput. The call control sequence is such that the call is accepted when possible. That is, the terminal sends information according to the amount of information generated within the range of the maximum throughput or less.

Figure 6 shows, for example, the IEICE Spring National Convention (1989
FIG. 19 is a block diagram showing a configuration of a transmission system of a conventional ATM packet adapter device as shown in B-366 “Hardware configuration of in-house ATM experimental machine”. In the figure, 1 is ATM
It is a packet adapter device. The ATM packet adapter device 1 has a function of disassembling / assembling cells so that terminals 6a to 6c not having an ATM interface can be connected to an ATM network, and having a function of multiplexing a plurality of terminals on one ATM line. ing.

In the ATM packet adapter device 1, the data sent from the terminals 6a to 6c not having an ATM interface are individually received by the cell assembling parts 3b to 3d, and the data are converted into cells of 48-byte length according to the ATM format. A 5-byte ATM header indicating the destination address is added. The cellized cell data is given to the transmission FIFO units 2b to 2c and temporarily stored there. On the other hand, the call control sequence described above is executed by the call control unit 4. That is, each of the terminals 6a to 6c notifies each cell assembling unit 3b to 3d of a call request before sending data, and the call request is transmitted to the call control unit 4 via the control bus 8. Here, the maximum throughput of each terminal 6a to 6c is predetermined for each terminal, and the call control unit 4 recognizes the terminal that has made a call request, determines the maximum throughput, and based on the call request, Cell assembly section 3a, transmission FIFO section 2
a, Call control is performed with the ATM network via the multiplex bus 7 and the line I / F unit 5, and the maximum throughput is set. The call control unit 4 is determined by the call control unit 4 at the time of call control via the control bus 8.
Various parameters including the ATM header are given to the cell assembling units 3a to 3d.

The cell data transmitted from the transmission FIFO units 2b to 2d are given to the multiplex bus 7 to be multiplexed, interfaced with the ATM network by the line I / F 5, and transmitted to the ATM network.

FIG. 7 is a block diagram showing the configuration of the transmission FIFO unit 2. In the figure, 9 is a FIFO that temporarily buffers the cells sent from the cell assembling unit 3, and writing in the FIFO 9
The read control is performed by the FIFO write control unit 11 and the FIFO read control unit 12. When the cell data is given from the cell assembling section 3, the FIFO write control section 11 detects the cell data and gives a read signal WR to the FIFO 9 and gives a FIFO data present signal DP to the multiplex bus control section 13. The multiplex bus control unit 13 performs arbitration (arbitration) control on the multiplex bus 7, issues a bus request (bus use request signal) BR to the multiplex bus 8, and responds to it by issuing a bus grant (bus use). (Approval signal) When BG is given, read start signal RDS is changed to FIF
O It is given to the read control unit 12. When the reading is completed, the FIFO
The read completion signal RDC from the read controller 12 is transmitted to the multiplex bus controller 1
Sent to 3.

Next, the operation of the conventional ATM packet adapter device configured as described above will be described. FIG. 8 is a timing chart of the reading operation of FIFO9.

The data sent from the terminals 6a to 6c are respectively stored in the cell assembling unit 3b.
It is input to ~ 3c, and it is made into cell data of 48 bytes which is the data length of ATM cell, and ATM of 5 bytes is further added to it.
A header is added. After being made into cells, the cell data is sent to the respective transmission FIFO units 2b to 2d, and is temporarily written in the FIFO 9 by the FIFO write control unit 11.

When data is written to the FIFO9, the FIFO write control unit 11
The IFO data present signal DP “L” is output to the multiplex bus control unit 13. The multiplex bus control unit 13 outputs the bus request BR “L” to the multiplex bus 7 when receiving the FIFO data present signal DP “L”, and then receives the bus grant BG “L” from the multiplex bus 8 to read the FIFO. The read start signal RDS “L” is output to the control unit 12. Upon receiving the read start signal RDS "L", the FIFO read controller 12 starts reading cell data from the FIFO 9 based on the read start signal RDS "L".

The FIFO read control unit 12 outputs a read completion signal RDC “L” to the multiplex bus control unit 13 at the timing when the reading of the cell data for one cell from the FIFO 9 is completed. Multiplex bus controller 13
Is a bus request BR based on the read completion signal RDC “L”
Output "L". Thereafter, the cell data is read from the FIFO9 in the same procedure.

On the other hand, when there is no cell data in the FIFO9, the FIFO data present signal DP becomes "H" and reading is not performed.

As described above, the multiplex bus control unit 13 changes the FIFO data presence signal DP from “H” to “L” and when the FIFO data presence signal DP is “L”.
The bus request BR “L” is output when the read completion signal RDC becomes “L” during the period.

The cell data sent from the transmission FIFO unit 2 to the multiplex bus 7 is input to the line I / F unit 5, where it is converted from electricity to light and the cell data is output to the ATM network.

[Problems to be Solved by the Invention]

However, in the conventional ATM packet adapter device, the data cannot be sent from the FIFO to the multiplex bus due to the congestion of the multiplex bus caused by the output of data from multiple terminals at the same timing, and the data is temporarily sent to the FIFO of the transmission FIFO unit. When a plurality of cell data are accumulated and read continuously from the FIFO when the congestion is released, cell data having a throughput of about 153 Mbps is sent to the multiplex bus. FIG. 9 is a diagram for explaining this, and shows the throughput when three cell data are continuously transmitted to the multiplex bus. Since the basic frequency of communication in the ATM network is set to 155.52 MHz, if 53 bytes of cell data are transmitted continuously at 1-byte intervals, the throughput will be Becomes Therefore, in the call control sequence, considering that cell data is sent out at once, the maximum throughput must always be set to 153 Mbps regardless of the maximum throughput of each terminal, and there is a problem that the line cannot be used effectively. It was That is, if the maximum throughput is set to 153 Mbps, even if data is actually sent from a terminal having a smaller throughput, the line will be occupied by the amount indicated by the set maximum throughput and other terminals will be occupied. Therefore, the data in the meantime cannot be transmitted.

The present invention has been made to solve the above problems, and sets an arbitrary throughput by setting and controlling the transmission interval of cell data based on the maximum throughput of cell data transmitted to the ATM network. And efficiently
An object is to provide an ATM packet adapter device that can use an ATM line.

[Means for solving the problem]

An ATM packet adapter device according to the present invention is a cell assembly unit that is connected to an ATM network, determines the maximum throughput of data transmitted from a plurality of terminals, and converts the data into cells of a predetermined length according to the ATM format. In the ATM packet adapter device, the cell assembling unit is provided, which comprises: and transmitting means for transmitting the cellized data of each terminal to a multiplex bus based on a set transmission interval for multiplexing and transmitting to the ATM network. And a call control unit that is provided to provide control information in the transmission unit and that determines the number of clocks of the transmission interval corresponding to the determined maximum throughput, and the cellized data of the cell based on the number of clocks determined by the call control unit. And a transmission interval setting means for setting the transmission interval.

[Action]

According to the present invention, the transmission interval calculated based on the maximum throughput determined in relation to the terminal that has made the call request in the call control sequence is set, and the cellized data is transmitted at the set transmission interval. To be done. Therefore, the transmission of data is always less than or equal to the maximum throughput, and the maximum throughput can be arbitrarily changed for each terminal, so that the line can be effectively used.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings showing an embodiment thereof. FIG. 1 is a block diagram showing a configuration of a transmission system of an ATM packet adapter device according to the present invention. The ATM packet adapter device 1 of the present invention disassembles / assembles a plurality of terminals 6a to 6c having no ATM interface so that they can be connected to an ATM network, and multiple terminals 6a to 6c are multiplexed on one ATM line. It has a function to do.

In the ATM packet adapter device 1, the cell assembling units 3b to 3d individually receive the data sent from the terminals 6a to 6c having no ATM interface, and the cell assembling into 48 byte length cell data according to the ATM format. Then, a 5-byte ATM header indicating the destination address is added. Cellized cell data is transmitted from the transmission FIFO unit 2b to
Given to 2d, where it is temporarily stored. On the other hand, the call control sequence described above is executed by the call control unit 4. That is, each of the terminals 6a to 6c notifies each cell assembling section 3b to 3d of a call request before sending data, and the call request is transmitted to the call control section 4 via the control bus 8. Here, each terminal 6a-6c
The maximum throughput of is predetermined for each terminal,
The call control unit 4 determines the maximum throughput by recognizing the terminals 6a to 6c that have issued the call request.

The call control unit 4 receives the call request from the cell assembly unit 3a and the transmission FI.
When the maximum throughput for the call request is declared to the ATM network via the FO unit 2a, the multiplex bus 7, and the line I / F unit 5, and when it is accepted, it is set as the maximum throughput.

Also, the call control unit 4 transmits various control information including the ATM header set at the time of call control via the control bus 8 to the cell assembling unit 3a.
To 3d and the transmission FIFO units 2a to 2d.

The cell data from each of the terminals 6a to 6c sent from the transmission FIFO units 2b to 2d is given to the multiplex bus 7 to be multiplexed,
The I / F unit 5 interfaces with the ATM network and sends it to the ATM network.

FIG. 2 is a block diagram showing the configuration of the transmission FIFO unit 2.

In the figure, reference numeral 9 is a FIFO for temporarily buffering the cell data sent from the cell assembling unit 3. The FIFO control unit 11 and the FIFO read control unit 12 control writing and reading in the FIFO 9. When the cell data is given from the cell assembling section 3, the FIFO write control section 11 detects the cell data and gives a read signal WR to the FIFO 9 and gives a FIFO data present signal DP to the multiplex bus control section 13. The multiplex bus control unit 13 performs arbitration (arbitration) control on the multiplex bus 7, issues a bus request (bus use request signal) BR to the multiplex bus 8, and responds to it by issuing a bus grant (bus use). (Approval signal) When BG is given, read start signal RDS is changed to FIF
O It is given to the read control unit 12.

Further, the transmission interval control unit 10 of the transmission FIFO unit 2 includes the call control unit 4
From the control bus 8 to the setting value of the transmission interval, each transmission FIFO
Control information such as address data and control data of the unit 2 is sent.

The communication interval control unit 10 controls the transmission interval of cell data at the time of sending to the multiplex bus 7 to a set value or more, and a control bus I / F unit 14 for interfacing with the transmission bus 8.
The transmission interval setting register 15 that latches the setting value included in the control information and the transmission interval counter 16 that counts down the set value as an initial value. A read completion signal RDC is given from the FIFO read control unit 12 to the transmission interval counter 16, and down counting is started at the input timing. When the transmission interval counter 16 finishes counting, it outputs a count zero signal CZ indicating this to the multiplex bus controller 13.

FIG. 3 is a block diagram showing the configuration of the transmission interval control unit 10. Here, the control bus 8 comprises an 8-bit data bus for transmitting various control data, a 16-bit address bus for transmitting the address of each element in the ATM packet adapter device 1 and a control bus for transmitting a control signal. In the transmission interval control unit 10, the call control unit 4 is connected via the data bus.
From this, a set value based on the maximum throughput is given to the transmission interval setting register 15. Further, an address is given to the address comparator in the control bus I / F unit 14 via the address bus. Further, a control signal is given to the control bus control unit 18 via the control bus. The address comparator 17 compares the given address with its own address, detects whether or not the own transmission FIFO unit 2 is designated, and when detected, gives a match signal MS to the control bus control unit 18.
The control bus control unit 18 causes the transmission interval setting register 15 to send the data latch signal DL based on the coincidence signal MS and the control signal CS.
Is output. The transmission interval setting register 15 latches the set value given via the data bus at the input timing of the data latch signal DL.

Next, the operation of the ATM packet adapter device of the present invention thus configured will be described. FIG. 4 is a timing chart of transmission of cell data to the multiplex bus 7, and FIG. 5 is a diagram showing a relationship between transmission intervals and throughput.

When the terminals 6a to 6c make a call request, the call control unit 4 declares the maximum throughput to the ATM network through the cell assembling unit 3a, the transmission FIFO unit 2a, the multiplex bus 7, and the line I / F unit 5, and the other side calls. Set the maximum throughput declared to accept as the maximum throughput during transmission.

The operation up to this point is the same as the conventional one. The difference from the conventional example is that the set value of the transmission interval is set based on the maximum throughput, and the transmission interval is controlled by the set value. As a result, the maximum throughput can be reduced according to the throughput of the terminal, and the line can be used efficiently.
That is, when the maximum throughput is set, the set value of the transmission interval is set accordingly. For example, the maximum throughput is 7
In the case of 7.76 Mbps, as shown in Fig. 5 (a), the transmission interval is
Since it is 53 clocks, the set value is set to "52", and when the maximum throughput is 38.88 Mbps, the transmission interval is 159 clocks as shown in FIG. 5B, so the set value is set to "158". Here, if the maximum throughput is TP and the clock of the transmission interval is S, Is required. The call control unit 4 sets the set value by the number obtained by subtracting 1 from the obtained clock S.

For example, when the maximum throughput of the terminal 6a is set to 77.76 Mbps, it is necessary to set the clock S of the transmission interval to a minimum of 53 clocks as shown in FIG. 5 (a). In that case, the call control unit 4 sets "52" as the set value of the transmission interval to the transmission interval control unit 10.

Specifically, the call control unit 4 outputs the control bus address of the transmission FIFO unit 2b to the address bus of the control bus 8. Control bus
The address comparator 17 in the I / F unit 14 detects that the address addressed to itself is output, and outputs the coincidence signal MS to the control bus control unit 18. The control bus control unit 18 uses the control signal CS of the control bus to output the write command of the set value of the current transmission interval and
By detecting MS, the data latch signal DL is output to the transmission interval setting register 15. At this time, since the set value "52" of the transmission interval is output to the data bus of the control bus 8, "52" is set in the transmission interval setting register 15.

Next, the flow of cell data will be described. The data output from the terminal 6a is converted into 48-byte data by the cell assembling unit 3b and added with a 5-byte ATM header. The cell data output from the cell assembling unit 3b is written in the FIFO 9 in the transmission FIFO unit 2b by the FIFO write control unit 11.

The FIFO write control unit 11 outputs the FIFO data present signal DP to the multiplex bus control unit 13, and the multiplex bus control unit 13 outputs the bus request BR.
/ Sends cell data to the multiplex bus 7 through the sequence of bus grant BG.

When the cell data sent from the FIFO 9 is completed, the read completion signal RDC “L” is sent from the FIFO read controller 12 to the transmission interval controller 1
It is output to the load input of the transmission interval counter 16 of 0.

At that time, the transmission interval counter 16 loads the set value “52” latched in the transmission interval setting register 15 as load input data and starts down counting.

The transmission interval counter 16 outputs the count zero signal CZ to the multiplex bus control unit 13 when the down count value becomes "0", and the multiplex bus control unit 13 outputs the bus request BR / buscrant BG by the count zero signal CZ "L". The cell data is transmitted to the multiplex bus 7 through the sequence of. After that, the line I / F unit 5 converts the electric signal into an optical signal and transmits it to the ATM network.

In this embodiment, the transmission interval control unit is configured by a transmission interval counter, and the transmission interval control unit is configured to set a setting value for maximum throughput regulation and a setting value corresponding to the number of clocks in the transmission cell interval. However, it goes without saying that the transmission interval control unit may be configured by a transmission interval timer, and the transmission interval time may be set in the transmission interval control unit as a set value for maximum throughput regulation.

〔The invention's effect〕

As described above, in the present invention, the call control unit sets the number of clocks of the transmission interval corresponding to the maximum throughput set according to each terminal. It is possible to negotiate with the converter side, know the maximum throughput value that will be determined by the negotiation on the terminal, and set the proper maximum throughput value accurately, and set this in the transmission interval setting means. Since it has a transmission interval control unit, the multiplex bus is congested, even when the cell data is accumulated in the transmitting means, the cell data is transmitted to the multiplex bus at the transmission interval set after the congestion is released,
The throughput does not exceed the set maximum throughput. Therefore, you can always set the optimal throughput,
It has excellent effects such as efficient use of the line.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an ATM packet adapter device according to the present invention, FIG. 2 is a block diagram showing the configuration of a transmission FIFO unit, and FIG. 3 is a block diagram showing the configuration of a transmission interval control unit. FIG. 4 is a timing chart at the time of transmitting cell data, FIG. 5 is a diagram showing the relationship between transmission intervals and throughput, FIG. 6 is a block diagram showing the configuration of a conventional ATM packet adapter device, and FIG. 7 is a conventional diagram. 8 is a block diagram showing the configuration of the transmission FIFO unit of FIG. 8, FIG. 8 is a timing chart at the time of transmitting cell data in the conventional example, and FIG. 9 is a diagram showing throughput when cell data is continuous. 1 ... ATM packet adapter device 2, 2a to 2d ... transmission FIFO unit, 3a to 3d ... cell assembly unit, 4 ...
... Call control unit, 5 ... Line I / F unit, 6a to 6c ... Terminal, 7 ...
... Multiple bus, 9 ... FIFO, 10 ... Transmission interval control unit, 15 ...
... Sending interval setting register, 16 ... Communication interval counter In the drawings, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hiroshi Haseyama 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Within Nippon Telegraph and Telephone Corporation (72) Koichi Nakajima 5-1-1 1-1 Ofuna, Kamakura-shi, Kanagawa (56) References JP-A-4-835 (JP, A) JP-A-2-170645 (JP, A) Proceedings of the 1989 IEICE Spring National Convention (1989- 3) B-366, "Hardware configuration of ATM experimental machines in companies"

Claims (1)

(57) [Claims] 1. A maximum throughput of data transmitted from a plurality of terminals connected to an ATM network is determined, and the data is AT
A cell assembling unit for cellizing into a predetermined length of data in accordance with the M format, and transmitting data of each cellified terminal to a multiplex bus based on a set transmission interval for multiplexing,
In an ATM packet adapter device comprising a transmitting means for transmitting to an ATM network, a call which is provided to provide control information in the cell assembling section and the transmitting means and which determines a clock number of a transmission interval corresponding to a determined maximum throughput An ATM packet adapter device comprising: a control unit; and a transmission interval setting means for setting a transmission interval of cellized data based on the number of clocks determined by the call control unit.