JPH04835A - Cell transmission controller - Google Patents

Abstract

PURPOSE:To prevent instantaneous quality deterioration of an ATM network by making a cell assembling means to assemble data into a cell and output a cell sending-out requesting signal to a cell transmission controlling means upon receiving transmission data to be sent to the ATM network and the cell transmission controlling means to control the cell transmission. CONSTITUTION:A data buffer 11 immediately outputs a transmission requesting signal SD to a gate 12 upon assembling one or more cells S1-S3 out of the data (b) received from a transmitting section 6. Upon inputting these active outputs Q and the signal SD, the gate 12 sends a transmitting signal SG to the buffer 11 and another gate 13 and informs the buffer 11 of a transmission permit. At the same time, the gate 12 sets the gate 13 to a conducted state. Upon inputting the signal SG, the buffer 11 reads out the cell S1 synchronously to the signal SG and sends read-out results to the gate 13. The buffer 11 sends the transmission requesting signal SD to the gate 12 while the buffer accumulates the cells. Therefore, the remaining cells S2 and S3 accumulated in the buffer 11 are read out synchronously to a clock pulse CP.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a cell transmission control device, more specifically an ATM (
Asynchronous Transfer Mode
) relates to a circuit for limiting the amount of transmitted data in A-M terminals connected to a network;

(Prior Art) In recent years, there has been an increasing demand for various media communications such as high-speed data communications and image communications. For example, "Trends in rATM communication technology" by Kawarasaki et al., Journal of the Institute of Electronics, Information and Communication Engineers,
In Volume 71, No. 8 (August 1988), an ATM network is described as a communication network that provides high-speed and flexible communication services that satisfy such user demands.

An ATM network is an asynchronous communication switching network that integrally processes various types of traffic such as voice, data, and image traffic having different information speeds and eight-speed characteristics. In other words, in the ATM network,
Since information is divided into fixed-length blocks (hereinafter referred to as cells) and then statistically multiplexed and transmitted, a flexible communication network can be constructed. Specifically, since the information generated at the terminal is processed by statistical multiplexing, variable rate is possible, and information transfer according to the amount of information at that time is possible. Therefore, compared to conventional fixed channels, the average transmission rate of information transfer can be reduced with the same quality. Furthermore, in the ATM network, a self-routing principle is introduced in order to perform switching processing for each cell that arrives asynchronously.

(Problem to be solved by the invention) However, such AT>! In networks, collisions on the same route occur due to asynchrony, and cell discards or transfer delays occur due to waiting. These vary widely depending on the traffic characteristics of calls accommodated in the ATM network, and it is difficult to clearly evaluate the traffic characteristics within the network. Therefore, due to the nature of the traffic handled within the network, there is the burst characteristic of cells sent from terminals as a technical problem that must be solved. That is,
Even if the long-term average rate is the same, if the statistical multiplexing effect in the network is impaired due to the superposition of burst traffic, cells will be discarded or transfer delays will occur, resulting in instantaneous transmission. There was a problem that the quality became unsatisfactory.

The present invention eliminates the drawbacks of the prior art, and by defining the traffic characteristics of subscriber terminals in an ATM network, transmission control of ATM terminals is performed so that cells within a predetermined amount are transmitted within the ATM network. An object of the present invention is to provide a cell transmission control device that performs the following.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a cell transmission control device that is applied to an ATM terminal that is connected to an ATM network and sends out cells to the ATM network. pulse generating means for generating clock pulses with a period corresponding to the burst characteristics of the cell; cell assembly means for receiving transmission data to be sent to the ATM network, accumulating the transmission data and assembling it into cells; and inputting clock pulses from the pulse generation means. It also has cell transmission control means that receives a cell transmission request signal from the cell assembly means and performs transmission control to transmit cells to the ATM network at intervals longer than a predetermined interval.

(Function) When the cell assembling means receives transmission data to be sent to the ATM network, it assembles this data into cells and outputs a cell transmission request signal to the cell transmission control means. When the cell transmission control means receives the cell transmission request signal, it performs cell transmission control in synchronization with the clock pulse from the pulse generation means.

(Example) Next, an example of a cell transmission control device according to the present invention will be described in detail with reference to the accompanying drawings.

In an ATM network, the burst interval BT of the parse interval B illustrated in FIG. 4 is defined by the terminal, but the cell transmission interval t in the heast B is not defined. Therefore, cells are transmitted continuously. In some cases, cell bursts may occur within the ATM network.

An embodiment of the present invention divides the burst characteristics of terminal equipment in an ATM network into classes, regulates cell transmission intervals in accordance with the classes, and prevents bursts within the network. This embodiment is a circuit that regulates the minimum cell transmission interval of a terminal according to the subscriber class of the terminal in an ATM network.

FIG. 1 shows a 57M network terminal device connected to an ATM highway and including an embodiment of the cell transmission control device of the present invention. It is composed of an ATM network terminal device transmitting unit 6 and a cell transmission control device IO, and a cell transmission control device 1
0 is arranged between the transmitter 6 and the ATM highway 8. The ATM network terminal device 1 is.

For example, it is a data terminal that handles image information, etc., and the cell transmission interval corresponding to the cell transmission burst characteristics is set by the cell transmission control device IO.

The cell transmission control device IO is composed of a data buffer 11, gates 12 and 13, a flip-flop 14, a cell transmission determination circuit 16, and a clock generation circuit 18. The data buffer 11 is an assembly circuit that is connected to the transmitter 6 via an output data line, temporarily stores output data b sent from now on, and assembles this into cells that are fixed length information. After assembling a cell from the data b, the buffer 11 outputs a transmission request signal SD to the gate 12. When the buffer 11 receives the transmission signal SG, it outputs the assembled cells to the gate 13 via the output 100.

The buffer 11 is also connected to the transmitter 6 via an input permission signal line a. When the buffer 11 becomes full of stored data, it turns off the input permission signal a and stops inputting data from the transmitter 6.

The gate 13 has an output terminal connected to the ATN highway 8 and a control input terminal connected to the output of the gate 12. game)
13 is a three-state driver that outputs the cells assembled in the data buffer 11 to the ATN highway 8 via the output 102 when the transmission signal SG from the gate 12 is in the ON state.

The transmission clock generation circuit 18 is a preset type counter that receives a clock CLK having a period T as shown in FIG. 3 and divides the frequency thereof. That is, the clock generating circuit 18 is capable of generating pulses with a period of 2T to 6 pulses corresponding to the class input Cl-C5, and one clock pulse CP selected from among the pulses is outputted to the two-lip-flop 14. Therefore, for example, by setting the period T of the clock CLK as the cell length, the cell interval can be varied within a range of 2 to 6 times the cell length using the class input C1-05. However, the data transmission speed is set higher than the data input speed from the transmitter 6.

The flip-flop 14 is a circuit that stores the claw and pulse CP output from the clock generation circuit 18.

That is, the flip-flop 14 has its set terminal S connected to the output side of the clock generation circuit 18, its reset terminal R connected to the output side of the cell sending determination circuit 16, and its output terminal Q connected to the gate 1.
2 input terminals, respectively. When the pulse CP is input to the set terminal S of the flip-flop 14,
The output Q connected to the gate 12 is activated. The flip-flop 14 also resets the active output Q when the cell transmission completion signal SE is input from the cell transmission determination circuit 16 to the reset terminal H.

The gate 12 has one input terminal connected to the data buffer 11 and the other input terminal connected to the output terminal Q of the flip-flop 14. Game [2 is the transmission request signal SD
This is a logic circuit that outputs a transmission signal SG to the control terminal of the gate 13 when it receives the output Q in the active state. The cell transmission determination circuit 16 is a signal delay circuit that determines the end time of cell transmission by receiving the transmission signal SG, and sends a cell transmission completion signal to the flip-flop 14.

Next, an example of the operation in this embodiment will be explained using the time chart shown in FIG. When the pulse CP is input to the set terminal S, the flip-flop 14 makes the output terminal Q active and outputs it to the gate 12. On the other hand, when the data buffer 11 assembles one or more cells 51 to S3 from the data b received from the transmitter 6, it immediately outputs a transmission request signal SD to the gate 12. The gate 12 receives these active outputs Q and the transmission request signal S.
When D is input, a transmission signal SG is sent to the buffer 11 and the gate 13, notifying the buffer 11 of permission for transmission, and making the gate 13 conductive.

When the data buffer 11 receives the transmission signal SG, it reads out the cells in synchronization with this and sends them to the gate 13. In other words, the cells 5l-S stored in the data buffer 11 are read out and sent to the gate 13.
3, the cell Sl is first outputted to the highway 8 via the gate 13. The cell transmission determination circuit 16 determines whether transmission of the cell St has ended by inputting the transmission signal SG. That is, the cell transmission determination circuit 16 determines whether the transmission signal S
After a certain period of time after inputting G, a cell sending completion signal SE is output to the reset terminal H of the flip-flop 14 to reset it.

Data buffer 11 sends a transmission request signal SD to gate 12 while storing cells. As a result, the remaining cells S2 and S3 stored in the buffer II are read out in synchronization with the clock pulse CP.
1, when there are no accumulated cells, the transmission request signal SD
Turn off to end cell transmission. When the buffer 11 receives data b of cells S4 to S6 again from the transmitter 6,
Buffer 11 outputs a transmission request signal SD and transmits cell S4 in synchronization with clock pulse CP in the same way as cell 5t-53.
~S5 is sent to the gate 13.

In this way, according to this embodiment, even if data consisting of a plurality of cells is input into the buffer 11 at once, these cells can be output at predetermined intervals synchronized with the period of the clock pulse CP. .

In this embodiment, the subscriber class is class C1-05, and it is assumed that any one of them can be used as a finger, but the present invention is not particularly limited to this. The number of subscriber classes may be greater or less than this, and may be fixed at l subscriber classes.

Furthermore, the clock generation circuit 18 may input the clock GLK or may have a built-in clock source. Furthermore, by creating the clock generation circuit 18 at a timing independent of the ATM network, data transmission events with other transmission circuits can be made independent.

(Effects of the Invention) As described above, according to the present invention, information sent from a subscriber terminal is sent out on the ATM highway at intervals that are predetermined due to its nature. As a result, the minimum inter-burst cell interval on the ATM highway is managed, eliminating burst transmissions that cause cell discard or transfer delays, and network resources in the ATM network are appropriately allocated. Therefore, it is possible to prevent instantaneous deterioration of network quality due to superimposition of burst traffic.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the cell transmission control device according to the present invention, FIG. 2 is a time chart showing the operation of the embodiment shown in FIG. 1, and FIG. FIG. 4 is an explanatory diagram of a cell burst section in an ATM network. Explanation of symbols of important parts 1... ATN network terminal device 691. Transmitting unit 8, , ATM highway 10, . 11. +2,13 14. 16. 18. , cell transmission control device data buffer, gate flip-flop cell transmission judgment circuit, clock generation circuit Patent applicant: Oki Electric Industry Co., Ltd. Representative: Takao Katori, Takao Maruyama, time number 1, 1st 7th occurrence of rule fishing cloth ρ1

Claims (1)

[Claims] An AT that is connected to an ATM network and sends cells to the ATM network.
In a cell transmission control device applied to an M terminal, the device includes: pulse generation means for generating a clock pulse with a period corresponding to the burst characteristic when the ATM terminal transmits cells; and a pulse generation unit for receiving transmission data sent to the ATM network. , cell assembling means for accumulating the transmission data and assembling it into cells; receiving a clock pulse from the pulse generating means and receiving a cell sending request signal from the cell assembling means;
A cell transmission control device comprising cell transmission control means for performing transmission control to send out the cells to the ATM network at intervals longer than a predetermined interval.