KR940003245A

KR940003245A - ATM (Asynchronous Transfer Mode) Layer Function Processing Unit for User-Network Interface (UNI) of Broadband Telecommunication Network (B-ISDN)

Info

Publication number: KR940003245A
Application number: KR1019920011799A
Authority: KR
Inventors: 김경수; 박찬; 최문기; 신영석
Original assignee: 양승택; 재단법인한국전자통신연구소
Priority date: 1992-07-02
Filing date: 1992-07-02
Publication date: 1994-02-21
Also published as: KR950008217B1

Abstract

본 발명은 광대역 종합정보통신망(B-ISDN)의 구성요소인 ATM(Asynchronous Transfer Mode)망 노드, 망종단 장치 및 단말 접속 장치 등에 공통으로 사용될 수 있는 ATM프로토콜 중 ATM계층 기능 처리 장치에 관한 것으로서 특히, B-ISDN 사용자-망간의 인터페이스에서의 ATM 계층 기능 처리장치에 관한 것으로, 하나의 서비스 보드에 접속을 제공하는 기본되는 ATM 프로토콜의 ATM 계층 기능을 수행하는 처리 장치이므로 광대역 종합정보통신망을 구축하는데 있어 하나의 칩으로 구현시 가입자의 증가에 따른 확장이 용이하다. 그리고, 물리계층의 기능과 ATM 계층 기능처리 장치의 회로가 프로세서와 같이 하나의 보드로 구성되어 광대역 종합통신망의 장치들의 어느곳에나 탑재되도록 함으로써 통신 시스템 구현에도 용이성을 제공할 수 있다. 또한, 망 종단장치의 경우에는 ATM 계층 처리장치를 VLSI화하여 물리적인 링크당 ATM 계층기능처리장치의 기능의 프로토콜 칩을 배치하고 이것을 다시 ATM 다중화함으로써 구성이 가능하므로, 앞으로 도래할 광대역 망의 핵심 부품이다.The present invention relates to an ATM layer function processing apparatus among ATM protocols that can be commonly used in Asynchronous Transfer Mode (ATM) network nodes, network termination devices, and terminal access devices, which are components of a broadband integrated telecommunication network (B-ISDN). The present invention relates to an ATM layer function processing device at an interface between a B-ISDN user-network and a processing device that performs an ATM layer function of an underlying ATM protocol that provides access to a service board. Therefore, when implemented as a single chip, it is easy to expand as the number of subscribers increases. In addition, since the functions of the physical layer and the circuit of the ATM layer function processing apparatus are configured as a single board such as a processor, they may be mounted on any of the devices of the broadband integrated communication network, thereby providing the ease of implementing the communication system. In addition, the network terminator can be configured by VLSI of the ATM layer processor to arrange the protocol chip of the ATM layer function processor per physical link and multiplex the ATM layer again. Parts.

Description

ATM (Asynchronous Transfer Mode) Layer Function Processing Unit for User-Network Interface (UNI) of Broadband Telecommunication Network (B-ISDN)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 B-SID의 ATM 프로토콜의 기준모델 예시도.1 is a diagram illustrating a reference model of an ATM protocol of B-SID.

제2도는 ATM 계층 기능 처리부의 개략적 기능클럭도2 is a schematic functional clock diagram of an ATM layer function processing unit

제3도는 연결 설정 기능블럭과 연결 해제 기능블럭도.3 is a connection establishment function block and a connection release function block.

제4도는 셀구성 기능블럭도 셀송신 기능블럭도.4 is a cell configuration function block and a cell transmission function block.

제5도는 셀수 신 기능블럭도.5 is a cell reception function block.

제6도는 제어 레지스터와 상태 레지스터의 피트포맷 예시도6 is a diagram illustrating a fit format of a control register and a status register.

Claims

Asynchronous Transfer Mode (ATM) ATM AAM (Asyndhr onous Transfer), which is connected to the VME bus interface (7) that is in charge of the interface with the layer management entity, and receives the status information and control information through the VME bus interface (7). Mode Operation Administration & Maintenance) A connection that receives a connection release request signal from the connection setup function block 1 and the ATM OAM function block 3, which receives a connection setup request signal from the function block 3 and the ATM OAM function block 3; A cell configuration function block 4 receiving a payload and a transmission request signal from the release function block 2 and the AAL (L3) layer, and a cell transmission function for receiving and transmitting buffer status information from the cell configuration function block 4; An ATM layer function processing apparatus for a user-network interface of a broadband integrated information network (B-ISDN), comprising a block (5) and a cell receiving function block (6).

2. The different ATM OAM function block (3) according to claim 1, wherein the different ATM OAM function block (3) includes a control register (32) which issues a command to request connection establishment from a management plane, and an OAM processing section (33) which receives a command from the control register (32). And an ATM OAM function block (3) composed of a status register (31) connected to the AOM processor (33) to confirm to a layer management entity (L6). ATM layer function processing device for a user-to-network interface.

The method of claim 1, wherein the connection establishment function block 1 connects an ATM layer connection termination identifier (ATM-CI), an ATM link identifier (VPI / VCI), a physical layer connection endpoint identifier (PHY-CI), and a connection parameter. At the same time as the request signal, the parameter setting unit (11) which is connected to the association setting unit (11) which is born first from the hierarchical organ object (L6) and the association setting unit (11), generates a confirmation signal for parameter and associated resource initialization and setting termination ( 12) and a connection establishment control unit 13 for controlling the association establishment unit 11 and the parameter initialization unit 12 according to the connection establishment request from the connection door layer management object L6. ATM layer function processing apparatus for user-network interface of a broadband integrated information network (B-ISDN).

The connection release function block (2) according to claim 3, wherein the connection release function block (2) is disconnected from the connection parameter deletion unit (21) that receives a connection release request signal from the ATM OAM function block (3) and the ATM OAM function block (3). ATM layer function for the user-network interface of the B-ISDN, comprising a resource release unit 22 for giving a completion signal and a connection release control unit 23 for controlling the mechanism. Processing unit.

The method of claim 1, wherein the cell configuration function block (4) and the cell transmission function block (5) are configured to receive 8-bit data through the ATM OAM function block (3) connected to an ATM layer management function object. A second transmission data buffer 42 that receives 8-bit data through an interface between the first and third transmission data buffers 41 and 43 and the AAL layer, and receives an input from the ATM OAM function block 3D. Dirk the logic to send write control signals to the first, second and third transmission data buffers 41 and 43 and receive buffer status information from the first, second and third transmission data buffers 41 to 43. The first write control unit 401 and the interface block input to the AAL layer and receive a control signal to the second transmission data buffer 42 to transmit the first and third transmission data buffers 41. A second write control unit 402 incorporating decoder logic for receiving buffer state information at a second reference point 43; First and second write counters 403a and 403b for counting the number of writes from one write control unit 401, and a third write counter for counting the number of writes from the second write control unit 402 ( 403c, first, second, and third third header buffers 47 to 49 which receive an 8-bit data signal from the ATM layer management function entity and accept an output from the first write control unit 401; First and second third cell number counters 405a, 405b, and 405c which input counter decrement values from the respective first, second and third write counters 403a, 403b, and 403c; Signal cell counter (CN-SIG) and user service cell counter (CN-SD) signal and management cell, which are built into the buffer of the first, second and third cell counters (405a, 405b, 405c). The first, second, and third cell header buffers 47 to 49 are received by receiving a counter number CN-LM and receiving buffer status information from the second transmission data buffer 42. Transmits a header read control signal, transmits a cell read control signal to the first, second, and third transmit data buffers 41 to 43, receives a cell transfer request from the physical layer, and transmits a cell synchronization clock to the physical layer. Receives a cell read control signal from the cell transmission control unit 51 and the cell transmission control unit 51 and receives respective outputs from the first, second, and third transmission data buffers 41 to 43, respectively. And first, second, and third multiplexers 407a, 407b, and 407c which receive axial force from the second and third cell header buffers 47 to 49, respectively, and transmit the multiplexing hysteresis signals to the physical layer. First, second, and third reads that receive a cell diary control signal from the cell transmission control unit 51 and send a count increment value to the first, second, and third cell counters 405a, 405b, and 405c. A cell read control signal from the number counters 404a, 404b, 404c and the cell transmission control unit 51; First, a first cell for supplying signal cell header transmission control (HN-SIG), user service cell header transmission control signal (HN-SD), and optical cell header transmission control signal (HM-LM) to the cell transmission control unit 51. And a second and third cell header loss control unit (406a, 406b, 406c). An ATM layer function processing apparatus for a user-network interface of a broadband information communication network (B-ISDN).

6. The cell receiving function block (6) according to claim 5, wherein the cell receiving function block (6) comprises a cell receiving control unit (61) which receives a physical layer data indication signal, a cell clock and a byte clock from the physical layer interface, and a cell receiving control unit (61). A cell header comparator 63 which receives an input bit selection reject signal and a header comparison signal and receives an 8-bit data signal from the physical layer interface and transmits an idle state indication signal to the cell reception controller 61; A cell header buffer 64 which receives an output enable signal from 61 and outputs it to the cell header comparator 63; and an 8-bit data signal from the Murari layer interface; A payload buffer 62 for receiving a read / write enable signal from the cell reception control unit 61 and transmitting a buffer empty signal to the cell reception control unit 61, and writing / writing from the cell reception control unit 62. Receiving an enable signal and receiving an 8-bit data signal from the payload buffer 62. receiving a buffer selection signal from the cell header comparator 63 and delivering an ATM data receiving instruction signal to a VME bus interface; Receives a 3-cell receive buffer (44,46), a burner read / write enable signal to the cell receive processor (61), receives an 8-bit data signal from the payload buffer (62), and receives the cell header comparator (63). ATM layer for user-to-network interface of a B-ISDN, characterized in that it comprises a second cell receiving buffer (45) for receiving a buffer selection signal from the signal and transmit a new hole to the AAL layer interface unit. Function processing unit.

※ Note: The disclosure is based on the initial application.