JPH11298320A - Pll synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress spuriousness. SOLUTION: A phase comparator 102 samples a constant current during time corresponding to the phase difference of reference frequency division signals from a reference frequency divider 101 and comparison frequency division signals from a comparison frequency divider 106 in each phase comparison cycle and samples the constant current during the time corresponding to the difference of the reference frequency division signals and the phase difference immediately after the sampling. Then, immediately after the sampling, respectively sampled first and second currents are simultaneously held respectively. A charge pump 103 converts the respectively held first current and second current to a differential input voltage and outputs a differential output current corresponding to the obtained differential input voltage to a loop filter 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL synthesizer.

[0002]

2. Description of the Related Art As a PLL (phase locked loop) synthesizer used in a mobile communication device such as a portable telephone, the one shown in FIG. 5 is known. A PLL synthesizer as shown in FIG. 5 includes a voltage controlled oscillator (VCO) 6
05 is divided by the comparison frequency divider 606, and the phase difference between the phase of the obtained comparison frequency division signal and the phase of the reference signal from the reference frequency divider 601 is obtained by the phase comparator 602. A signal corresponding to the obtained phase difference is supplied to the charge pump 60.
3, the output is filtered by the loop filter 604, the VCO 605 is driven by the DC output from the loop filter 604, and the frequency and phase of the comparison frequency-divided signal are locked to the reference signal.

[0005] A phase comparator 602 shown in FIG. 5 is constituted by a logic gate, and includes a reference signal Ref and a comparison frequency-divided signal.
It operates in response to the rising edge of Slv. The frequency (fref) of the reference signal Ref and the comparison signal Slv
When the frequency (fslv) relationship is fref> fslv, for example, as shown in FIG. 6, the level of the output signal UP becomes H (high level) and the level of the output signal DW becomes L (low level). Become. When fref <fslv, for example, as shown in FIG. 7, the level of the output signal UP is L and the level of the output signal DW is H
become. Even when fref = fslv, the phase comparator 602
, The output signal UP and the output signal DW become hazards (whiskers), for example, as shown in FIG.

The charge pump 603 shown in FIG.
As shown in the figure, two FETs Mp
1 and Mn1 are connected in series, and when the level of the output signal UP of the phase comparator 602 becomes H, the FET Mp1 is turned on and current is supplied from the power supply to the loop filter 604. Is high, the FET Mn1 is turned on and the loop filter 604 is turned on.
Current is drawn from the

[0005]

However, when fref = fslv, a wide hazard (whisker) appears due to the propagation delay between the logic gates constituting the phase comparator 602. In some cases, the resulting hazards had an adverse effect on the phase noise or spurious characteristics of the system.

As a method for solving such a problem,
There is known a method in which the comparison frequency is set higher in the fractional frequency division method (Fractional N) than in the integer frequency division method, so that the spurious position on the frequency axis is farther from the oscillation frequency of the VCO. However, this method requires arithmetic processing, so that when this method is employed, there is a new problem that the circuit scale becomes larger than that of the integer frequency division method. In addition, even if this method is adopted, spurious components are only far away from the oscillation frequency of the VCO, and are not eliminated. It didn't work out.

An object of the present invention is to solve the above-mentioned problems and to provide a PLL synthesizer capable of suppressing spurious.

[0008]

A PLL synthesizer of the present invention divides an output from a voltage controlled oscillator by a comparison divider, and obtains a phase of an obtained comparison division signal and a reference from a reference divider. A phase difference from the phase of the signal is obtained by a phase comparator, a signal corresponding to the obtained phase difference is output by a charge pump, the output is filtered by a loop filter, and the voltage control is performed based on a DC output from the loop filter. In a PLL synthesizer that changes an oscillation frequency of an oscillator, the phase comparator samples a constant current for a time corresponding to a phase difference between the reference frequency-divided signal and the comparative frequency-divided signal for each phase comparison cycle. (1) when the constant current is changed according to a difference between the reference frequency-divided signal and the phase difference immediately after sampling by the first sampling means; And a first and second hold for simultaneously holding the first and second currents respectively sampled by the first and second sampling means immediately after sampling by the second sampling means. Means, wherein the charge pump comprises the first and second charge pumps.
Converting the first current and the second current respectively held by the holding means into a differential input voltage, and outputting a differential output current corresponding to the obtained differential input voltage to the loop filter. You.

The first sampling means samples a constant current for a time corresponding to a pulse width obtained by performing an AND operation on the level of the reference frequency-divided signal and the inverted comparison frequency-divided signal level of the comparison frequency-divided signal. Wherein the second sampling means samples the constant current for a time corresponding to a pulse width obtained by ANDing the level of the reference frequency-divided signal and the level of the comparison frequency-divided signal. Can be. Further, when the first current is less than the second current, the charge pump draws a difference current between the first current and the second current from the loop filter, and the first current is equal to the second current. If the first current exceeds the second current, the difference current between the first current and the second current may be supplied to the loop filter, and the current may not be output when the first current is equal to the second current.

The charge pump further includes a circuit for flowing a differential output current corresponding to the differential input voltage from a current source in addition to a circuit for flowing a differential output current corresponding to the differential input voltage. Can be superimposed.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
An embodiment will be described. In FIG. 1, reference numeral 101 denotes a reference frequency divider, which divides a signal from the reference oscillator 100. Reference numeral 106 denotes a comparison frequency divider for dividing the output from a voltage controlled oscillator (VCO) 105. Reference numeral 102 denotes a phase comparator, which performs an AND operation on the level of the reference signal Ref from the reference frequency divider 101 and the inverted level of the comparison frequency-divided signal Slv from the comparison frequency divider 106 to generate a signal up. A signal dw is generated by performing an AND operation on the level of Ref and the comparison frequency-divided signal Slv, and the signal comp rises in synchronization with the fall of the signal dw and is a master obtained by dividing the output signal of the reference oscillator 100. A signal comp having a pulse width of n (> 1) clocks is generated, and a signal init is generated by performing an AND operation on the inverted level of the signal comp and the inverted level of the reference signal Ref. The signal up and the signal dw
FIG. 2 shows an example of the timing for each phase comparison cycle of the signal, the signal comp, and the signal init. A charge pump 103 outputs a current corresponding to the phase difference obtained by the phase comparator 102. Reference numeral 104 denotes a loop filter for filtering a current from the charge pump 103. Reference numeral 105 denotes a voltage controlled oscillator (VCO) that changes the oscillation frequency according to the DC output voltage of the loop filter 104.

The detailed description of the comparison frequency divider 106, the loop filter 104, and the VCO 105 is described in, for example, Fr.
equency Synthesizer Design Handbook; James A. Craw
See ford, 1994.

Next, the operation of the charge pump 103 of FIG. 1 will be described with reference to FIG. For each phase comparison period, the signal up, the signal dw, the signal comp, and the signal init from the phase comparator 102 are applied to the charge pump 103 at the timing shown in FIG. 2, for example. In the charge pump 103, the signal up is applied to the FET SWP1 and the FET SWN3, and an inverted signal up # of the signal up (up # is u in FIG. 3).
(shown by p-bar) are FET SWP2 and FET SW
Applied to N4 and the signal dw is applied to FET SWP3 and FET
A signal dw # which is applied to SWN1 and is an inverted signal of the signal dw
(Dw # is indicated by a dw bar in FIG. 3).
SWP4 and FET SWN2 are applied to the
ET SWN7 and FET SWN8
t is applied to FET SWN5 and FET SWN6.

At each phase comparison period, first, the signal up rises, and while the signal up is H, the signal dw and the signal co
The levels of mp and signal init are both L. Therefore, the FET SW to which the H signal up is applied
P1 is turned off, the FET SWP2 to which the L signal up # is applied is turned on, the FET MP2 is activated, and the FET to which the L signal dw is applied.
SWN1 is turned off, the FET SWN2 to which the H signal dw # is applied is turned on, the FET MN3 is inactivated, and the FET SWN7 to which the L signal comp is applied is turned off, The FET SWN5 to which the L signal init is applied is turned off, and the current from the power supply is charged to the capacitor Csamplep via the FET MP2.

On the other hand, an FET to which an L signal dw is applied
SWP3 is turned on, the FET SWP4 to which the H signal dw # is applied is turned off, the FET MP3 is made inactive, and the F signal to which the H signal up is applied.
ET SWN3 is turned on, and the FET SWN4 to which the L signal up # is applied is turned off, and the FET MN4
Is activated, the FET SWN8 to which the L signal comp is applied is turned off, the FET SWN6 to which the L signal init is applied is turned off, and the capacitor Csam
The charge of plen is discharged to ground via FET MN4.

Then, at the same time when the signal up falls,
While the signal dw rises and the signal dw is H, the signal up
, The signal comp, and the signal init are each at L level. Therefore, the FET SWP1 to which the L signal up is applied is turned on, and the H signal up is applied.
FET SWP2 to which # is applied is turned off, and FETMP
2 is made inactive, the FET SWN1 to which the H signal dw is applied is turned on, and the FET SWN2 to which the L signal dw # is applied is turned off, and the FE
T MN3 is activated, and the L-level signal com
The FET SWN7 to which p is applied is turned off, and the L signal i
The FET SWN5 to which nit is applied is turned off, and the electric charge of the capacitor Csamplep is discharged to the ground via the FET MN3.

On the other hand, the FET to which the H signal dw is applied
While SWP3 is turned off, the FET SWP4 to which the L signal dw # is applied is turned on, the FET MP3 is activated, and the FET to which the L signal up is applied.
SWN3 is turned off, the FET SWN4 to which the H signal up # is applied is turned on, the FET MN4 is inactivated, and the FET SWN8 to which the L signal comp is applied is turned off, The FET SWN6 to which the L signal init is applied is turned off, and the current of the power supply becomes FE.
The capacitor Csamplen is charged via T MP3.

At the same time as the signal dw falls,
While the signal comp rises and the signal comp is H,
The levels of the signal up, the signal dw, and the signal init are L. Therefore, the FET to which the L signal up is applied
While SWP1 is turned on, the FET SWP2 to which the H signal up # is applied is turned off, the FET MP2 is made inactive, and the FET SWN1 to which the L signal dw is applied is turned off. And the H signal dw #
Is applied, the FET SWN2 is turned on, and the FET MN
3 is deactivated, and the signal comp of H
Is applied, the FET SWN7 is turned on, and the L signal in
The FET SWN5 to which it was applied is turned off, and the charge of the capacitor Csamplep is transferred to the capacitor via the FET SWN7.
Discharged to Choldp and held in capacitor Choldp.

On the other hand, an FET to which an L signal dw is applied
SWP3 is turned on, the FET SWP4 to which the H signal dw # is applied is turned off, the FET MP3 is made inactive, and the F signal to which the L signal up is applied.
ETSWN3 is turned off, the FET SWN4 to which the H signal up # is applied is turned on, the FET MN4 is made inactive, and the FET SWN8 to which the H signal comp is applied is turned on, and The FET SWN6 to which the signal init is applied is turned off, and the capacitor Csam
The electric charge of plen is discharged to the capacitor Choldn via the FET SWN3, and is held by the capacitor Choldn.

The charge on the capacitor Csamplep is
When the charge of the capacitor Csamplen is held by the capacitor Choldn while being held at the oldp, the voltage of the capacitor Choldp is applied to the FET MN5 of the differential amplifier circuit, and the voltage between the capacitors Choldn is changed by the FET MN6 of the differential amplifier. And the differential output is applied to FET MP6 and MP7 of the VI converter.

When the pulse width of the signal up is larger than the pulse width of the signal dw, that is, the frequency of the reference frequency-divided signal Ref
If fref is smaller than the frequency fslv of the comparison frequency-divided signal, F
Since the current flowing through ETMP7 is larger than the current flowing through FET MP6, that is, the current flowing through FET MN8, FEMP
The difference current between the current flowing through T MP6 and the current flowing through FET MP7 flows into loop filter 104.

When the pulse width of the signal up is smaller than the pulse width of the signal dw, that is, the frequency of the reference frequency-divided signal Ref
If fref is higher than the frequency fslv of the comparison frequency-divided signal, F
Since the current flowing through ETMP7 is smaller than the current flowing through FET MP6, that is, the current flowing through FET MN8, FEMP
The difference current between the current flowing through T MP6 and the current flowing through FET MP7 is drawn from loop filter 104.

When the pulse width of the signal up is equal to the pulse width of the signal dw, that is, the frequency fr of the reference frequency-divided signal Ref
If ef matches the frequency fslv of the comparison frequency-divided signal, FE
When the current Iup flowing through TMP7 is equal to the current Idw flowing through the FET MP6, that is, the current flowing through the FET MN8, that is, when the period during which the current Iup flows is Tup and the period during which the current Idw flows is Tdw,

[0025]

## EQU1 ## It can be expressed as I up × T up = I dw × T dw, and between the periods T up and T dw and the phase comparison period T,

[0026]

## EQU2 ## Since there is a relationship of Tup + Tdw = T / 2, current from the charge pump 103 does not flow into the loop filter 104 and is not drawn.

At the same time as the signal comp falls, the signal init rises, and while the level of the signal init is H, the signal up, the signal dw, and the signal com
The level of p is L. Accordingly, while the FET SWP1 to which the L signal up is applied is turned on, the H signal u
The FET SWP2 to which p # is applied is turned off, and the FET
MP2 is made inactive, the FET SWN1 to which the signal dw of L is applied is turned off, and the FET SWN2 to which the signal dw # of H is applied is turned on.
The FET MN3 is made inactive, and the FET SWN7 to which the signal comp of L is applied is turned on,
The FET SWN5 to which the signal init is applied is turned on, the electric charge of the capacitor Csamplep is discharged to ground via the FET SWN5, and the capacitor Csamplep is initialized.

On the other hand, the FET to which the L signal dw is applied
SWP3 is turned on, the FET SWP4 to which the H signal dw # is applied is turned off, the FET MP3 is made inactive, and the F signal to which the L signal up is applied.
ET SWN3 is turned off, and the FET SWN4 to which the signal up # of H is applied is turned on, and the FET MN4
Is inactive, and the FET SWN8 to which the L signal comp is applied is turned off, and the H signal ini is
FET SWN6 to which t is applied is turned on, and the capacitor
The charge of Csamplen is discharged to the ground via the FET SWN6, and the capacitor Csamplen is initialized.

Here, the charge Qt supplied from the charge pump 103 to the loop filter 104 is represented by the following formula: when the output current from the charge pump 103 is I and the phase comparison cycle is T.

[0030]

## EQU3 ## Qt = I × T.

On the other hand, in the conventional example shown in FIG. 4, the charge Qt supplied from the charge pump 603 to the loop filter 604 is such that the charge pump output average current is Iav,
If the period during which the signal UP is H is TUP (or the period during which the signal DW is H) is TDW,

[0032]

## EQU4 ## Qt = Iav × TUP or

[0033]

## EQU5 ## Qt = Iav × TDW.

The relationship between the phase comparison period T and the period TUP during which the signal UP is H (or the period TDW during which the signal DW is high) is TUP <T / 2 (or TDW <T /
2), the charge pump 103 of the present embodiment
Can be suppressed lower than the current from the charge pump 603 of the conventional example. In addition, since the charge pump 103 performs the sample-and-hold as described above, a decrease in loop gain due to a reduction in current does not occur. Therefore, it is possible to prevent a decrease in the frequency pull-in speed due to a decrease in the loop gain.

Further, in the present embodiment, since the above-described sample hold is performed by the charge pump 103, the occurrence of switching noise (feedthrough noise) and offset can be reduced.

Further, in the present embodiment, when the lock condition is satisfied, that is, when the current I flowing through the FET MP7 is
When up and the current Idw flowing through the FET MN8 become equal, the period during which the current Iup flows is Tup,
When a period in which the current Idw is flowing is Tdw and a phase comparison cycle is T,

[0037]

## EQU6 ## The relationship of Tup = Tdw = T / 4 holds, and the current source of the charge pump 103 operates by the phase comparison period / 4 at the time of phase sampling, and the current Iup and the current Idw in the locked state. Are equal, the current to the loop filter 104 only becomes zero, and the charge pump 103 is operating.
There is no dead zone in the phase comparator 102. Therefore, the phase noise (or spurious) characteristic of the PLL synthesizer is not adversely affected.

Generally, phase comparators and charge pumps are used as components of a transmit or receive PLL synthesizer, but this is within the scope of the present invention.
Although the frequency pull-in time is determined from the transfer function of the system, the phase noise (or the spurious characteristics of the system) largely depends on the circuit system of the components.

<Second Embodiment> This embodiment is a first embodiment.
The configuration of the VI converter is different from that of the embodiment. In the present embodiment, as shown in FIG.
The circuit in which the current source Ip and the FET MP8 are connected in series is connected to the FET
Connected in parallel with MP7, FET MP7 and FETMP8
A voltage between the capacitor Choldn is applied to each of the gates, and a circuit in which the FET MP9 and the current source Ip are connected in series is connected in parallel to the FET MN8,
Capacitor Chol is connected to each gate of MN8 and FET MN9.
Since the dP voltage is applied, the FET MP8
Works substantially the same as the ET MP7,
MP9 operates substantially similar to FET MN8.

The operation in the locked state will be described. Since the gate potential of the FET MN5 is higher than the gate potential of the FET MN6, the drain voltage of the FET MP4 drops, and the gm of the FET MP8 rises. Flows easily. As a result, the current supplied to the loop filter 104 increases, and the frequency pull-in speed increases. When the gate potentials of the FETs MN5 and MN6 are balanced, the FETs MP8 and F
ET MN9 is almost off, and the current sources Ip, In
Is not supplied to the loop filter 104.

That is, the potential of the loop filter 104 becomes
If it is far from the locking potential,
The current from Ip or the current source In is supplied to the charge pump 103
FET MN8, MP9 adjusts the current from the current sources Ip, In as the voltage approaches the locking potential.When locked, both FETs MP8, MN9 turn off and charge. The current of the pump 103 is the FET MP7
, MN8 only.

According to this embodiment, the frequency pull-in speed is faster than that of the first embodiment.

[0043]

As described above, according to the present invention,
With the configuration described above, the phase noise characteristic or the spurious characteristic can be improved.

Further, according to the present invention, since the above configuration is adopted, the frequency pull-in speed can be further increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 shows a signal u output from the phase comparator 102 of FIG.
6 is a timing chart showing an example of timings of a signal p, a signal dw, a signal comp, and a signal init.

FIG. 3 is a circuit diagram showing a configuration of a charge pump 103 in FIG.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional example of a PLL synthesizer.

FIG. 6 is a circuit diagram showing a configuration of a charge pump 603 in FIG.

FIG. 7 is a timing chart showing an example of the timing of each signal when Ref> Slv.

FIG. 8 is a timing chart showing an example of the timing of each signal when Ref <Slv.

FIG. 9 is a timing chart showing an example of the timing of each signal when Ref = Slv.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Reference oscillator 101 Reference divider 102 Phase comparator 103 Charge pump 104 Loop filter 105 Voltage controlled oscillator 106 Comparison divider

Claims (4)

[Claims] An output from a voltage controlled oscillator is frequency-divided by a comparison frequency divider, and a phase difference between a phase of an obtained comparison frequency-divided signal and a phase of a reference signal from a reference frequency divider is calculated. In a PLL synthesizer that outputs a signal corresponding to the obtained phase difference by a charge pump, filters the output by a loop filter, and changes the oscillation frequency of the voltage controlled oscillator based on a DC output from the loop filter, The phase comparator includes: a first sampling unit that samples a constant current for a time corresponding to a phase difference between the reference frequency-divided signal and the comparison frequency-divided signal for each phase comparison cycle; Immediately after sampling,
A second sampling means for sampling the constant current for a time corresponding to a difference between the reference frequency-divided signal and the phase difference; immediately after the sampling by the second sampling means, the first and second sampling means respectively First and second holding means for simultaneously holding the sampled first and second currents, respectively, wherein the charge pump comprises: a first current and a second current respectively held by the first and second holding means. To a differential input voltage, and a differential output current corresponding to the obtained differential input voltage is output to the loop filter.
LL synthesizer. 2. The device according to claim 1, wherein the first sampling means sets the level of the reference frequency-divided signal and the level of the inverted comparison frequency-divided signal of the comparison frequency-divided signal as A
The constant current is sampled for a time corresponding to the pulse width obtained by the ND operation, and the second sampling means obtains the level of the reference frequency-divided signal and the level of the comparison frequency-divided signal by AND operation. Wherein the constant current is sampled for a time corresponding to a given pulse width. 3. The charge pump according to claim 2, wherein when the first current is less than the second current, the charge pump draws a difference current between the first current and the second current from the loop filter, When the first current exceeds the second current,
A PLL synthesizer characterized by flowing a difference current between the first current and the second current into the loop filter, and not outputting a current when the first current is equal to the second current. 4. The charge pump according to claim 1, further comprising: a current source; and a circuit for flowing a differential output current from the current source in accordance with the differential input voltage. Is superimposed on a differential output current according to the differential input voltage according to claim 1.