JP4018803B2 - PLL synthesizer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a PLL synthesizer.
[0002]
[Prior art]
As a PLL (phase locked loop) synthesizer used in mobile communication devices such as cellular phones, the one shown in FIG. 5 is known. The PLL synthesizer as shown in FIG. 5 divides the output from the voltage controlled oscillator (VCO) 605 by the comparison frequency divider 606, the phase of the obtained comparison frequency division signal, and the reference frequency from the reference frequency divider 601. A phase difference from the phase of the signal is obtained by the phase comparator 602, a signal corresponding to the obtained phase difference is output by the charge pump 603, the output is filtered by the loop filter 604, and the DC output from the loop filter 604 is used. The VCO 605 is driven to lock the frequency and phase of the comparison divided signal to the reference signal.
[0003]
The phase comparator 602 shown in FIG. 5 is constituted by a logic gate, and operates in response to rising edges of the reference signal Ref and the comparison divided signal Slv. When the relationship between the frequency (fref) of the reference signal Ref and the frequency (fslv) of the comparison signal Slv is fref> fslv, the level of the output signal UP is H (high level), for example, as shown in FIG. The level of the output signal DW becomes L (low level). In the case of fref <fslv, for example, as shown in FIG. 7, the level of the output signal UP is L and the level of the output signal DW is H. Even when fref = fslv, since the dead zone of the phase comparator 602 is eliminated, for example, as shown in FIG. 8, the output signal UP and the output signal DW become a hazard (whisker).
[0004]
As shown in FIG. 9, the charge pump 603 shown in FIG. 5 has two FETs Mp1 and Mn1 connected in series between the power source and the ground, and when the level of the output signal UP of the phase comparator 602 becomes H. FET Mp1 is turned on and current is supplied from the power supply to the loop filter 604. On the other hand, when the output signal DW of the phase comparator 602 becomes H, FET Mn1 is turned on and current is drawn from the loop filter 604.
[0005]
[Problems to be solved by the invention]
However, when fref = fslv, a wide hazard (whisker) may appear due to the propagation delay between the logic gates constituting the phase comparator 602. In this case, it appears. Due to the hazard, the phase noise or spurious characteristics of the system were adversely affected.
[0006]
As a method for solving such a problem, the fractional frequency division method (Fractional N) is used to set the comparison frequency higher than the integer frequency division method, and the spurious position on the frequency axis is moved far from the oscillation frequency of the VCO. The method of doing so is known. However, since this method requires arithmetic processing, when this method is adopted, there arises a new problem that the circuit scale becomes larger than the integer frequency division method. Moreover, even if this method is adopted, the spurious is only far away from the oscillation frequency of the VCO, and is not lost. Depending on the conditions, there is a possibility of adversely affecting the phase noise characteristics of the system. It was not a solution.
[0007]
An object of the present invention is to provide a PLL synthesizer capable of solving the above-described problems and suppressing spurious.
[0008]
[Means for Solving the Problems]
The PLL synthesizer of the present invention divides the output from the voltage controlled oscillator by the comparison frequency divider, and calculates the phase difference between the phase of the obtained comparison frequency division signal and the phase of the reference signal from the reference frequency divider. A PLL synthesizer that outputs a signal corresponding to the obtained phase difference by a charge pump, filters the output by a loop filter, and changes the oscillation frequency of the voltage controlled oscillator based on a DC output from the loop filter. The charge pump supplies a current for a first time corresponding to a phase difference between the reference frequency-divided signal and the comparative frequency-divided signal for each phase comparison period, and a first time based on the supplied current. a first charge means for charging a first charge in the first capacitors, immediately after the charge due to the first charge means, corresponding to a half period of the phase comparison period The second supply current during a time corresponding to a difference between the first time and during a second charge means for charging the second charge to the second capacitor based on the supplied current, the second immediately after the charge by the charge means, and first and second hold means for simultaneously holding each said first and second electric charge charged respectively by the first and second charge means, said first and second A difference current corresponding to the difference between the first and second charges held by the holding means is output to the loop filter.
Further, the PLL synthesizer according to the present invention receives the voltages corresponding to the first and second charges held by the first and second hold means, respectively, and outputs the first and second output voltages, respectively. Amplifying means; and voltage-current converting means for converting the first and second output voltages into first and second currents and outputting the difference current between the first current and the second current to the loop filter. Further, it can be provided.
[0009]
The first charging means supplies and supplies a current for a time corresponding to a pulse width obtained by ANDing the level of the reference frequency-divided signal and the inverted comparative frequency-divided signal level of the comparative frequency-divided signal. The first charge based on the current is charged in the first capacitor, and the second charging means corresponds to a pulse width obtained by ANDing the level of the reference frequency division signal and the level of the comparison frequency division signal. A current can be supplied for a time, and a second charge based on the supplied current can be charged to the second capacitor.
[0010]
The voltage-current conversion means draws the difference current from the loop filter when the first current is less than the second current, and converts the difference current to the loop when the first current exceeds the second current. When flowing into a filter and the first current is equal to the second current, no current can be output. Further, the voltage-current conversion means includes first and second current sources, a first superimposing circuit that superimposes a third current from the first current source on the first current according to the first output voltage, A second superimposing circuit for superimposing the fourth current from the second current source on the second current according to a second output voltage, and a current obtained by superimposing the third current on the first current, A difference current from a current obtained by superimposing the fourth current on two currents can be output to the loop filter.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0012]
<First Embodiment>
FIG. 1 shows a first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a reference frequency divider that divides a signal from the reference oscillator 100. Reference numeral 106 denotes a comparison frequency divider that divides an output from a voltage controlled oscillator (VCO) 105. A phase comparator 102 AND-operates the level of the reference signal Ref from the reference frequency divider 101 and the inverted level of the comparative frequency division signal Slv from the comparison frequency divider 106 to generate a signal up, A master signal obtained by ANDing the level of Ref and the comparative frequency-divided signal Slv to generate a signal dw and dividing the output signal of the reference oscillator 100 that rises in synchronization with the fall of the signal dw. A signal comp having a pulse width corresponding to n (> 1) clocks is generated, and a signal init is generated by ANDing the inversion level of the signal comp and the inversion level of the reference signal Ref. FIG. 2 shows an example of the timing for each phase comparison period of the signal up, the signal dw, the signal comp, and the signal init. Reference numeral 103 denotes a charge pump that outputs a current corresponding to the phase difference obtained by the phase comparator 102. A loop filter 104 filters the current from the charge pump 103. A voltage controlled oscillator (VCO) 105 changes the oscillation frequency in accordance with the DC output voltage of the loop filter 104.
[0013]
For details of the comparison frequency divider 106, the loop filter 104, and the VCO 105, see, for example, Frequency Synthesizer Design Handbook; James A. Crawford, 1994.
[0014]
Next, the operation of the charge pump 103 in FIG. 1 will be described with reference to FIG. For each phase comparison period, the signal up, the signal dw, the signal comp, and the signal init from the phase comparator 102 are applied to the charge pump 103 at the timing shown in FIG. 2, for example. In the charge pump 103, the signal up is applied to the FET SWP1 and the FET SWN3, the inverted signal up # of the signal up (up # is indicated by an up bar in FIG. 3) is applied to the FET SWP2 and the FET SWN4, and the signal dw Is applied to FET SWP3 and FET SWN1, a signal dw # (dw # is indicated by dw bar in FIG. 3) which is an inverted signal of the signal dw is applied to FET SWP4 and FET SWN2, and a signal comp is applied to FET SWN7 and FET SWN7. The signal init is applied to the FET SWN8 and the signal init is applied to the FET SWN5 and the FET SWN6.
[0015]
For each phase comparison period, first, the level of the signal dw, the signal comp, and the signal init is L while the signal up rises and the signal up is H. Accordingly, the FET SWP1 to which the H signal up is applied is turned off, the FET SWP2 to which the L signal up # is applied is turned on, the FET MP2 is activated, and the L signal dw is The applied FET SWN1 is turned off, the FET SWN2 to which the H signal dw # is applied is turned on, the FET MN3 is inactivated, and the FET SWN7 to which the L signal comp is applied is The FET SWN5 to which the L signal init is applied is turned off, and the current from the power source is charged to the capacitor Csamplep via the FET MP2.
[0016]
On the other hand, the FET SWP3 to which the L signal dw is applied is turned on, the FET SWP4 to which the H signal dw # is applied is turned off, the FET MP3 is inactivated, and the H signal up FET SWN3 to which is applied is turned on, FET SWN4 to which L signal up # is applied is turned off, FET MN4 is activated, and FET SWN8 to which L signal comp is applied is The FET SWN6 to which the L signal init is applied is turned off, and the charge of the capacitor Csamplen is discharged to the ground via the FET MN4.
[0017]
Then, at the same time as the signal up falls, while the signal dw rises and the signal dw is H, the levels of the signal up, the signal comp, and the signal init are respectively L. Accordingly, the FET SWP1 to which the L signal up is applied is turned on, the FET SWP2 to which the H signal up # is applied is turned off, the FET MP2 is inactivated, and the H signal dw FET SWN1 to which L is applied is turned on, FET SWN2 to which L signal dw # is applied is turned off, FET MN3 is activated, and FET SWN7 to which L signal comp is applied is The FET SWN5 to which the L signal init is applied is turned off, and the charge of the capacitor Csamplep is discharged to the ground through the FET MN3.
[0018]
On the other hand, the FET SWP3 to which the H signal dw is applied is turned off, the FET SWP4 to which the L signal dw # is applied is turned on, the FET MP3 is activated, and the L signal up is The applied FET SWN3 is turned off, the FET SWN4 to which the H signal up # is applied is turned on, the FET MN4 is made inactive, and the FET SWN8 to which the L signal comp is applied is turned off. The FET SWN6 to which the L signal init is applied is turned off, and the current of the power supply is charged to the capacitor Csamplen via the FET MP3.
[0019]
At the same time as the signal dw falls, the signal comp rises, and while the signal comp is H, the levels of the signal up, the signal dw, and the signal init are L. Accordingly, the FET SWP1 to which the L signal up is applied is turned on, the FET SWP2 to which the H signal up # is applied is turned off, the FET MP2 is inactivated, and the L signal dw FET SWN1 to which is applied is turned off, FET SWN2 to which H signal dw # is applied is turned on, FET MN3 is made inactive, and FET SWN7 to which H signal comp is further applied Is turned on, the FET SWN5 to which the L signal init is applied is turned off, and the charge of the capacitor Csamplep is discharged to the capacitor Choldp through the FET SWN7 and held in the capacitor Choldp.
[0020]
On the other hand, the FET SWP3 to which the L signal dw is applied is turned on, the FET SWP4 to which the H signal dw # is applied is turned off, the FET MP3 is inactivated, and the L signal up FETSWN3 to which H is applied is turned off, FET SWN4 to which H signal up # is applied is turned on, FET MN4 is made inactive, and FET SWN8 to which H signal comp is applied is turned on The FET SWN6 to which the L signal init is applied is turned off, and the charge of the capacitor Csamplen is discharged to the capacitor Choldn via the FET SWN3 and held in the capacitor Choldn.
[0021]
When the charge of the capacitor Csamplep is held in the capacitor Choldp and the charge of the capacitor Csamplen is held in the capacitor Choldn, the voltage of the capacitor Choldp is applied to the FET MN5 of the differential amplifier circuit, and the voltage between the capacitors Choldn is The differential output is applied to FET MN6 of the differential amplifier, and the differential output is applied to FET MP6 and FET MP7 of the VI converter.
[0022]
When the pulse width of the signal up is larger than the pulse width of the signal dw, that is, when the frequency fref of the reference divided signal Ref is smaller than the frequency fslv of the comparative divided signal, the current flowing through the FET MP7 is the current flowing through the FET MP6. That is, since it is larger than the current flowing through the FET MN8, the difference current between the current flowing through the FET MP6 and the current flowing through the FET MP7 flows into the loop filter 104.
[0023]
When the pulse width of the signal up is smaller than the pulse width of the signal dw, that is, when the frequency fref of the reference divided signal Ref is larger than the frequency fslv of the comparative divided signal, the current flowing through the FET MP7 is the current flowing through the FET MP6. That is, since it is smaller than the current flowing through the FET MN8, the difference current between the current flowing through the FET MP6 and the current flowing through the FET MP7 is drawn from the loop filter 104.
[0024]
When the pulse width of the signal up is equal to the pulse width of the signal dw, that is, when the frequency fref of the reference divided signal Ref coincides with the frequency fslv of the comparative divided signal, the current Iup flowing through the FET MP7 changes the FET MP6. When the current Idw is equal to the current flowing through the FET MN8, that is, the period in which the current Iup flows is Tup and the period in which the current Idw is flowing is Tdw,
[0025]
[Expression 1]
I up × Tup = I dw × Tdw
In addition, between the periods Tup, Tdw and the phase comparison period T,
[0026]
[Expression 2]
Tup + Tdw = T / 2
Therefore, the current from the charge pump 103 does not flow into the loop filter 104 and is not drawn.
[0027]
At the same time as the signal comp falls, the signal up, the signal dw, and the level of the signal comp are L while the signal init rises and the level of the signal init is H. Accordingly, the FET SWP1 to which the L signal up is applied is turned on, the FET SWP2 to which the H signal up # is applied is turned off, the FET MP2 is inactivated, and the L signal dw FET SWN1 to which is applied is turned off, FET SWN2 to which H signal dw # is applied is turned on, FET MN3 is inactivated, and FET SWN7 to which L signal comp is applied Is turned on, the FET SWN5 to which the H signal init is applied is turned on, the charge of the capacitor Csamplep is discharged to the ground through the FET SWN5, and the capacitor Csamplep is initialized.
[0028]
On the other hand, the FET SWP3 to which the L signal dw is applied is turned on, the FET SWP4 to which the H signal dw # is applied is turned off, the FET MP3 is inactivated, and the L signal up FET SWN3 to which is applied is turned off, FET SWN4 to which H signal up # is applied is turned on, FET MN4 is inactivated, and FET SWN8 to which L signal comp is applied Is turned off, the FET SWN6 to which the H signal init is applied is turned on, the charge of the capacitor Csamplen is discharged to the ground through the FET SWN6, and the capacitor Csamplen is initialized.
[0029]
Here, the charge Qt supplied from the charge pump 103 to the loop filter 104 has an output current from the charge pump 103 as I and a phase comparison period as T.
[0030]
[Equation 3]
Qt = I x T
It can be expressed as.
[0031]
On the other hand, in the conventional example shown in FIG. 9 , the charge Qt supplied from the charge pump 603 to the loop filter 604 has a charge pump output average current Iav, and the period when the signal UP is H is TUP (or H of the signal DW is H If the period is TDW)
[0032]
[Expression 4]
Qt = Iav x TUP
Or
[0033]
[Equation 5]
Qt = Iav × TDW
It can be expressed as.
[0034]
Further, the relationship between the phase comparison period T and the period TUP in which the signal UP is H (or the period TDW in which the signal DW is H) is TUP <T / 2 (or TDW <T / 2). The current from the charge pump 103 of this embodiment can be suppressed to be lower than the current from the charge pump 603 of the conventional example. In addition, since the charge pump 103 performs the sample and hold as described above, the loop gain does not decrease due to the reduced current. Accordingly, it is possible to prevent a decrease in the frequency pulling speed due to a decrease in loop gain.
[0035]
In the present embodiment, since the above-described sample hold is performed by the charge pump 103, the occurrence of switching noise (feed through noise) and offset can be reduced.
[0036]
Furthermore, in the present embodiment, when the lock condition is satisfied, that is, when the current I up flowing through the FET MP7 becomes equal to the current I dw flowing through the FET MN8, the period during which the current Iup flows is expressed as Tup. And the period during which the current Idw flows is Tdw and the phase comparison period is T,
[0037]
[Formula 6]
Tup = Tdw = T / 4
Thus, the current source of the charge pump 103 operates at a phase comparison period of / 4 at the time of phase sampling. In the locked state, the current I up and the current I dw become equal, and the current to the loop filter 104 Since the charge pump 103 is operating only at zero, the phase comparator 102 has no dead zone. Therefore, the phase noise (or spurious) characteristic of the PLL synthesizer is not adversely affected.
[0038]
In general, phase comparators and charge pumps are used as components of a transmit or receive PLL synthesizer, which is within the scope of the present invention. The frequency acquisition time is determined from the transfer function of the system, but the phase noise (or the spurious characteristic of the system) largely depends on the circuit scheme of the component.
[0039]
<Second Embodiment>
This embodiment is different from the first embodiment in the configuration of the VI converter. In the present embodiment, as shown in FIG. 4, a circuit in which a current source Ip and FET MP8 are connected in series is connected in parallel to FET MP7, and a voltage across a capacitor Choldn is applied to each gate of FET MP7 and FETMP8. In addition, the circuit in which the FET MN9 and the current source In are connected in series is connected in parallel to the FET MN8, and the voltage between the capacitors CholdP is applied to the gates of the FET MN8 and the FET MN9. Operates substantially similar to FET MP7, and FET MN9 operates substantially similar to FET MN8.
[0040]
To explain the operation when in the locked state, the gate potential of the FET MN5 is higher than the gate potential of the FET MN6, down the drain voltage of the FET MP4, up gm of the FET MP8 is, from the current source Ip current is likely to flow to the FET MP8 of. As a result, the current supplied to the loop filter 104 increases, and the frequency pulling speed increases. When the gate potentials of FET MN5 and FET MN6 are balanced, FET MP8 and FET MN9 are almost turned off , and the current from the current sources Ip and In does not flow to FET MP8 and FET MN9. The currents from the current sources Ip and In are not supplied to the loop filter 104.
[0041]
In other words, when the potential of the loop filter 104 is greatly deviated from the potential to be locked, the current from the current source Ip or the current source In is added to the current of the charge pump 103 and output, and approaches the potential to be locked. As a result, the FET MP8 and MN9 adjust the current from the current sources Ip and In. When locked, the FET MP8 and MN9 are both turned off, and the current of the charge pump 103 is only the difference current between the FET MP7 and MN8. .
[0042]
Since the present embodiment is configured as described above, the frequency pull-in speed is increased as compared with the first embodiment.
[0043]
【The invention's effect】
As described above, according to the present invention, since it is configured as described above, it is possible to improve phase noise characteristics or spurious characteristics.
[0044]
Moreover, according to the present invention, since it is configured as described above, the frequency pull-in speed can be further increased.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of the present invention.
2 is a timing chart showing an example of timings of a signal up, a signal dw, a signal comp, and a signal init output from the phase comparator 102 of FIG.
3 is a circuit diagram showing a configuration of the charge pump 103 of FIG. 1. FIG.
FIG. 4 is a circuit diagram showing a second embodiment of the present invention.
FIG. 5 is a block diagram showing a conventional example of a PLL synthesizer.
6 is a circuit diagram showing a configuration of a charge pump 603 in FIG. 5. FIG.
FIG. 7 is a timing chart showing an example of the timing of each signal when Ref> Slv.
FIG. 8 is a timing chart showing an example of the timing of each signal when Ref <Slv.
FIG. 9 is a timing chart showing an example of the timing of each signal when Ref = Slv.
[Explanation of symbols]
100 Reference Oscillator 101 Reference Divider 102 Phase Comparator 103 Charge Pump 104 Loop Filter 105 Voltage Controlled Oscillator 106 Comparative Divider

Claims (5)

The output from the voltage controlled oscillator is divided by the comparison divider, and the phase difference between the phase of the obtained comparison divided signal and the phase of the reference signal from the reference divider is obtained by the phase comparator. In a PLL synthesizer that outputs a signal according to the phase difference by a charge pump, filters the output by a loop filter, and changes the oscillation frequency of the voltage controlled oscillator based on a DC output from the loop filter.
The charge pump is
In each phase comparison period, a current is supplied for a first time corresponding to the phase difference between the reference divided signal and the comparative divided signal, and a first charge based on the supplied current is supplied to the first capacitor. A first charging means for charging ;
Immediately after the charge due to the first charge means, supplying a second current during the time corresponding to the difference between the time corresponding to a half period and the first time of the phase comparison period, the supplied current Second charging means for charging the second capacitor with the second charge based thereon ;
Immediately after the charge due to the second charge means, and first and second hold means for simultaneously holding each said first and second electric charge charged respectively by the first and second charge means,
PLL synthesizer and outputting a difference current corresponding to a difference between the held first and second charge respectively by said first and second holding means to said loop filter. In claim 1,
Differential amplifying means for inputting voltages corresponding to the first and second charges held by the first and second holding means, respectively, and outputting first and second output voltages, respectively;
Voltage-current conversion means for converting the first and second output voltages into first and second currents and outputting the difference current between the first current and the second current to the loop filter;
A PLL synthesizer further comprising: In claim 1 or 2,
The first charging means supplies and supplies a current for a time corresponding to a pulse width obtained by ANDing the level of the reference divided signal and the inverted comparison divided signal level of the comparative divided signal. Charging the first capacitor with a first charge based on the measured current;
The second charging means supplies a current for a time corresponding to a pulse width obtained by ANDing the level of the reference divided signal and the level of the comparative divided signal, and is based on the supplied current A PLL synthesizer characterized by charging a second charge to the second capacitor . In claim 2 ,
The voltage-current conversion means draws the difference current from the loop filter when the first current is less than the second current, and converts the difference current to the voltage when the first current exceeds the second current. A PLL synthesizer that flows into a loop filter and does not output a current when the first current is equal to the second current . In claim 2,
  The voltage-current conversion means includes
  First and second current sources; a first superimposing circuit for superimposing a third current from the first current source on the first current in accordance with the first output voltage; and the first superposing circuit in response to the second output voltage. A second superimposing circuit for superimposing a fourth current from a second current source on the second current,
  A PLL synthesizer, wherein a current of a difference between a current obtained by superimposing the third current on the first current and a current superposed by the fourth current on the second current is output to the loop filter.

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