JPH11297084A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen or eliminate the temp. dependence of a threshold voltage in a write or erase state of memory cells. SOLUTION: The semiconductor device comprises an electrically erasable and writable nonvolatile memory 30, temp. detecting means 8 for detecting the temp. of the semiconductor device, and control means (CPU) 10 capable of changing a verify voltage generated in a verify voltage generator circuit 22. The control means 10 changes the verify voltage in the direction to cancel the variation of the threshold voltage of a memory cell when tending to change depending on the semiconductor device temp., e.g. more raises the write verify voltage for the detected temp. higher, thereby canceling the temp. dependence of the verify voltage itself by that of other circuits concerning the verifying operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for controlling an erase verify voltage or a write verify voltage in a semiconductor device having electrically erasable and writable nonvolatile memory cells, for example, a flash memory and a flash memory. The present invention relates to a technology that is effective when applied to a microcomputer or the like having an on-chip.

[0002]

2. Description of the Related Art As a semiconductor device having an electrically erasable and writable nonvolatile memory cell, a nonvolatile semiconductor memory device capable of storing information by injecting electrons into or extracting electrons from a floating gate, for example, EEP
ROM or flash memory has been conventionally provided. A flash memory has a memory cell transistor having a floating gate (floating gate), a control gate, a source and a drain. In this memory cell transistor, the threshold voltage increases when electrons are injected into the floating gate, and the threshold voltage decreases when electrons are extracted from the floating gate. The memory cell transistor stores information according to the level of the threshold voltage with respect to the word line voltage (control gate applied voltage) for data reading. E
The EPROM is basically the same as the flash memory. A state where the threshold voltage of the memory cell transistor is low may be defined as a write state, and a state where the threshold voltage is high may be defined as an erase state. The opposite is sometimes defined.

As an example of a document describing a flash memory, Nikkei Microdevices (November 1994) No. 48
Page and page 49, and JP-A-9-297996.

For example, a write operation in a flash memory is performed by applying a high voltage between a control gate and a drain of a memory cell to be selected for writing. Generally, application of a write voltage is performed gradually in short time intervals to prevent an overwrite state. Whenever a write voltage is applied, a write verify operation is performed. For example, when a state in which the threshold voltage is lower than the erase state is defined as a write state, a word line selection voltage that is turned off when the memory cell has the threshold voltage in the write state is given as a write verify voltage after a write voltage is applied, and If the memory cell to be written is turned on, it is determined that writing is completed, and if it is off, it is determined that writing is incomplete.

[0005]

The present inventors have studied the temperature dependence of the threshold voltage in the written state or the erased state. The inventor has found that the threshold voltage of a memory cell varies depending on the temperature during a write operation or an erase operation. For example, a state in which the threshold voltage is lower than the erased state is defined as a written state unless otherwise specified. At this time, when the write operation is performed at a low temperature, the threshold voltage of the memory cell becomes the normal temperature (for example, 2
0 ° C), and the depletion margin is significantly deteriorated. Conversely, the threshold voltage tends to increase during writing at a high temperature. This situation is shown in detail in FIG. 11, and the threshold voltage distribution at the time of writing is lower at a low temperature and higher at a high temperature, compared to the threshold voltage distribution in an erased state.

As shown in FIG. 12, the temperature dependency of the threshold voltage due to the above-described writing of a memory cell is determined by a reference voltage generating circuit used when generating a verify voltage,
The present invention is based on the temperature characteristics of a memory cell, a sense amplifier, etc., and may be caused by a situation where the temperature dependence of the verify voltage itself and the temperature dependence of other circuits related to the verify operation are not offset. Was found by others.

An object of the present invention is to provide a semiconductor device capable of reducing or eliminating the temperature dependency of a threshold voltage in a write or erase state of a memory cell.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the nonvolatile memory cell includes an electrically erasable and writable nonvolatile memory cell and a verify voltage generating circuit (22) for generating an erase or write verify voltage. Voltage or write verify voltage (Vwvfy)
Is applied to a selected word line to perform an erase or write verify operation in a semiconductor device (33, 51), a temperature detecting means (8) for detecting the temperature of the semiconductor device, and a verify voltage generated by the verify voltage generating circuit. And control means (10, 11, 50) for making the temperature variable based on the temperature detected by the temperature detecting means. The control means changes the verify voltage in a direction to offset a change in the threshold voltage of the memory cell which tends to change depending on the temperature of the semiconductor device. For example, the control means increases the write verify voltage as the detected temperature is lower.

As described above, the temperature dependence of the verify voltage itself and the temperature dependence of other circuits related to the verify operation cancel each other, whereby the temperature dependence of the threshold voltage in the write or erase state of the memory cell is canceled. Can be reduced or eliminated.

As a specific mode of the verify voltage control, a storage area of a data table (TBL) in which control data for determining a verify voltage in a predetermined temperature range is arranged in advance at predetermined temperature intervals is provided. Refers to control data for obtaining a verify voltage at the detected temperature from the data table based on a temperature difference between the reference temperature and the detected temperature, and controls the verify voltage using the referred control data. Can be. The temperature difference (Tdi) between the reference temperature (Tm) and the detected temperature (Tn)
By using f), it is possible to operate the temperature information by the relative value.

[0013] Further, a storage area (18) for process variation compensation data for compensating a variation related to a verify voltage at a reference temperature caused by a process variation inherent to the semiconductor device is provided. The process variation compensation data is added to the data, and the verify voltage can be controlled by the added data. The process variation compensation data is for compensating for individual differences of individual semiconductor devices with respect to the contents of the data table, and the control data of the data table is logically or ideally defined at the reference temperature. The trimming data value is a trimming data value that can form a difference voltage from the actually measured verify voltage value with the same control data at the reference temperature, and can be created by reflecting the device test results of the semiconductor device. It can be said that the correction method using the data table based on the reference temperature is also excellent in compensating for process variation.

The control means includes a central processing unit (10).
And the storage means (11) for storing the operation program can be configured in software, or can be configured in hardware by a dedicated arithmetic circuit (50).

The semiconductor device can store not only binary data in a nonvolatile memory cell but also multi-valued data of four or more values in one memory cell.

[0016]

FIG. 2 is a block diagram of a microcomputer as an example of a semiconductor device according to the present invention. Microcomputer (MCU) shown in the figure
33 is formed on one semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique, for example. The microcomputer 33 is a microcomputer with a built-in flash memory, and has a CPU (Central
Processing Unit (Central Processing Unit) 10, RAM serving as a work area or a temporary data storage area for CPU 10
(Random Access Memory) 11, a flash memory (FROM) 30 in which an operation program and control data of the CPU 10 are stored, a temperature sensor 8 such as a thermistor for measuring the temperature of the microcomputer 33, An analog / digital conversion circuit (A / D) 9 for converting analog temperature information into a digital signal output from the temperature sensor 8, an input / output port (I / O) 32 for external interface, and other peripheral circuits (PRF) ) 31 which are connected to the internal bus 14 which is typically shown.

FIG. 1 shows an example of a detailed value of a portion focusing on generation of a write verify voltage of the flash memory 30. In FIG. 1, registers 15, 16, 17, 1
8 and 20 are not particularly limited, but should be understood to be data registers in the CPU 10 or storage areas allocated to the RAM 11.

In FIG. 1, reference numeral 3 denotes a flash memory mat in which flash memory cells are arranged in a matrix. Although not particularly shown, the flash memory cell has a floating gate (floating gate), a control gate, a source, and a drain. The control gate is connected to a word line, the drain is connected to a bit line, and the source is connected to a source line. The circuit block indicated by 2 includes a word driver, a write circuit, a source driver, a sense amplifier, a column selection switch (Y-SW), a decoder, and a controller. The word driver selectively drives a word line according to a word line power supply. The source driver drives a source line by a source line power supply. The sense amplifier functions as a sense latch that detects and latches data read to the bit line. Y-SW is a switch circuit for selectively conducting a bit line to a common data line. The decoder decodes the address signal to Y
Form a selection signal of SW and a drive selection signal of a word driver. The controller generates control procedures necessary for operations such as erasing, erasing verify, writing, write verifying, and reading according to a command received from the outside.

The power supply switching circuit 1 includes a word line power supply (word line drive power supply for reading, writing, and erasing),
Data line power supply (bit drive line power supply for writing / erasing),
Source line power supply, sense amplifier power supply, write circuit power supply,
And an operation voltage such as a Y-SW power supply (Y-SW selection drive power supply) is switched to an operation mode or an operation state and supplied to the circuit block 2. The power supply switching circuit 1 is supplied with an external power supply voltage VCC, several types of boosted voltages obtained by boosting the external power supply voltage VCC by a booster circuit (not shown), a write verify voltage Vwvfy, and the like. The power supply switching circuit 1 is a circuit block according to an operation mode.
The switching of the input power to the output power is controlled in accordance with a control signal output from the second controller.

The threshold voltage of the memory cell transistor increases when electrons are injected into the floating gate, and decreases when electrons are extracted from the floating gate. The memory cell transistor stores information according to the level of the threshold voltage with respect to the word line voltage (control gate applied voltage) for data reading. A state where the threshold voltage of the memory cell transistor is low is defined as a write state, and a state where the threshold voltage is high is defined as an erase state.

When a write operation is designated in the flash memory 30, a high voltage is applied between the control gate and the drain of the memory cell to be selected for writing. In order to prevent the overwriting state, the application of the writing voltage is gradually performed in short time intervals. Whenever a write voltage is applied, a write verify operation is performed. For example, when a state in which the threshold voltage is lower than the erase state is defined as a write state, a word line selection voltage that is turned off when the memory cell has the threshold voltage in the write state is given as a write verify voltage after a write voltage is applied, and If the memory cell to be written is turned on, it is determined that writing is completed, and if it is off, it is determined that writing is incomplete.

The write verify voltage Vwvfy is generated by a write verify voltage generating circuit 22. The write verify voltage generation circuit 22 is configured by a clamp power supply mainly composed of a positive-phase amplification operational amplifier that receives a reference voltage Vref output from the reference voltage generation circuit 6 at a non-inverting input terminal (+). The output terminal of the operational amplifier 4 is feedback-connected to the inverting input terminal (−) via the feedback resistor circuit 21 and the trimming switch circuit 5. The trimming switch circuit 5 selects the feedback voltage divided by the feedback resistor circuit 21. The write verify voltage Vwvfy is determined according to the selected feedback voltage. The selection of the feedback voltage by the trimming switch circuit 5 is determined by the data set in the register 19. In other words, the write verify voltage V
The value of wvfy can be made variable.

The CPU 10 detects a verify voltage Vwvfy generated by the verify voltage generating circuit 22 in order to reduce or eliminate the temperature dependency of the threshold voltage in the write state of the flash memory cell. Is variably controlled based on. That is, the CPU 10 operates according to the operation program.
The verify voltage is changed in such a direction as to offset the threshold value variation of the memory cell which is likely to change depending on the temperature of the microcomputer. For example, the CPU 10 controls the data in the register 19 so that the lower the detected temperature is, the higher the write verify voltage is.

A detailed example of the method of controlling the verify voltage will be described. First, a data table TBL in which control data (trimming data) for determining a verify voltage in a predetermined temperature range is arranged in advance at predetermined temperature intervals is loaded into the RAM 11. The initial data of the data table TBL can be held in the flash memory 30 or the like.
11 can be initially loaded. An example of the data table TBL is shown in FIG.
° C), trimming data D0 to Dn are arranged. The data table TBL is typically generated based on actual measurement or theoretical calculation. That is, the write verify voltage necessary to offset the temperature dependence of the threshold voltage of the memory cell in the written state is determined by actual measurement or theoretical calculation, and individual trimming data is determined based on this. Therefore, the theoretical value of the write verify voltage formed by the trimming data is grasped in advance.

Further, the process variation compensation data for compensating for the variation in the verify voltage at the reference temperature caused by the process variation inherent to the microcomputer is loaded into the register 18. The process variation compensation data is for compensating for individual differences between individual microcomputers with respect to the contents of the data table TBL. At the reference temperature, the control data of the data table logically or ideally defines a verify voltage and a verify voltage. , A trimming data value for forming a difference voltage from an actually measured verify voltage value generated by the control data at the reference temperature. The process variation compensation data is obtained as part of a device test of the microcomputer 33 and stored in the flash memory 33. The process variation compensation data is initially loaded into the register 18 by a power-on reset.

The CPU 10 controls the write verify voltage using the data table TBL and the process variation compensation data as follows. The information of the reference temperature is initially loaded from the flash memory 30 to the register 15 at the time of power-on reset. For example, the reference temperature information is information on the temperature Tm related to the trimming data D5 in FIG. The CPU 10 stores the current temperature information measured by the temperature sensor 8 (for example, information on the temperature Tn in FIG. 3) in the register 20. The CPU 10 calculates the difference (Tm-Tn) between the reference temperature information and the current temperature information, and stores the difference in the register 16 as temperature difference information (Tdif in FIG. 3). C
The PU 10 generates final temperature information Tlst based on a value obtained by adding the temperature difference information Tdif to the reference temperature information Tm. As can also be seen in FIG. 3, the temperature difference information T
The sum (Tdif + Tm) of the dif and the reference temperature information Tm is not always an integral multiple of the step temperature i of each trimming data. There is an error, and a temperature at which the difference from the reference temperature becomes an integral multiple of the step temperature i of the trimming data. Is made to be the final temperature information Tlst. This operation can be expressed as a temperature correction function Fa (T) which can be expressed by Tlst = Fa (Tdif + Tm). The CPU 10 searches the data table according to the final temperature information Tlst, and stores, for example, the searched trimming data D7 in the register 17. This search processing is performed by F
b (Tlst).

At the time of power-on reset, process variation compensation data is initially loaded into the register 18 of FIG. For example, when the write bias voltage is formed using the trimming data D5 corresponding to the reference temperature (Tm) while the temperature of the microcomputer 33 is maintained at the reference temperature (Tm), the voltage becomes Vj with respect to the expected value voltage V5. , The process variation compensation data is set to Dcmp = − (Vj−V5).

The CPU 10 adds the process variation compensation data Dcmp to the trimming data D5 corresponding to the final temperature information Tlst, sets the added data in the register 19, and determines the write verify voltage.

FIG. 4 shows the method of calculating the trimming data. Td is stored in the register 16 (R2).
if = (Tm-Tn) is stored. Register 17 (R
3) includes trimming data Fb corresponding to the final temperature information.
(Tlst) = Fb ｛Fa (R0, R1)｝ = Fb ｛F
a (Tdif + Tm)} is stored.

FIG. 5 shows the relationship between the correction control of the write verify voltage and the threshold voltage of the memory cell thereby, using temperature as a parameter. If the write verify voltage is not corrected, the threshold voltage of the memory cell becomes too low during low-temperature writing. Conversely, it becomes too high at high temperatures.
By correcting the write verify voltage according to the temperature (in this example, the write verify voltage is increased as the temperature becomes lower, the distribution of the threshold voltage of the memory cell becomes substantially constant.

Therefore, it is possible to solve the conventional problems that the depletion margin is remarkably deteriorated even when writing at a low temperature. Further, the operation guarantee temperature range at the time of writing can be expanded, and the usability is improved. Variations in the threshold voltage of the memory cell in the written state are reduced, and the reliability of the memory is improved. In addition, since the performance of the sense amplifier and the verify power supply circuit itself is improved to reduce the threshold voltage variation of the memory cell,
It is not necessary to pay attention to the sense amplifier, the verify power supply circuit, and the like for suppressing the variation in the threshold voltage of the memory cell, which contributes to shortening of the design. Further, by using the temperature difference between the reference temperature and the detected temperature, it is possible to operate the temperature information based on the relative value, and the calculation process for correction is simplified.

FIG. 6 shows a flowchart of a write operation to the flash memory 30. CPU10
Indicates a write operation to the flash memory 30 (S
1), the write data is transferred to the RAM 11 (S2), and R
The data is transferred from the AM 11 to the data latch of the flash memory 30 (S3). After the transfer, the trimming data is corrected (S4), and the calculated trimming data is set in the register 19 (S5). Thereafter, a write voltage is applied to the write target memory cell for a certain period of time (S6), and a write verify operation is performed (S7). It is determined whether or not all bits are written by the write verify operation (S8). Until all bits are written, the rewrite data is calculated (S9) and the above steps S3 to S3 are performed.
8 is repeated. As described above, the trimming data correction process is performed every time the write voltage is applied.
Variation in the write threshold voltage can be suppressed with high reliability.

The structure for correcting the write verify voltage can be applied to a circuit for forming an erase verify voltage. For example, the correction may be performed so that the lower the temperature, the higher the erase verify voltage. The erasing operation at that time is performed by the CPU as illustrated in the flowchart of FIG.
After the erase command is issued from S10 (S11), a trimming data correction operation for erase verify voltage control is performed (S12), and the corrected trimming data is set in the control data register of the erase verify voltage generating circuit (S12). S13). Then, an erase voltage is applied for a predetermined time (S14), and an erase verify operation is performed (S15). It is determined whether or not all bits are erased by the erase verify operation (S16), and the operations of steps S11 to S16 are repeated until the all bits are erased. As described above, the trimming data correction process is performed every time the erase voltage is applied, so that the variation in the threshold voltage of the memory cell in the erased state can be suppressed with high reliability.

FIG. 8 shows a microcomputer in which the write verify voltage is corrected by the dedicated arithmetic circuit 50. Reference temperature information of register 15 and register 2
There is provided an adder 12 for calculating a difference from the current temperature information of 0, and the adder 12 provides the difference information (Tm-Tn).
Is calculated and stored in the register 16 as temperature difference information (Tdif in FIG. 3). The temperature difference information Tdif stored in the register 16 is supplied to the conversion circuit 7. The conversion circuit 7 calculates the final temperature information Tlst based on a value obtained by adding the temperature difference information Tdif to the reference temperature information Tm.
Is generated, and the final temperature information Tlst is converted into trimming data corresponding thereto. In the conversion circuit 7, for example, the logic of the data table TBL and the logic of searching the table with the final temperature information Tlst are realized by hardware logic circuits. The process variation compensation data is added to the trimming data converted by the conversion circuit 7 by the adder 13, and the added data is set in the register 19, thereby determining the write verify voltage.

FIG. 9 is a block diagram of a flash memory as another example of the semiconductor device according to the present invention. The flash memory 51 shown in the figure is a semiconductor device of a single flash memory. The flash memory 51 shown in the figure has the flash memory 30 of FIG. 8, the temperature sensor 8, the A / D 9, and the input / output circuit 24, and is formed on a single semiconductor substrate.

FIG. 10 shows an example of a write verify voltage generation circuit using a booster circuit. In the description so far, the write verify voltage is constituted by a voltage regulator using an operational amplifier as exemplified in FIG.
This is because the case where the threshold voltage of the memory cell in the written state is lower than the threshold voltage of the memory cell in the erased state is taken as an example. Conversely, when the threshold voltage of the memory cell in the written state is higher than the threshold voltage of the memory cell in the erased state, the comparison is performed by the comparator 4A. This allows the boosted voltage level to be freely controlled. The specific voltage correction method is the same as described above.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist thereof. No.

For example, the correction calculation method of the trimming data is not limited to the above description, but can be changed as appropriate. Also,
In the above description, a flash memory that stores binary data in one memory cell is described as an example. However, the present invention is also applied to, for example, a nonvolatile memory that stores multi-valued data of four or more values in one memory cell. can do. For example, in the case where quaternary information can be stored in one memory cell, the memory cells have different threshold voltages, and each of the erased state, the first written state, the second written state, and the third written state is different. One state will be selected from among them. In the case of a multi-valued memory, the distribution of the multi-valued threshold voltage must be in a narrower range. Therefore, the present invention which can eliminate or alleviate the temperature dependence of the threshold voltage of the memory cell is a multi-valued memory. The effect is even more remarkable if applied to a nonvolatile memory.

In the above description, mainly the case where the invention made by the present inventor is applied to a microcomputer with a built-in flash memory or a flash memory chip, which is the field of application as the background, but the present invention is not limited to this. , And can be widely applied to other logic LSIs and memories.

[0040]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the verify voltage is changed in such a direction as to offset the variation of the threshold voltage of the memory cell which is to be changed depending on the temperature of the semiconductor device, the temperature dependency of the verify voltage itself and the verify operation Can be offset with the temperature dependence of other circuits related to the threshold voltage, thereby reducing or eliminating the temperature dependence of the threshold voltage in the write or erase state of the memory cell. Therefore, even if the writing is performed at a low temperature, the conventional problem that the depletion margin is significantly deteriorated can be solved. Further, the operation guarantee temperature range at the time of writing or erasing can be expanded, and the usability is improved. Variations in the threshold voltage of the memory cell in the written state or the erased state are reduced, and the reliability of the memory is improved. In addition, since the performance of the sense amplifier and the verify power supply circuit itself is improved to reduce the threshold voltage variation of the memory cell, the sense amplifier and the verify power supply circuit reduce the threshold voltage variation of the memory cell. It is not necessary to pay attention to the above, which contributes to shortening of the design. Further, by using the temperature difference between the reference temperature and the detected temperature, it is possible to operate the temperature information based on the relative value, thereby simplifying the arithmetic processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a detailed example of a portion focusing on generation of a write verify voltage of a flash memory in a microcomputer as an example of a semiconductor device according to the present invention.

FIG. 2 is an overall block diagram of a microcomputer as an example of a semiconductor device according to the present invention.

FIG. 3 is an explanatory view exemplarily showing a relationship among trimming data, a verify voltage, and a notch temperature in a data table.

FIG. 4 is a flowchart showing a method of calculating trimming data.

FIG. 5 is a characteristic diagram showing a relationship between correction control of a write verify voltage and a threshold voltage of a memory cell by the correction control using temperature as a parameter.

FIG. 6 is a flowchart illustrating an example of a write operation to a flash memory.

FIG. 7 is a flowchart illustrating an example of an erasing operation for a flash memory.

FIG. 8 is a block diagram of a microcomputer in which a write verify voltage is corrected by a dedicated arithmetic circuit.

FIG. 9 is a block diagram of a flash memory as another example of the semiconductor device according to the present invention.

FIG. 10 is a block diagram illustrating an example of a write verify voltage generation circuit using a booster circuit.

FIG. 11 is a characteristic diagram showing that a threshold voltage distribution of a memory cell in a written state has temperature dependency.

FIG. 12 is an explanatory diagram exemplifying causes of temperature dependence on a threshold voltage distribution of a memory cell;

[Explanation of symbols]

 Reference Signs List 8 temperature sensor 9 A / D 10 CPU 11 RAM TBL data table D0 to Dn trimming data Tm reference temperature Tn measurement temperature Tdif temperature difference information Tlst final temperature information 22 write verify voltage generation circuit Vwvfy write verify voltage 30 flash memory 33 micro computer 50 Dedicated arithmetic circuit 51 Flash memory

Claims (7)

[Claims] A nonvolatile memory cell capable of electrically erasing and writing, and a verify voltage generating circuit for forming an erase or write verify voltage, wherein an erase verify voltage or write is performed after an erase voltage or a write voltage is applied. In a semiconductor device which performs an erase or write verify operation by applying a verify voltage to a selected word line, a temperature detecting means for detecting a temperature of the semiconductor device, and a verify voltage generated by the verify voltage generating circuit is detected by the temperature detecting means. Control means for making the variable based on the detected temperature, wherein the control means changes the verify voltage in a direction to offset a variation in the threshold voltage of the memory cell which is likely to change depending on the temperature of the semiconductor device. A semiconductor device characterized by being made to cause. 2. The semiconductor device according to claim 1, wherein said control means increases the write verify voltage as the detected temperature is lower. 3. A storage area of a data table in which control data for determining a verify voltage in a predetermined temperature range is arranged in advance at predetermined temperature intervals, wherein said control means stores a temperature between a reference temperature and a detected temperature. 2. The control method according to claim 1, wherein control data for obtaining a verify voltage at the detected temperature is referenced from the data table based on the difference, and the verify voltage is controlled using the referenced control data. Or the semiconductor device according to 2. 4. A storage area for process variation compensation data for compensating a variation related to a verify voltage at a reference temperature caused by a process variation inherent to the semiconductor device, wherein the control means stores the process variation compensation data in the referenced control data. 4. The semiconductor device according to claim 3, wherein the process variation compensation data is added, and a verify voltage is controlled by the added data. 5. The semiconductor device according to claim 1, wherein said control means is a central processing unit and a storage means for storing an operation program thereof. 6. The semiconductor device according to claim 1, wherein said control means is a dedicated arithmetic circuit. 7. The semiconductor device according to claim 1, wherein the nonvolatile memory cell stores multi-valued data of four or more values.