JPS62175998A - Refreshing system for rom - Google Patents

Abstract

PURPOSE:To execute refresh of all memory cells of an EPROM in a short period by executing re-write by a reference value data, only in case a reference value data which has been read out by a usual word line selecting voltage level, and an expected value data which has been read out a word line selecting voltage level used for a test do not coincide with each other. CONSTITUTION:A microprocessor CPU reads out a reference value data which has been read out by a usual word line selecting voltage level, and an expected value data which has been read out by a testing voltage level, from a RAM, and executes an operation for a collation. As a result, in case both the data have coincided, it is decided that a memory cell of a read-out address of an EPROM is normal, and the address is advanced by one and the operation is migrated to a read-out operation of a memory cell of the next address. On the other hand, as a result of operation, in case both the data have not coincided, it is decided that a storage state of the memory cell of the read-out address of the EPROM has dropped, an access is executed again to the EPROM by the same address, and write of the same data as the reference value data, namely, refresh is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a refresh method for ROM (read only memory), and for example, uses FAMO3 (floating gate avalanche processing) as its memory cell.・MOS)）EPROM (erasable & programmable) using transistors, etc.
This technology is effective when used in microprocessors with built-in read-only memory (read-only memory), etc.

[Conventional technology]

Regarding ROMs such as EPROMs, various products are described in the "Hitachi IC Memory Data Book" published by Hitachi, Ltd. in 1985, for example. As these ROMs have become more popular and their application fields have expanded, for example, when they are used as storage devices for IC cards, automobile microcomputers, etc., the environment in which they are used has to be controlled over a relatively large range of temperature and humidity. A situation has arisen where this must be tolerated.

In such a case, it is effective to refresh the stored contents of the memory cells, as is done in dynamic RAM and the like. Regarding the ROM refresh method,
It is described in Japanese Patent No. 0-22438. This refresh method uses a method in which the stored contents of all memory cells of the ROM are read out and the same data is rewritten unconditionally.

[Problem that the invention seeks to solve]

The present inventors have discovered that the above-mentioned conventional method for refreshing the ROM has the following problems. In other words, since the memory contents of all memory cells in the ROM are read out and the same data is rewritten to the same address, it takes a relatively long time to refresh all the memory cells, and Even if the characteristics of the memory cell deteriorate, it cannot be identified.

An object of this invention is to provide a new ROM refresh method.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows. That is,
Comparing and determining reference value data read at a normal word line selection voltage level and expected value data read at a test word line selection voltage level close to a level that would cause relatively erroneous reading, If both data do not match, rewriting is performed using reference value data.

[For production]

By performing the test read, data comparison, and rewrite operations described above on all memory cells when the power is turned on or at regular intervals, rewriting is performed only on memory cells whose memory condition has begun to deteriorate, and all memory cells are rewritten. The object of the present invention is to realize a ROM refresh method that can shorten the time required for refresh, and can identify deterioration in the characteristics of a memory cell and prohibit the use of that memory cell.

〔Example〕

FIG. 1 shows a block diagram of an actual Mfi example of a microcomputer to which the present invention is applied.

In the same figure, the part surrounded by the broken line is the semiconductor integrated circuit L.
It is an SI, and each circuit block formed here constitutes a 1-chip microcomputer as a whole.
It is formed on a single semiconductor substrate such as single crystal silicon using known semiconductor integrated circuit manufacturing techniques.

What is indicated by the symbol CPU is a microprocessor, and the configuration and functions of such a microprocessor CPU can be found, for example, in
Since this is well known from Mitsuharu Yada's Fundamentals of Microcomputers 1 published on October 1, 2015, detailed explanation thereof will be omitted.

Denoted by symbol I10 is an input/output boat,
It contains a data transmission direction register therein. What is indicated by the symbol O5C is an oscillation circuit, which forms a highly accurate reference frequency signal using an externally connected crystal resonator Xtal, although this is not particularly limited. This reference frequency signal forms the clock pulses required in the microprocessor CPU. The symbol RAM is a random access memory, which is mainly used as a temporary storage circuit for programs being executed or data in the middle of an operation. The symbol EPROM indicates eraser pull & programmable read.
It is only memory, and stores programs, dictionary data, etc. for processing various information. The RAM and EPROM include control circuits necessary for read and write operations of the storage elements. Data storage in EFROM is performed using FAMO3 (floating gate avalanche injection MO) used in memory cells.
S)) This is done by setting the threshold voltage of the transistor to either a normal relatively low voltage (logic "1") or a relatively high voltage (logic "0") by charge injection writing to the floating gate.

The symbol VcxCONT indicates a word line voltage control circuit, which controls the word line selection power supply voltage Vcx of the EFROM according to instructions from the microprocessor CPU when refreshing the EFROM.

The above circuit blocks are interconnected by an input/output bus l10BUS centered around the microprocessor CPU. This input/output bus l10BUS includes a data bus and an address bus.

In this actual example microcomputer, EPR
The refresh operation of the OM is roughly performed by the following procedure. That is, the microprocessor CPU starts the refresh operation of the EPROM when the power is turned on or by being activated at predetermined time intervals by a built-in clock device.

After the microprocessor CPU determines the first address to be refreshed, the word line voltage control circuit VcxC
An instruction is given to the ONT to bring the word line selection voltage level to the normal voltage level. Here, the normal voltage level refers to the voltage level near the center of the word line selection voltage level range at which normal reading can be performed in a normal memory cell of the EPROM, and which provides the most stable reading. performs a read operation of the EPROM using the above-mentioned first address, and stores the read data in the RAM as reference value data. EF used in the microcomputer of this embodiment
The ROM is a ROM that is accessed in units of 8 bits, and 8-bit reference value data can be obtained by - times of read operations.

Next, the microprocessor CPU instructs the word line voltage control circuit VcxCONT to bring the word line selection voltage level to the test voltage level. Here, the test voltage level is a word line selection voltage that is close to the limit that does not erroneously read write data of logic "0", which is set as a high threshold voltage, as logic "1" in a normal memory cell of EFROM. Indicates level. At this test voltage level, in a memory cell whose characteristics have begun to deteriorate, the charge injected into the floating gate decreases and the threshold voltage decreases, so logic "O" is read as logic 11t11. The microprocessor CPIJ reads the EFROM using the same address and stores the 8-bit read data in the RAM as expected value data.

Here, the microprocessor CPU reads the reference value data previously read out at the normal word line selection voltage level and the expected value data read out at the test voltage level from the RAM, and performs calculations for comparison. If they match, it is determined that the memory cell at the read address of the EPROM is normal, and the address is advanced by one and the read operation for the memory cell at the next address is started. On the other hand, if the two data do not match as a result of the calculation, it is assumed that the storage state of the memory cell at the read address of the EPROM has deteriorated, and the EPROM is accessed again at the same address to obtain the same data as the reference value data. Write or refresh. Although not particularly limited, after the above rewriting,
The microprocessor CPU performs a test read on the memory cell at the same address again and makes a judgment. If there is no limit, it proceeds to the next address, but if the two data do not match again, the characteristics of that memory cell have deteriorated. regarded as. The microprocessor CPU registers the address of the memory cell whose characteristics are considered to have deteriorated, and proceeds to the next address.

Read, judge, and rewrite operations on EP RO
When the refresh operation is performed for all M addresses, the microprocessor CPU finishes the refresh operation and moves on to other arithmetic processing.

FIG. 2 shows a block diagram of an embodiment of the EPROM incorporated in the microcomputer.
The operating power supplies are a logic voltage system such as 5.5 and a write voltage system of a high level such as 10-odd V due to the power supply voltage VPp, and the logic voltage system is used during normal read operations.

Furthermore, the word line selection voltage level for selecting a word line is determined by the power supply voltage Vcx supplied from the word line voltage control circuit VcxCONT.

EPROM has address input terminals XO to Xi and YO
−yj and the control terminal G.
Its operation is controlled by chip enable signals, output enable signals, and program signals supplied via E, OE, and PGM. These control signals are activated by the microprocessor CPU (not shown).
It is relayed or formed by the memory control circuit in the ROM.

The EPROM in this embodiment performs memory read or write operations in 8-bit units, but in FIG.
One bit of memory array M-ARY is representatively shown. Memory array M-ARY includes multiple FAMO3
) transistor (non-volatile memory element... MO3FETQ
I to Q6), a plurality of word lines including word lines Wl and W2, and a plurality of data lines including data lines Di, D2 and D3. In memory array M-ARY, FAMO3) transistor Q1 arranged in the same row
The control gates of ~Q3 (Q4~Q6) are connected to the corresponding word lines Wl and W2, respectively, and the drains of the FAMO5) transistors Ql and Q4, Q2 and Q5, and Q3 and Q6 arranged in the same column are connected to the corresponding word lines Wl and W2, respectively. The data lines D1 to D3 are connected to the data lines D1 to D3. The common source line C8 of the FAMO5) transistors is not particularly limited, but
Grounded via depletion type MO3FET QIO.

An X address signal and a Y address signal supplied from the microprocessor CPU via address terminals xo-xt and YO to Yj are input to an X address buffer XADB and a Y address buffer YADB. Address buffer XADB.

YADB is operated by the timing signal ce formed by the control circuit C0NT and is controlled by the microprocessor CP.
It takes in the address signal supplied from U, forms a complementary address signal consisting of internal address signals in phase with it and in phase with it, and supplies it to X address decoder XDCR and Y address decoder YDCH.

The X address decoder XDCR is the X address buffer
A selection signal for selecting a word line of memory array M-ARY is formed according to a complementary address signal supplied by ADB. The voltage level of the word line selection signal formed by the X address decoder XDCH is equal to the power supply voltage Vcx supplied from the word line voltage control circuit VcxCONT.
0 During normal read and write operations, the word line selection voltage level is the normal voltage level, that is, the most stable voltage level within the voltage level range that allows normal reading in normal memory cells of the EPROM. The voltage level is set near the center where reading is performed.

In addition, during the refresh operation of the EFROM, under the control from the microprocessor CPU, the normal voltage level and the test voltage level as described above, that is, the logic "" set to a high threshold voltage in the normal memory cell of the EPROM, are controlled by the microprocessor CPU. The word line selection voltage level is repeatedly changed to a level close to the limit at which the write data of "0" is not erroneously read as logic "1". On the other hand, memory array M-A
The level of the selection signal required by RY is the low level of s' o v, which is the high level lowered below the power supply voltage VCC as will be described later, in the read operation, but y' in the write operation. The high level of the write voltage Vl)p level is '>' o vO low level. Therefore, the X address decoder
Memory array M-A responds to a selection signal output from memory array M-A.
In order to set each word line of RY to the required level, a depletion type MO3F is connected between the output terminal of the X address decoder XDCR and each word line of the memory array.
ETQI 1 to Q12 are provided. Further, a write high voltage load circuit 'gPrXR is provided between each word line and the write voltage power supply terminal Vpρ for supplying the write voltage Vl)p to the word line during the writing operation. The depletion type MO3FETs QII to Q12 have their gates supplied with an internal write control signal outputted from the control circuit CONT. The voltage level of the internal write control signal 1 is 1, which is like a ground potential during a write operation, and the voltage level of the X address decoder XD during a read operation.
The voltage is set to the same high level as the selection voltage level from CR.

In the read operation, the internal write control signal we is set to the word line selection voltage level from the X address decoder XDCR and the same voltage level as described above. Therefore, MO5FETs QI 1 and Q12 are turned on by the word line selection signal output from the X address decoder XDCR.

Therefore, the output of the X address decoder XDCR is directly transmitted to each word line.

On the other hand, in a write operation, the internal write control signal we
is set to the low level of ＼゛0■. Therefore, for example, the word 1llW is set by the X address decoder XDCR.
When 1 is selected, its potential is at the selection voltage level, so the MO3FET QII is automatically turned off because the voltage applied to its gate is brought to a negative level relative to the voltage applied to its source. Ru. Accordingly,
The word line W1 is set to the level H/f, which is the level of the 1' write voltage Vpp, by the high voltage load circuit XR. On the other hand, if the voltage level of the word line is at the low level of OV, such as word line -v2 which is not selected by the X address decoder XDCR, the MO3FE
TQ12 remains in the off state. Therefore, word line W
2 is VQv depending on the row address decoder XDCR.
is set to low level.

By the way, each word line is equipped with a constant voltage circuit VC that clamps the potential of the word line and a constant voltage circuit VC that clamps the potential of the word line to prevent erroneous reading due to the potential of the word line becoming higher than necessary during normal read operation. A switch MOS FET is provided for connection to the MOS FET. MO3FETQI
A control signal re is supplied to the gates of the MO3FET switches represented by MO3FETs 6 and Q17, which becomes a low level when reading at a test voltage level during a write operation or a refresh operation, and which becomes a f level during normal reading. Ru. As a result, during normal read operation, these switches MOS I"ET are turned on and a constant voltage circuit is selected for the selected word line, so the voltage level of the word line is adjusted to ensure more stable readout. Clamped to voltage level.

In FIG. 2, the memory array M-ARY is provided with a common data line CD, and between each data line of the memory array M-ARY and the common data line CD is an MO5F E' which constitutes a column switch circuit C8W. 1' Q 7～Q
9 is provided.

Y address decoder YDCR is address buffer YA
A complementary address signal supplied by DB forms a selection signal for selecting a data line of memory array M-ARY. The Y address decoder YDCR operates using a +5V logic voltage system. Y address decoder YD
The selection signal output from CR is sent to column switch circuit c
It is supplied to the gates of MOS F' ET Q7 to Q9 of Sw, and is used for controlling the column switch C8W.

Here, the column switch circuit C3W is required to have the ability to transmit a write signal at a write voltage level in a write operation. In order to turn on and off the column switch MO3FET sufficiently, the Y address decoder YDC
R output terminal and column switch MO3FET gate,
That is, depletion type MO3FETs Q13 to Q15 are arranged between the column selection line and the column selection line. The internal write control signal WO is supplied to the gates of these MO3FETs Q13 to Q15, similarly to the MO5FETs QI 1 to Q12. A write high voltage load circuit YR similar to that for the word line is provided between each of the column selection lines and the high voltage vpp.

The common data line CD is coupled to an output terminal of a data input circuit DIB that receives a write data signal input via terminals DIO-DI7.

4. The output circuit of the data input circuit DIB sends out the write voltage vpp via the output MO5FET which is turned on and off according to the write data signal supplied from the microprocessor CPU. This output circuit is configured such that its output impedance is in a high impedance state when the harmful pulse we is at a low level (read operation).

The input terminal of the data output circuit DOB is the common data line CD
is combined with The data output circuit DOB is composed of a sense amplifier, an output cover that receives the output from the sense amplifier, and two ports.

Although the sense amplifier is not particularly limited, the common data line C
It has a bias circuit for supplying bias current to D. This bias circuit is activated by a read control signal Oe supplied from the control circuit C0NT, and outputs a bias current in the activated state. The bias circuit is provided with appropriate level detection functionality. As a result, a bias current is generated when the input level of the data output circuit DOB is below a predetermined potential, and the bias current becomes substantially O when the input level reaches the predetermined potential.

The selected memory cell has a relatively low threshold voltage (,!I2i logic “1”) in the initial state where no writing is performed.
), and when a write occurs and charge is injected into its floating gate, a relatively high threshold voltage (logic “
O”).

If the selected memory cell in the memory array M-ARY has a high threshold voltage (logic "0'), the common
No direct current path is formed between the data line CD and the ground point of the circuit. In this case, the common data line CD is brought to a relatively high level by current supply from the sense amplifier. Supply of bias current from the bias circuit in the sense amplifier is substantially stopped when the common data line CD reaches a predetermined potential. Therefore, the high level of the common data line is limited to a relatively low potential.

On the other hand, if the selected memory cell in the memory array M-ARY has a low threshold voltage (“l”), a column switch MO3FET is connected between the common data line CD and the ground point of the circuit, and the data line , a DC current path is formed through the selected memory cell and MO5FETQIO. Therefore, the common data line CD becomes low level regardless of the bias current supplied from the bias circuit. Common data line C by such a bias circuit
Limiting the amplitude of D between high and low levels provides the following advantages. That is, even though there is a stray capacitance or the like that limits the signal change speed in the common data line CD, etc., it is possible to increase the read speed.

The operation of the output sofa in the data output circuit DOB is controlled by the read control signal oe. When the control signal Oe is at a high level, the output sofa outputs a data signal at a level corresponding to the signal supplied from the sense amplifier to the external terminals DIO to DI7. On the other hand, when the control signal Oe is at a low level, the output sofa is in a high output impedance state.

The control circuit C0NT is activated by the power supply voltage Vcc, and is activated by instructions from the microprocessor CPU.
Various control signals are formed according to a write high voltage vpp, a chip enable signal CE, an output/enable signal OE, and a program signal PGM supplied from a memory control circuit of an EPROM (not shown). The control circuit C0NT identifies operation modes such as normal read, write, and test read based on the combination of the control signals.

As shown in the above embodiment, when the present invention is applied to refreshing an EP ROM built into a microcomputer, the following effects can be obtained. That is, (11) the reference value data read at the normal word line selection voltage level and the expected value data read at the test word line selection voltage level close to the level that would cause relatively erroneous reading. By comparing and determining, and rewriting with reference value data only if the two data do not match,
The effect is that all memory cells of the EPROM can be refreshed in a relatively short time.

(2) Due to the refresh operation described in (1) above, even in relatively harsh usage environments such as IC cards and automatic microcomputers, it is not affected by the storage data retention time of E F ROM, etc., and is stable. The advantage is that it is possible to provide a storage device that is

(3) By repeating readout and determination in the riff L/TSH operation, memory cells whose characteristics have deteriorated and are no longer usable can be identified, and the microprocessor CP
U has the effect of avoiding the use of such memory cell addresses.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in this embodiment, the reading and determination operations by the microprocessor CPU were performed for each address of the EPROM.
It is also possible to perform this in units of a plurality of addresses at once. Also, the refresh operation for all addresses is set to 1.
For example, it is not necessary to do this in batches; for example, divide all addresses into several addresses, and then
It is also possible to refresh all the addresses by refreshing the first divided address, then refreshing the second divided address at the next refresh operation, and repeating this sequentially. This allows the refresh operation time to be further shortened. In addition, the reference value data read out at the normal voltage level and the expected value data read out at the test voltage level are not stored in RAM, but are held in a register in the microprocessor CPU for comparison and judgment. It may be. Furthermore, in order to determine the characteristic deterioration, it is also possible to write a specific reference pattern and test read it.

In the above explanation, the invention made by the present inventor was mainly applied to refreshing the EFROM of a microcomputer, which is the background field of application, but the invention is not limited to this. EPRO in various control devices etc.
It can be used to refresh M, EIF, PRCM (Electrically Erasable & Programmable ROM), etc. In addition, the above embodiments also use E as a data memory.
PROM, EEPROM, etc. 7 L/S, As explained above, this applies to a device that determines logic using an electrically writable non-volatile memory element as shown in Japanese Patent Application Laid-Open No. 58-85638. It can also be applied to refreshing the electrically writable nonvolatile memory element. The present invention can be used as a refresh method for an electrically writable ROM included in a device having at least an arithmetic circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, the reference value data read at the normal word line selection voltage level is compared with the expected value data read at the test word line selection voltage level, which is relatively close to the level that would cause erroneous reading. However, by rewriting with the reference value data only when the two data do not match, it is possible to refresh all memory cells of the EPROM in a relatively short time, and it is also possible to identify memory cells whose characteristics have deteriorated. It is what it is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a one-chip microcomputer used in the present invention, and FIG. 2 is a block diagram showing one embodiment of the E,PROM. CPU...Microprocessor, RAM...Rung access memory, EPROM...Erasable &
Programmable read-only memory, Ilo
...I/O board, O20...Oscillation circuit, l10BU
S...I/O bus, VcxCONT...Word line voltage control circuit, M-ARY...Memory array, XDCR
...X address decoder, YDCR...Y address decoder, XADB...X address buffer, YAD
B...Y address buffer, DOB...data output circuit, DIB...data input circuit, C0NT...control circuit, XR-YR...write high voltage load circuit, V
C... To constant voltage circuit X'-7.

Claims (1)

[Claims] 1. In a device including a ROM and a word line voltage control circuit that controls a word line selection voltage level of the ROM, a first
The reference value data read out at the word line selection voltage level and the expected value data read out at the second word line selection voltage level are compared and determined, and memory cells in which the reference value data and the expected value data do not match are determined. The refresh method is characterized by rewriting the data. 2. The ROM is an EPROM or an EEPROM, and the first word line selection voltage level is the most stable readout voltage level within the range of wordline selection voltage levels that allow normal reading in normal memory cells of the ROM. This is the voltage level near the center where the second
The word line selection voltage level is close to the limit at which write data of logic "0" with a high threshold voltage is not erroneously read as logic "1" in a normal memory cell of the ROM. A refresh method according to claim 1, characterized in that: 3. The word line voltage control circuit controls the word line selection voltage level by changing the word line selection power supply voltage of the ROM according to instructions from the arithmetic circuit. The refresh method described in the first or second item of the range. 4. Claims 1, 2, or 3, characterized in that the arithmetic circuit performs or repeats the reading and determination operations to identify memory cells whose ROM characteristics have deteriorated. Refresh method described.