JPH11288889A - Thin-film deposition method through plasma cvd - Google Patents

Thin-film deposition method through plasma cvd

Info

Publication number
JPH11288889A
JPH11288889A JP10091285A JP9128598A JPH11288889A JP H11288889 A JPH11288889 A JP H11288889A JP 10091285 A JP10091285 A JP 10091285A JP 9128598 A JP9128598 A JP 9128598A JP H11288889 A JPH11288889 A JP H11288889A
Authority
JP
Japan
Prior art keywords
thin film
plasma cvd
substrate
electrode
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10091285A
Other languages
Japanese (ja)
Other versions
JP3540149B2 (en
Inventor
Hitoshi Nishio
仁 西尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kanegafuchi Chemical Industry Co Ltd
Original Assignee
Kanegafuchi Chemical Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kanegafuchi Chemical Industry Co Ltd filed Critical Kanegafuchi Chemical Industry Co Ltd
Priority to JP09128598A priority Critical patent/JP3540149B2/en
Publication of JPH11288889A publication Critical patent/JPH11288889A/en
Application granted granted Critical
Publication of JP3540149B2 publication Critical patent/JP3540149B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

PROBLEM TO BE SOLVED: To provide a method for depositing a thin film of uniform thickness through a plasma CVD method, so as to cover a conductive layer formed on an insulating board. SOLUTION: A thin-film deposition method is carried out through a plasma CVD method in a manner, where a first conductive thin film 5 is formed covering all the primary surface of an insulating board 3, isolating grooves 7 which are substantially rectilinear and parallel with each other are provided to the first thin film 5 so as to divide it into several regions, and when a second thin film is deposited through a CVD method to cover the first conductive thin film 5, the isolating grooves 7 are formed to have each provided with at least one non-groove region 7x of a prescribed length.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、絶縁性基板上に形
成された導電性の第1の薄膜上にプラズマCVDによっ
て第2の薄膜を堆積させる方法の改善に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a method for depositing a second thin film by plasma CVD on a first conductive thin film formed on an insulating substrate.

【0002】[0002]

【従来の技術】プラズマCVDによる薄膜堆積方法を利
用して製造される装置の一例として、集積型薄膜太陽電
池がある。一般に、集積型薄膜太陽電池モジュールにお
いては、比較的大きな単一の絶縁性基板上に順次積層さ
れた第1電極層、半導体光電変換層および第2電極層が
複数の光電変換セルを形成するように実質的に直線状で
互いに平行な複数の分離溝によって分離されていて、そ
れらの複数のセルが電気的に直列接続された構造が採用
されている。そして、その半導体光電変換層は、一般に
プラズマCVDによって堆積される。このような集積型
薄膜太陽電池モジュールの一部の例が、図2の概略的な
断面図において示されている。
2. Description of the Related Art As an example of an apparatus manufactured by using a thin film deposition method by plasma CVD, there is an integrated thin film solar cell. Generally, in an integrated thin-film solar cell module, a first electrode layer, a semiconductor photoelectric conversion layer, and a second electrode layer sequentially stacked on a single relatively large insulating substrate form a plurality of photoelectric conversion cells. A structure in which the cells are separated by a plurality of substantially linear and parallel separation grooves, and the plurality of cells are electrically connected in series is adopted. Then, the semiconductor photoelectric conversion layer is generally deposited by plasma CVD. An example of a part of such an integrated thin-film solar cell module is shown in the schematic sectional view of FIG.

【0003】図2に示されている集積型薄膜太陽電池モ
ジュール20においては、たとえばガラス等の透光性絶
縁基板3上に透光性導電薄膜からなる第1電極層5が形
成されており、これは互いに平行な直線状の複数の第1
電極分離溝7によって複数の第1電極5a,5b,5c
に分離されている。第1電極層5上には、pin接合な
どの半導体接合を含む薄膜半導体光電変換層11がプラ
ズマCVDによって堆積されており、これは第1電極分
離溝7に平行な複数の接続用開口溝8によって複数の光
電変換領域11a,11b,11cに分割されている。
光電変換層11上には適当な金属からなる第2電極層1
5が形成されており、これも第1電極分離溝7に平行な
複数の分離溝9によって複数の第2電極15a,15
b,15cに分離されている。
In the integrated thin-film solar cell module 20 shown in FIG. 2, a first electrode layer 5 made of a light-transmitting conductive thin film is formed on a light-transmitting insulating substrate 3 such as glass. This comprises a plurality of linear first
The plurality of first electrodes 5a, 5b, 5c are formed by the electrode separation grooves 7.
Are separated. On the first electrode layer 5, a thin film semiconductor photoelectric conversion layer 11 including a semiconductor junction such as a pin junction is deposited by plasma CVD, and the thin film semiconductor photoelectric conversion layer 11 includes a plurality of connection opening grooves 8 parallel to the first electrode separation groove 7. Is divided into a plurality of photoelectric conversion areas 11a, 11b, 11c.
On the photoelectric conversion layer 11, the second electrode layer 1 made of a suitable metal
5 are also formed, and the plurality of second electrodes 15a, 15a are also formed by a plurality of separation grooves 9 parallel to the first electrode separation grooves 7.
b, 15c.

【0004】このようにして、1つの基板3上で、複数
の光電変換領域11a,11b,11cに対応して複数
の光電変換セル17a,17b,17cが形成されてい
る。これらの光電変換セルの任意のセル17bの第1電
極5bは、接続用溝8を介して、隣接するセル17aの
第2電極15aに電気的に接続されている。すなわち、
基板3上で、複数の光電変換セル17a,17b,17
cが電気的に直列接続されて集積化されている。
In this way, a plurality of photoelectric conversion cells 17a, 17b, 17c are formed on one substrate 3 corresponding to the plurality of photoelectric conversion regions 11a, 11b, 11c. The first electrode 5b of any of the photoelectric conversion cells 17b is electrically connected to the second electrode 15a of the adjacent cell 17a via the connection groove 8. That is,
On the substrate 3, a plurality of photoelectric conversion cells 17a, 17b, 17
c are electrically connected in series and integrated.

【0005】図3は、図2に示された集積型薄膜太陽電
池モジュールの半導体層11を堆積する前において、基
板3上の第1電極層5が第1電極分離溝7によって複数
の第1電極5a,5b,5cに分離された状態を断面図
で示しており、図4は図3の状態に対応する上面図であ
る。図3と図4からわかるように、第1電極層5の電極
分離溝7は、長方形基板3の長手方向のほぼ全長にわた
って形成されている。これは、基板面積に占める光電変
換セルの面積をできる限り多く取って、光発電のための
有効面積を大きくすることによって、太陽電池モジュー
ル全体としての出力を高めるためである。すなわち、こ
うすることによって、光電変換セルの単位面積あたりの
真性効率が同じであっても、太陽電池モジュール全体と
しての出力を向上させることができる。
FIG. 3 shows that the first electrode layer 5 on the substrate 3 is formed by a plurality of first electrode separation grooves 7 before the semiconductor layer 11 of the integrated type thin film solar cell module shown in FIG. FIG. 4 is a cross-sectional view showing a state where the electrodes 5a, 5b, and 5c are separated from each other. FIG. 4 is a top view corresponding to the state shown in FIG. As can be seen from FIGS. 3 and 4, the electrode separation groove 7 of the first electrode layer 5 is formed over substantially the entire length of the rectangular substrate 3 in the longitudinal direction. This is because the output of the solar cell module as a whole is increased by taking as much as possible the area of the photoelectric conversion cells in the substrate area and increasing the effective area for photovoltaic power generation. That is, by doing so, even if the intrinsic efficiency per unit area of the photoelectric conversion cells is the same, the output of the entire solar cell module can be improved.

【0006】[0006]

【発明が解決しようとする課題】他方、このような集積
型薄膜太陽電池モジュール20においては、当然のこと
ながら1枚の基板3あたりの出力を少しでも高くする必
要があり、そのためには、特に光発電に寄与する半導体
薄膜層11の局所的な膜厚変動をできるだけ小さくしな
ければならない。たとえば、50段の光電変換セルを直
列接続した集積型薄膜太陽電池モジュール20を想定し
た場合、50段のセル中で1段のセルの短絡光電流(I
SC)が他の49段のセルに比較して10%だけ低い場合
でも、実際にそのモジュール20全体を流れるISCとし
ても、その10%だけ低い値になってしまう。このと
き、半導体薄膜層11の局所的な膜厚変動が直接的にI
SCに影響するわけではないが、密接な相関関係があるこ
とは確かである。また、半導体薄膜層11中で局所的に
膜厚が異常に薄い部分が存在すれば、第1電極層5と第
2電極層15との間で局所的な短絡欠陥部分ができやす
くなる。もしそうなれば、集積型薄膜太陽電池モジュー
ル20の開放端電圧(VOC)や曲線因子(FF)も低下
してしまう。
On the other hand, in such an integrated thin-film solar cell module 20, it is naturally necessary to increase the output per one substrate 3 as much as possible. The local thickness variation of the semiconductor thin film layer 11 that contributes to photovoltaic power generation must be minimized. For example, assuming an integrated thin-film solar cell module 20 in which 50 stages of photoelectric conversion cells are connected in series, the short-circuit photocurrent (I
SC ) is 10% lower than that of the other 49-stage cells, but the value of I SC actually flowing through the entire module 20 is lower by 10%. At this time, local film thickness variation of the semiconductor thin film layer 11 is directly
It does not affect SC , but it does have a close correlation. In addition, if there is a locally abnormally thin portion in the semiconductor thin film layer 11, a local short-circuit defect portion between the first electrode layer 5 and the second electrode layer 15 is likely to be formed. If this happens, the open-circuit voltage (V OC ) and fill factor (FF) of the integrated thin-film solar cell module 20 will also decrease.

【0007】ここで、プラズマCVDのようにグロー放
電分解による薄膜堆積法において、膜厚の局所的変動が
発生する原因としては、高周波電極と接地電極との間の
距離の局所的な変動、膜堆積面内におけるプロセスガス
濃度の分布、さらには絶縁性基板の使用に起因する膜堆
積面内における電位勾配の分布などが考えられる。
Here, in a thin film deposition method by glow discharge decomposition such as plasma CVD, local fluctuations in the film thickness are caused by local fluctuations in the distance between the high-frequency electrode and the ground electrode, and the film thickness. The distribution of the process gas concentration in the deposition surface, the distribution of the potential gradient in the film deposition surface due to the use of the insulating substrate, and the like can be considered.

【0008】たとえば、絶縁性基板11上に形成された
透光性の導電性酸化物層のように導電率が比較的小さな
導電体層5を分離溝7によって分離し、それらの互いに
分離された複数の島状導電体領域を覆うようにプラズマ
CVDで半導体薄膜11を堆積する場合、導電体層5内
において接地電極に対する抵抗値の局所的な差異がかな
り大きくなり、かつ平均の抵抗値の上昇が生じる。ま
た、接地電極と同電位にある基板装着用治具と基板3と
は膜堆積を期待していない基板周囲部で機械的に接触し
ているだけであり、その治具の変形や基板の寸法精度等
に依存して電気的な接続状態が変動し得るという問題が
ある。この問題が解決されている場合でも導電率が大き
くない導電体層5が用いられているときには、接地電位
部に対して膜堆積面の周囲部と中央部における抵抗値に
ついて大きな差があり、この差は基板サイズが大きくな
ればなるほど顕著になる。このような比較的小さな導電
率を有する導電体層5上に半導体薄膜11を堆積すると
き、特に放電状態が不安定な場合や放電電力が弱いとき
には、半導体層11の局所的な膜厚変動が増大してしま
う。
For example, a conductor layer 5 having a relatively small conductivity, such as a light-transmitting conductive oxide layer formed on an insulating substrate 11, is separated by a separation groove 7 and separated from each other. When the semiconductor thin film 11 is deposited by plasma CVD so as to cover a plurality of island-shaped conductor regions, the local difference in the resistance value with respect to the ground electrode in the conductor layer 5 becomes considerably large, and the average resistance value increases. Occurs. Further, the substrate mounting jig having the same potential as the ground electrode and the substrate 3 are only in mechanical contact with each other at the periphery of the substrate where film deposition is not expected. There is a problem that an electrical connection state may fluctuate depending on accuracy or the like. Even when this problem is solved, when the conductor layer 5 having a low conductivity is used, there is a large difference in the resistance value between the peripheral portion and the central portion of the film deposition surface with respect to the ground potential portion. The difference becomes more pronounced as the substrate size increases. When the semiconductor thin film 11 is deposited on the conductor layer 5 having such a relatively small conductivity, particularly when the discharge state is unstable or when the discharge power is weak, local variation in the film thickness of the semiconductor layer 11 may occur. Will increase.

【0009】このような状況下において、大面積の絶縁
性基板3上に堆積する半導体薄膜11の局所的な膜厚変
動を低減させるために、従来からさまざまな方法が採用
されている。
Under such circumstances, various methods have conventionally been employed to reduce local fluctuations in the film thickness of the semiconductor thin film 11 deposited on the insulating substrate 3 having a large area.

【0010】その第1の方法においては、基板面とそれ
に対向する高周波電極面の平坦性を確保し、かつそれら
両面が正確に平行になるように基板と電極の間の距離が
調整される。これによって、基板と高周波電極との間の
局所的な電位変動が低減され、堆積される薄膜の局所的
な厚さ変動が低減され得る。しかし、この方法では、長
期間にわたる電極の変形のような経時変化には対応でき
ないので、電極の配置の定期的な修正が必要となる。
In the first method, the flatness between the substrate surface and the high-frequency electrode surface facing the substrate surface is ensured, and the distance between the substrate and the electrodes is adjusted so that both surfaces are exactly parallel. Thereby, local potential fluctuation between the substrate and the high-frequency electrode can be reduced, and local thickness fluctuation of the deposited thin film can be reduced. However, this method cannot cope with a temporal change such as deformation of the electrode over a long period of time, so that it is necessary to periodically correct the arrangement of the electrode.

【0011】第2の方法としては、プロセスガスの導入
方法を工夫して、膜堆積面の全体に均一にガスが供給さ
れるようにする方法がある。一般的なガスの導入法とし
ては、高周波電極板を中空にして、基板3に対向する面
に微小な開口孔を均一に多数設ける方法がある。また、
この高周波電極の中空内部でそれらの開口孔までに複数
の邪魔板を電極面に平行に配置することによって、基板
表面に向けて均一にガスを導入する方法もある。さらに
は、基板に平行な面内においてガス導入用配管のコンダ
クタンスが等しくなるように、その面内に配管を対称形
の配置にして、適当な部位にガス導入用開口を設けるこ
とによって均一にガスを導入する方法もある。
As a second method, there is a method in which a method of introducing a process gas is devised so that the gas is uniformly supplied to the entire film deposition surface. As a general gas introduction method, there is a method in which a high-frequency electrode plate is hollow and a large number of minute opening holes are uniformly provided on a surface facing the substrate 3. Also,
There is also a method in which a plurality of baffle plates are arranged parallel to the electrode surface in the hollow interior of the high-frequency electrode up to their opening holes, thereby uniformly introducing gas toward the substrate surface. Furthermore, the gas introduction pipe is arranged symmetrically in the plane parallel to the substrate so that the conductance of the gas introduction pipe becomes equal, and the gas introduction opening is provided at an appropriate portion to uniformly distribute the gas. There is also a method to introduce.

【0012】通常は、上述のような方法のいくつかを適
当に組合せて、均一な半導体薄膜11の堆積が行なわれ
ている。ただし、絶縁性基板3が大きくなって膜堆積面
積が大きくなればなるほど、プラズマCVDにおける放
電状態が不安定な場合や放電電力が小さいときには、堆
積される半導体膜11の局所的な膜厚変動が大きくなる
傾向がある。
Normally, the semiconductor thin film 11 is uniformly deposited by appropriately combining some of the above methods. However, as the insulating substrate 3 becomes larger and the film deposition area becomes larger, when the discharge state in the plasma CVD is unstable or the discharge power is small, the local film thickness variation of the semiconductor film 11 to be deposited becomes larger. Tends to be larger.

【0013】以上のような従来の技術の状況に鑑み、本
発明は、絶縁性基板上で複数の領域に分離された導電性
の第1の薄膜を覆うように第2の薄膜をプラズマCVD
で堆積する場合に、主にプラズマCVD装置側のパラメ
ータのみで制御していた第2の薄膜の局所的な厚さ変動
の抑制をさらに基板側の構造を工夫して抑制し、局所的
な膜厚変動の非常に少ない第2の薄膜を堆積する方法を
提供することを目的としている。
In view of the state of the prior art as described above, the present invention provides a method of forming a second thin film on an insulating substrate by plasma CVD so as to cover the first conductive thin film separated into a plurality of regions.
In the case of depositing by the method, the local thickness fluctuation of the second thin film, which is controlled mainly by only the parameters of the plasma CVD apparatus, is further suppressed by devising the structure on the substrate side. It is an object of the present invention to provide a method for depositing a second thin film having a very small thickness variation.

【0014】[0014]

【課題を解決するための手段】本発明におけるプラズマ
CVDによる薄膜堆積方法は、絶縁性基板の1主面全体
を覆うように導電性の第1の薄膜を形成し、その第1薄
膜を複数の領域に分離するように実質的に直線状で互い
に平行な複数の分離溝を形成し、そして第1薄膜を覆う
ようにプラズマCVDによって第2の薄膜を堆積させる
方法であって、それらの分離溝の各々が所定長さの溝中
断領域の少なくとも1つを含んでいることを特徴として
いる。
According to the method of depositing a thin film by plasma CVD of the present invention, a conductive first thin film is formed so as to cover one entire main surface of an insulating substrate, and the first thin film is formed into a plurality of thin films. A method of forming a plurality of substantially linear and parallel separation grooves so as to separate into regions, and depositing a second thin film by plasma CVD so as to cover the first thin film, wherein the separation grooves are formed. Include at least one of the groove interrupted regions of a predetermined length.

【0015】本発明のこのような薄膜堆積方法によれ
ば、絶縁性基板上に形成された透光性の導電性酸化物層
のように比較的導電率が小さな導電体層を複数の分離溝
によって分離し、それらの分離された複数の島状導電体
領域を覆うように第2の薄膜をプラズマCVDで堆積す
る場合に、接地電位に対する導電体層の局所的な抵抗値
の変動と抵抗値の平均値が低減されるので、プラズマC
VDにおける放電状態が不安定な場合や放電電力が小さ
いときでも、導電体層上に堆積される第2の薄膜の局所
的な膜厚変動を小さくすることができる。
According to such a thin film deposition method of the present invention, a conductive layer having a relatively small conductivity, such as a light-transmitting conductive oxide layer formed on an insulating substrate, is formed by a plurality of separation grooves. And when the second thin film is deposited by plasma CVD so as to cover the plurality of separated island-shaped conductor regions, the local resistance value variation and resistance value of the conductor layer with respect to the ground potential Is reduced, the plasma C
Even when the discharge state in VD is unstable or when the discharge power is small, local thickness fluctuation of the second thin film deposited on the conductor layer can be reduced.

【0016】[0016]

【発明の実施の形態】図1において、本発明の実施の形
態の一例を説明するために、絶縁性基板3上に形成され
た導電性の第1の薄膜5が模式的な上面図で示されてい
る。この図1においては、図4の場合と同様に、基板3
上に形成された第1電極層5の電極分離溝7が、長方形
基板3の長手方向のほぼ全域にわたって形成されてい
る。しかし、基板3の長手方向の中央部においては、電
極分離溝7の各々について溝中断領域7xが1ヶ所設け
られている。なお、この透明電極層5中の溝中断領域7
xに関しては、分離溝1本あたりのその数、位置、およ
び長さについて特に限定されるものではない。
FIG. 1 is a schematic top view showing a conductive first thin film 5 formed on an insulating substrate 3 in order to explain one embodiment of the present invention. Have been. In FIG. 1, as in the case of FIG.
The electrode separation groove 7 of the first electrode layer 5 formed thereon is formed over substantially the entire area of the rectangular substrate 3 in the longitudinal direction. However, at the central portion in the longitudinal direction of the substrate 3, one groove interruption region 7 x is provided for each of the electrode separation grooves 7. The groove interruption region 7 in the transparent electrode layer 5
Regarding x, the number, position, and length of each separation groove are not particularly limited.

【0017】基板3としてガラスや透明樹脂等の透光性
絶縁基板が用いられる場合、通常は、第1電極層5とし
て透光性酸化物導電材料が用いられる。しかし、この第
1電極層5のための具体的な材料は特に限定されるもの
ではなく、周知の導電材料から適宜に選択して用いるこ
とができる。
When a light-transmitting insulating substrate such as glass or transparent resin is used as the substrate 3, a light-transmitting oxide conductive material is usually used for the first electrode layer 5. However, the specific material for the first electrode layer 5 is not particularly limited, and can be appropriately selected from known conductive materials and used.

【0018】第1電極層5上に形成される第2の薄膜に
用いられる材料も特に限定されるものではなく、プラズ
マCVDによって堆積され得る材料であればよい。たと
えばそれが非晶質シリコン系半導体材料の場合には、非
晶質シリコン、水素化非晶質シリコン、水素化非晶質シ
リコンカーバイド、水素化非晶質シリコンナイトライド
の他に、炭素、ゲルマニウム、錫などを含む非晶質シリ
コン合金も含まれる。さらに、これらの各種半導体材料
に、p型またはn型のドーパント元素を添加することに
よって、荷電子制御を行なった材料の薄膜も堆積され得
る。
The material used for the second thin film formed on the first electrode layer 5 is not particularly limited as long as it can be deposited by plasma CVD. For example, when it is an amorphous silicon-based semiconductor material, in addition to amorphous silicon, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, hydrogenated amorphous silicon nitride, carbon, germanium And an amorphous silicon alloy containing tin or the like. Further, by adding a p-type or n-type dopant element to these various semiconductor materials, a thin film of a material whose valence electrons are controlled can be deposited.

【0019】図1に示されているような絶縁性基板3上
の導電性薄膜5を覆うように第2の薄膜の堆積がプラズ
マCVDで行なわれるわけであるが、透光性の導電性酸
化物のように比較的導電率が小さな導電体膜5を分離溝
7によって分離して、それらの分離された複数の島状導
電体薄膜領域を覆うように第2の薄膜をプラズマCVD
で堆積する場合に、膜堆積面内における接地電位に対す
る抵抗値の局所的変動および平均の抵抗値がかなり低減
され得る。
The second thin film is deposited by plasma CVD so as to cover the conductive thin film 5 on the insulating substrate 3 as shown in FIG. The conductive film 5 having a relatively small conductivity such as an object is separated by the separation groove 7, and the second thin film is formed by plasma CVD so as to cover the separated plurality of island-shaped conductive thin film regions.
, Local variations in resistance to ground potential and average resistance in the film deposition plane can be significantly reduced.

【0020】接地電位と同電位である基板装着用治具と
基板3との接続は、基板3の周囲部の四辺における接触
によって行なわれるが、図4の場合に比較すれば、長方
形基板3の長手方向の中央部における電極分離溝中断領
域7xを通じて電流の経路が存在するので、膜堆積面の
全体にわたって抵抗値の局所的な変動と平均抵抗値がか
なり低減され得る。その結果、第1電極層5を覆うよう
に第2の薄膜をプラズマCVDで堆積する場合に、横堆
積面と高周波電極面との間における局所的な電位変動が
かなり低減され得て、それに伴って、発生する膜堆積前
駆体の密度の局所的変動をも抑制することができ、第2
の薄膜の局所的な膜厚変動を低減させることが可能にな
る。
The connection between the substrate mounting jig having the same potential as the ground potential and the substrate 3 is made by contacting the four sides of the peripheral portion of the substrate 3, but as compared with the case of FIG. Since a current path exists through the electrode separation groove interruption region 7x in the central portion in the longitudinal direction, the local fluctuation of the resistance value and the average resistance value over the entire film deposition surface can be considerably reduced. As a result, when depositing the second thin film by plasma CVD so as to cover the first electrode layer 5, local potential fluctuation between the horizontal deposition surface and the high-frequency electrode surface can be considerably reduced, and accordingly, As a result, local fluctuations in the density of the generated film deposition precursor can be suppressed, and the second
Local variation in film thickness of the thin film can be reduced.

【0021】[0021]

【実施例】図1を参照して説明された本発明の実施の形
態に対応して、絶縁性基板上に形成された導電性の複数
の第1薄膜領域を覆うようにプラズマCVDによって第
2の薄膜が実施例として堆積させられた。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In accordance with the embodiment of the present invention described with reference to FIG. 1, a second CVD method is used to cover a plurality of first thin film regions formed on an insulating substrate. Was deposited as an example.

【0022】まず、910mm×455mmの長方形と
4mmの厚さを有するガラス基板3上に、第1電極層5
として透明酸化物導電薄膜が熱CVDによって形成され
た。この透明電極層5は、0.53μmの波長を有する
YAGレーザの第2高調波を膜面側から照射して複数の
分離溝7を形成することによって、複数の短冊状の透明
電極領域に分離された。その後、基板3と透明電極層5
が純水中で洗浄され、この透明電極層5上には第2薄膜
層がプラズマCVDによって堆積された。
First, a first electrode layer 5 is formed on a glass substrate 3 having a rectangular shape of 910 mm × 455 mm and a thickness of 4 mm.
A transparent oxide conductive thin film was formed by thermal CVD. The transparent electrode layer 5 is separated into a plurality of strip-shaped transparent electrode regions by irradiating the second harmonic of a YAG laser having a wavelength of 0.53 μm from the film surface side to form a plurality of separation grooves 7. Was done. Then, the substrate 3 and the transparent electrode layer 5
Was washed in pure water, and a second thin film layer was deposited on the transparent electrode layer 5 by plasma CVD.

【0023】この実施例による透明電極層5では、長さ
88cmで幅50μmの分離溝7が、0.9cmのピッ
チで51本形成され、それらの分離溝7の中央部に適当
な長さの溝中断領域7xが設けられた。
In the transparent electrode layer 5 according to this embodiment, 51 separation grooves 7 having a length of 88 cm and a width of 50 μm are formed at a pitch of 0.9 cm, and an appropriate length is formed at the center of the separation grooves 7. A groove interruption region 7x was provided.

【0024】以上のような電極分離溝7中の溝中断領域
7xの長さを0.5mmから12mmまで変化させて、
接地電極と透明電極層5の表面との間の抵抗値の変化の
様子が調べられた。表1は、作製された5枚の基板につ
いて、図1に示されているように基板3において一点鎖
線で表わされた長手方向の中心線に沿った位置a〜eに
依存する抵抗値のばらつきを示している。
By changing the length of the groove interruption region 7x in the electrode separation groove 7 from 0.5 mm to 12 mm as described above,
The state of the change in the resistance value between the ground electrode and the surface of the transparent electrode layer 5 was examined. Table 1 shows that the resistance values depending on the positions a to e along the longitudinal center line represented by the dashed line on the substrate 3 as shown in FIG. The variation is shown.

【0025】[0025]

【表1】 [Table 1]

【0026】なお、この透明電極層5の面積抵抗値は、
約10〜12Ω/□であった。表1においては、参考の
ために、電極分離溝7が形成される前における透明電極
層5上の各点a〜eと接地電極との間の抵抗値も示され
ており、この平均値は18Ωであるが、図4に示されて
いる従来例と同様に分離溝7が形成された状態(7x=
0mm)では、抵抗の平均値が168Ωのように大幅に
増大している。他方、分離溝7の中断長さ7xを0.5
mmにした状態では、抵抗の平均値が101Ωとなり、
従来の方法に比較すれば4割程度低減されている。ま
た、7x=2mmでは平均抵抗値が93Ωであり、7x
=12mmでは平均抵抗が87Ωになっており、溝中断
長さ7xが大きいほど平均抵抗値が小さくなっている。
さらに、その平均抵抗値の低下に伴って、各抵抗値のば
らつきも小さくなっている。
The area resistance of the transparent electrode layer 5 is as follows:
It was about 10 to 12 Ω / □. Table 1 also shows, for reference, resistance values between the points a to e on the transparent electrode layer 5 and the ground electrode before the electrode separation groove 7 is formed. 18Ω, but in a state where the separation groove 7 is formed as in the conventional example shown in FIG. 4 (7x =
0 mm), the average value of the resistance is greatly increased to 168Ω. On the other hand, the interruption length 7x of the separation groove 7 is set to 0.5
mm, the average resistance is 101Ω,
It is reduced by about 40% as compared with the conventional method. Also, when 7x = 2 mm, the average resistance value is 93Ω, and 7x
= 12 mm, the average resistance is 87Ω, and the greater the groove interruption length 7x, the smaller the average resistance value.
Further, as the average resistance value decreases, the variation in each resistance value also decreases.

【0027】なお、図1に示されているような基板上に
集積型薄膜太陽電池モジュールが形成された場合には、
たとえば、溝中断領域7xを除去するように基板3ごと
そのモジュールを切断すればよい。
When an integrated thin-film solar cell module is formed on a substrate as shown in FIG.
For example, the module may be cut together with the substrate 3 so as to remove the groove interruption region 7x.

【0028】[0028]

【発明の効果】以上のように、本発明の薄膜堆積方法に
よれば、絶縁性基板上に形成された透明導電性酸化物の
ような比較的導電率が小さな第1の薄膜を分離溝によっ
て分離して、それらの分離された複数の島状導電領域を
覆うように第2の薄膜をプラズマCVDにて堆積する場
合に、膜堆積面内における接地電位に対する抵抗値の局
所的な変動や平均値をかなり低減させることができるの
で、プラズマCVDにおける放電状態が不安定な場合や
放電電力が弱いときでも、均一な膜厚分布を有する第2
の薄膜の堆積が行なわれ得る。特に、大面積の基板上に
堆積される薄膜の局所的な膜厚変動を大幅に低減させる
ことができるとともに、薄膜の生産歩留りを大幅に向上
させることができる。
As described above, according to the thin film deposition method of the present invention, the first thin film having relatively small conductivity such as the transparent conductive oxide formed on the insulating substrate is separated by the separation groove. When separating and depositing the second thin film by plasma CVD so as to cover the plurality of isolated island-shaped conductive regions, a local variation or an average of a resistance value with respect to a ground potential in a film deposition surface is obtained. Since the value can be considerably reduced, even when the discharge state in plasma CVD is unstable or the discharge power is weak, the second layer having a uniform film thickness distribution can be obtained.
Can be deposited. In particular, local variation in thickness of a thin film deposited on a large-area substrate can be significantly reduced, and the production yield of the thin film can be significantly improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態の一例による絶縁性基板上
に形成された導電層と複数の分離溝を示す模式的な上面
図である。
FIG. 1 is a schematic top view showing a conductive layer and a plurality of separation grooves formed on an insulating substrate according to an example of an embodiment of the present invention.

【図2】集積型薄膜太陽電池モジュールの一部を図解す
る模式的な断面図である。
FIG. 2 is a schematic cross-sectional view illustrating a part of the integrated thin-film solar cell module.

【図3】従来の方法によって絶縁性基板上に形成された
導電層と複数の分離溝を示す模式的な断面図である。
FIG. 3 is a schematic cross-sectional view showing a conductive layer and a plurality of separation grooves formed on an insulating substrate by a conventional method.

【図4】図3に対応する状態を示す概略的な上面図であ
る。
FIG. 4 is a schematic top view showing a state corresponding to FIG. 3;

【符号の説明】[Explanation of symbols]

3 ガラス等の基板 5 第1電極層 7 第1電極分離溝 8 接続用溝 9 第2電極分離溝 11 半導体光電変換層 15 第2電極層 17 光電変換セル 20 集積型薄膜太陽電池モジュール Reference Signs List 3 Substrate such as glass 5 First electrode layer 7 First electrode separation groove 8 Connection groove 9 Second electrode separation groove 11 Semiconductor photoelectric conversion layer 15 Second electrode layer 17 Photoelectric conversion cell 20 Integrated thin-film solar cell module

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板の1主面全体を覆うように導
電性の第1の薄膜を形成し、前記第1薄膜を複数の領域
に分離するように実質的に直線状で互いに平行な複数の
分離溝を形成し、そして前記第1薄膜を覆うようにプラ
ズマCVDによって第2の薄膜を堆積させる方法におい
て、前記分離溝の各々が所定長さの溝中断領域の少なく
とも1つを含んでいることを特徴とするプラズマCVD
による薄膜堆積方法。
1. A first conductive thin film is formed so as to cover one entire main surface of an insulating substrate, and is substantially linear and parallel to each other so as to divide the first thin film into a plurality of regions. A method of forming a plurality of isolation trenches and depositing a second thin film by plasma CVD over the first thin film, wherein each of the isolation trenches includes at least one groove interrupted region of a predetermined length. Plasma CVD
Thin film deposition method.
【請求項2】 前記第1薄膜は透光性の導電性酸化物を
含むことを特徴とする請求項1に記載のプラズマCVD
による薄膜堆積方法。
2. The plasma CVD method according to claim 1, wherein the first thin film contains a light-transmitting conductive oxide.
Thin film deposition method.
【請求項3】 前記第2薄膜は水素化非晶質シリコンま
たはその合金を含むことを特徴とする請求項1または2
に記載のプラズマCVDによる薄膜堆積方法。
3. The method according to claim 1, wherein the second thin film contains hydrogenated amorphous silicon or an alloy thereof.
3. The method for depositing a thin film by plasma CVD according to 1.
【請求項4】 前記第2薄膜は多結晶シリコンを含むこ
とを特徴とする請求項1または2に記載のプラズマCV
Dによる薄膜堆積方法。
4. The plasma CV according to claim 1, wherein the second thin film contains polycrystalline silicon.
D. Thin film deposition method.
JP09128598A 1998-04-03 1998-04-03 Thin film deposition method by plasma CVD Expired - Fee Related JP3540149B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09128598A JP3540149B2 (en) 1998-04-03 1998-04-03 Thin film deposition method by plasma CVD

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Application Number Priority Date Filing Date Title
JP09128598A JP3540149B2 (en) 1998-04-03 1998-04-03 Thin film deposition method by plasma CVD

Publications (2)

Publication Number Publication Date
JPH11288889A true JPH11288889A (en) 1999-10-19
JP3540149B2 JP3540149B2 (en) 2004-07-07

Family

ID=14022202

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Country Status (1)

Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335692A (en) * 2006-06-16 2007-12-27 Seiko Instruments Inc Semiconductor device
JP2011035270A (en) * 2009-08-04 2011-02-17 Sharp Corp Photoelectric converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335692A (en) * 2006-06-16 2007-12-27 Seiko Instruments Inc Semiconductor device
JP2011035270A (en) * 2009-08-04 2011-02-17 Sharp Corp Photoelectric converter

Also Published As

Publication number Publication date
JP3540149B2 (en) 2004-07-07

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