JPH11288373A5 - - Google Patents

Info

Publication number
JPH11288373A5
JPH11288373A5 JP1999015811A JP1581199A JPH11288373A5 JP H11288373 A5 JPH11288373 A5 JP H11288373A5 JP 1999015811 A JP1999015811 A JP 1999015811A JP 1581199 A JP1581199 A JP 1581199A JP H11288373 A5 JPH11288373 A5 JP H11288373A5
Authority
JP
Japan
Prior art keywords
register
instruction
execution
thread
selecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1999015811A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11288373A (ja
JP3871458B2 (ja
Filing date
Publication date
Priority claimed from US09/016,692 external-priority patent/US6308261B1/en
Application filed filed Critical
Publication of JPH11288373A publication Critical patent/JPH11288373A/ja
Publication of JPH11288373A5 publication Critical patent/JPH11288373A5/ja
Application granted granted Critical
Publication of JP3871458B2 publication Critical patent/JP3871458B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP01581199A 1998-01-30 1999-01-25 コンピュータ・システム Expired - Fee Related JP3871458B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US016,692 1998-01-30
US09/016,692 US6308261B1 (en) 1998-01-30 1998-01-30 Computer system having an instruction for probing memory latency

Publications (3)

Publication Number Publication Date
JPH11288373A JPH11288373A (ja) 1999-10-19
JPH11288373A5 true JPH11288373A5 (enExample) 2006-03-23
JP3871458B2 JP3871458B2 (ja) 2007-01-24

Family

ID=21778434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP01581199A Expired - Fee Related JP3871458B2 (ja) 1998-01-30 1999-01-25 コンピュータ・システム

Country Status (4)

Country Link
US (1) US6308261B1 (enExample)
EP (1) EP0933698B1 (enExample)
JP (1) JP3871458B2 (enExample)
DE (1) DE69931288T2 (enExample)

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US7257814B1 (en) 1998-12-16 2007-08-14 Mips Technologies, Inc. Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
US7237093B1 (en) * 1998-12-16 2007-06-26 Mips Technologies, Inc. Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams
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US6965914B2 (en) * 2000-10-27 2005-11-15 Eric Morgan Dowling Negotiated wireless peripheral systems
US6973561B1 (en) * 2000-12-04 2005-12-06 Lsi Logic Corporation Processor pipeline stall based on data register status
US20030101336A1 (en) * 2001-11-28 2003-05-29 Sun Microsystems, Inc. Technique for associating instructions with execution events
US7137111B2 (en) * 2001-11-28 2006-11-14 Sun Microsystems, Inc. Aggressive prefetch of address chains
US7134139B2 (en) * 2002-02-12 2006-11-07 International Business Machines Corporation System and method for authenticating block level cache access on network
US7100157B2 (en) * 2002-09-24 2006-08-29 Intel Corporation Methods and apparatus to avoid dynamic micro-architectural penalties in an in-order processor
US7454747B2 (en) * 2003-02-07 2008-11-18 Sun Microsystems, Inc. Determining maximum acceptable scheduling load latency using hierarchical search
US20040226011A1 (en) * 2003-05-08 2004-11-11 International Business Machines Corporation Multi-threaded microprocessor with queue flushing
US7360064B1 (en) 2003-12-10 2008-04-15 Cisco Technology, Inc. Thread interleaving in a multithreaded embedded processor
US7441101B1 (en) 2003-12-10 2008-10-21 Cisco Technology, Inc. Thread-aware instruction fetching in a multithreaded embedded processor
US7206922B1 (en) 2003-12-30 2007-04-17 Cisco Systems, Inc. Instruction memory hierarchy for an embedded processor
US7827543B1 (en) 2004-02-28 2010-11-02 Oracle America, Inc. Method and apparatus for profiling data addresses
US8065665B1 (en) 2004-02-28 2011-11-22 Oracle America, Inc. Method and apparatus for correlating profile data
US7735073B1 (en) 2004-02-28 2010-06-08 Oracle International Corporation Method and apparatus for data object profiling
US7711928B2 (en) 2004-03-31 2010-05-04 Oracle America, Inc. Method and structure for explicit software control using scoreboard status information
US7707554B1 (en) 2004-04-21 2010-04-27 Oracle America, Inc. Associating data source information with runtime events
US7516306B2 (en) * 2004-10-05 2009-04-07 International Business Machines Corporation Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies
JP4783005B2 (ja) * 2004-11-25 2011-09-28 パナソニック株式会社 プログラム変換装置、プログラム変換実行装置およびプログラム変換方法、プログラム変換実行方法。
US7552318B2 (en) * 2004-12-17 2009-06-23 International Business Machines Corporation Branch lookahead prefetch for microprocessors
US7266674B2 (en) 2005-02-24 2007-09-04 Microsoft Corporation Programmable delayed dispatch in a multi-threaded pipeline
US20070260856A1 (en) * 2006-05-05 2007-11-08 Tran Thang M Methods and apparatus to detect data dependencies in an instruction pipeline
US8122439B2 (en) * 2007-08-09 2012-02-21 International Business Machines Corporation Method and computer program product for dynamically and precisely discovering deliquent memory operations
US7711936B2 (en) * 2007-08-28 2010-05-04 Sun Microsystems, Inc. Branch predictor for branches with asymmetric penalties
US10140210B2 (en) 2013-09-24 2018-11-27 Intel Corporation Method and apparatus for cache occupancy determination and instruction scheduling
US10896130B2 (en) * 2016-10-19 2021-01-19 International Business Machines Corporation Response times in asynchronous I/O-based software using thread pairing and co-execution
JP7013707B2 (ja) * 2017-08-02 2022-02-01 富士通株式会社 情報処理装置および情報処理方法
US11467966B2 (en) * 2020-09-02 2022-10-11 Shenzhen GOODIX Technology Co., Ltd. Cache memory having a programmable number of ways

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US6016542A (en) * 1997-12-31 2000-01-18 Intel Corporation Detecting long latency pipeline stalls for thread switching

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