JP3871458B2 - コンピュータ・システム - Google Patents

コンピュータ・システム Download PDF

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Publication number
JP3871458B2
JP3871458B2 JP01581199A JP1581199A JP3871458B2 JP 3871458 B2 JP3871458 B2 JP 3871458B2 JP 01581199 A JP01581199 A JP 01581199A JP 1581199 A JP1581199 A JP 1581199A JP 3871458 B2 JP3871458 B2 JP 3871458B2
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JP
Japan
Prior art keywords
register
instruction
execution
contents
computer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP01581199A
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English (en)
Japanese (ja)
Other versions
JPH11288373A (ja
JPH11288373A5 (enExample
Inventor
デール・シー・モリス
ダグラス・ビー・ハント
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HP Inc
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Hewlett Packard Co
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Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH11288373A publication Critical patent/JPH11288373A/ja
Publication of JPH11288373A5 publication Critical patent/JPH11288373A5/ja
Application granted granted Critical
Publication of JP3871458B2 publication Critical patent/JP3871458B2/ja
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
JP01581199A 1998-01-30 1999-01-25 コンピュータ・システム Expired - Fee Related JP3871458B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US016,692 1998-01-30
US09/016,692 US6308261B1 (en) 1998-01-30 1998-01-30 Computer system having an instruction for probing memory latency

Publications (3)

Publication Number Publication Date
JPH11288373A JPH11288373A (ja) 1999-10-19
JPH11288373A5 JPH11288373A5 (enExample) 2006-03-23
JP3871458B2 true JP3871458B2 (ja) 2007-01-24

Family

ID=21778434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP01581199A Expired - Fee Related JP3871458B2 (ja) 1998-01-30 1999-01-25 コンピュータ・システム

Country Status (4)

Country Link
US (1) US6308261B1 (enExample)
EP (1) EP0933698B1 (enExample)
JP (1) JP3871458B2 (enExample)
DE (1) DE69931288T2 (enExample)

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* Cited by examiner, † Cited by third party
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US7020879B1 (en) 1998-12-16 2006-03-28 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
US7529907B2 (en) 1998-12-16 2009-05-05 Mips Technologies, Inc. Method and apparatus for improved computer load and store operations
US7035997B1 (en) 1998-12-16 2006-04-25 Mips Technologies, Inc. Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
US6389449B1 (en) 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors
US7257814B1 (en) 1998-12-16 2007-08-14 Mips Technologies, Inc. Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
US7237093B1 (en) * 1998-12-16 2007-06-26 Mips Technologies, Inc. Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams
DE60143896D1 (de) 2000-07-14 2011-03-03 Mips Tech Inc Anweisungsabruf und -absendung in einem multi-thread-system
US6965914B2 (en) * 2000-10-27 2005-11-15 Eric Morgan Dowling Negotiated wireless peripheral systems
US6973561B1 (en) * 2000-12-04 2005-12-06 Lsi Logic Corporation Processor pipeline stall based on data register status
US20030101336A1 (en) * 2001-11-28 2003-05-29 Sun Microsystems, Inc. Technique for associating instructions with execution events
US7137111B2 (en) * 2001-11-28 2006-11-14 Sun Microsystems, Inc. Aggressive prefetch of address chains
US7134139B2 (en) * 2002-02-12 2006-11-07 International Business Machines Corporation System and method for authenticating block level cache access on network
US7100157B2 (en) * 2002-09-24 2006-08-29 Intel Corporation Methods and apparatus to avoid dynamic micro-architectural penalties in an in-order processor
US7454747B2 (en) * 2003-02-07 2008-11-18 Sun Microsystems, Inc. Determining maximum acceptable scheduling load latency using hierarchical search
US20040226011A1 (en) * 2003-05-08 2004-11-11 International Business Machines Corporation Multi-threaded microprocessor with queue flushing
US7360064B1 (en) 2003-12-10 2008-04-15 Cisco Technology, Inc. Thread interleaving in a multithreaded embedded processor
US7441101B1 (en) 2003-12-10 2008-10-21 Cisco Technology, Inc. Thread-aware instruction fetching in a multithreaded embedded processor
US7206922B1 (en) 2003-12-30 2007-04-17 Cisco Systems, Inc. Instruction memory hierarchy for an embedded processor
US7827543B1 (en) 2004-02-28 2010-11-02 Oracle America, Inc. Method and apparatus for profiling data addresses
US8065665B1 (en) 2004-02-28 2011-11-22 Oracle America, Inc. Method and apparatus for correlating profile data
US7735073B1 (en) 2004-02-28 2010-06-08 Oracle International Corporation Method and apparatus for data object profiling
US7711928B2 (en) 2004-03-31 2010-05-04 Oracle America, Inc. Method and structure for explicit software control using scoreboard status information
US7707554B1 (en) 2004-04-21 2010-04-27 Oracle America, Inc. Associating data source information with runtime events
US7516306B2 (en) * 2004-10-05 2009-04-07 International Business Machines Corporation Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies
JP4783005B2 (ja) * 2004-11-25 2011-09-28 パナソニック株式会社 プログラム変換装置、プログラム変換実行装置およびプログラム変換方法、プログラム変換実行方法。
US7552318B2 (en) * 2004-12-17 2009-06-23 International Business Machines Corporation Branch lookahead prefetch for microprocessors
US7266674B2 (en) 2005-02-24 2007-09-04 Microsoft Corporation Programmable delayed dispatch in a multi-threaded pipeline
US20070260856A1 (en) * 2006-05-05 2007-11-08 Tran Thang M Methods and apparatus to detect data dependencies in an instruction pipeline
US8122439B2 (en) * 2007-08-09 2012-02-21 International Business Machines Corporation Method and computer program product for dynamically and precisely discovering deliquent memory operations
US7711936B2 (en) * 2007-08-28 2010-05-04 Sun Microsystems, Inc. Branch predictor for branches with asymmetric penalties
US10140210B2 (en) 2013-09-24 2018-11-27 Intel Corporation Method and apparatus for cache occupancy determination and instruction scheduling
US10896130B2 (en) * 2016-10-19 2021-01-19 International Business Machines Corporation Response times in asynchronous I/O-based software using thread pairing and co-execution
JP7013707B2 (ja) * 2017-08-02 2022-02-01 富士通株式会社 情報処理装置および情報処理方法
US11467966B2 (en) * 2020-09-02 2022-10-11 Shenzhen GOODIX Technology Co., Ltd. Cache memory having a programmable number of ways

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5142631A (en) * 1989-02-03 1992-08-25 Digital Equipment Corporation System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register
GB2234613B (en) * 1989-08-03 1993-07-07 Sun Microsystems Inc Method and apparatus for switching context of state elements in a microprocessor
US5251306A (en) 1990-01-16 1993-10-05 Advanced Micro Devices, Inc. Apparatus for controlling execution of a program in a computing device
US5493687A (en) * 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5530825A (en) * 1994-04-15 1996-06-25 Motorola, Inc. Data processor with branch target address cache and method of operation
JPH096633A (ja) 1995-06-07 1997-01-10 Internatl Business Mach Corp <Ibm> データ処理システムに於ける高性能多重論理経路の動作用の方法とシステム
US5933627A (en) * 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
JP2970553B2 (ja) * 1996-08-30 1999-11-02 日本電気株式会社 マルチスレッド実行方法
US5802386A (en) * 1996-11-19 1998-09-01 International Business Machines Corporation Latency-based scheduling of instructions in a superscalar processor
US5887166A (en) * 1996-12-16 1999-03-23 International Business Machines Corporation Method and system for constructing a program including a navigation instruction
US5905889A (en) * 1997-03-20 1999-05-18 International Business Machines Corporation Resource management system using next available integer from an integer pool and returning the integer thereto as the next available integer upon completion of use
US6016542A (en) * 1997-12-31 2000-01-18 Intel Corporation Detecting long latency pipeline stalls for thread switching

Also Published As

Publication number Publication date
JPH11288373A (ja) 1999-10-19
DE69931288T2 (de) 2006-12-07
US6308261B1 (en) 2001-10-23
EP0933698A3 (en) 2000-12-06
EP0933698A2 (en) 1999-08-04
DE69931288D1 (de) 2006-06-22
EP0933698B1 (en) 2006-05-17

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