JPH11287807A - System for collecting analysis data with utilizing bank memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To collect data without handshaking between an analysis data collection CPU and a host system. SOLUTION: This system includes an analysis data collection means 2 for collecting analysis data from an analyzing apparatus 1 and writing to either of memory banks 6, 7, a host process means 3 for reading the analysis data written in either of the memory banks and carrying out an analysis process, a bank switch means 5 for switching connection of a data bus and an address bus on the basis of a bank switch signal, and an address hold coincidence detection means 4 for holding a final address of the memory bank where the analysis data is written and detecting coincidence of the final address with a final address at the address bus of the host process means, thereby outputting a coincidence signal. The bank switch signal is sent to the bank switch means 5 in accordance with the coincidence signal of the address hold coincidence detection means 4, thereby switching connection of the memory bank.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analysis data collection system using a bank memory system for collecting analysis data from an analyzer using a plurality of memory banks.

[0002]

2. Description of the Related Art FIG. 3 is a diagram for explaining a conventional example of an analysis data collection system using a bank memory system. In many cases, computer systems adopt a bank memory system in which two or more memories (memory banks) are allocated to one memory space and switched and used as needed. When the bank memory system is adopted, for example, in order for the host system to read external information, a CPU for collecting external data and a circuit for performing a handshake between them are required. For example, when the analysis conditions are set as shown in FIG. 3 and the analysis data is repeatedly collected by the analysis data collection CPU 2 from the analyzer 1 and the analysis processing of the analysis data is executed by the host system 3, the analysis data collection C
When the analysis data collected by the PU 2 is written into one memory bank 6 or 7, an interrupt is generated to the host system 3 via the switching handshake circuit 21 to notify that the bank switching is enabled. When the host system 3 receives this interrupt, the bank switching circuit 5
Issue a switching instruction for memory banks 6 and 7 to switch the memory banks. This switching enables the analysis data collection CPU 2 to read the analysis data written in the memory bank from the host system 3.

[0003]

However, in the conventional system, as described above, the host system 3 accepts an interrupt from the analysis data collection CPU 2 via the switching handshake circuit 21 and issues a bank switching instruction. Therefore, the host system 3 must handle them, and the host system 3 not only analyzes and processes the analysis data but also increases the burden of handling. Therefore, when the host system simply cannot access the memory area to which the memory bank is assigned, reads data and performs predetermined work, and cannot handle bank switching, the host system is adapted to the above system. A problem arises that it is not possible.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to enable data collection between an analysis data collection CPU and a host system without handshaking.

Accordingly, the present invention provides an analysis data collection system using a bank memory system for collecting analysis data from an analyzer using a plurality of memory banks. Analysis data collection means for writing to one of the memory banks, host processing means for reading analysis data written to one of the memory banks and executing analysis processing, and a data bus for the analysis data collection means and the host processing means. Bank switching means for alternately switching the connection between the address bus and the data bus and address bus of the plurality of memory banks based on a bank switching signal; and holding the final address of the memory bank to which the analysis data has been written by the analysis data collection means. And reads the analysis data from the memory bank. Address holding match detecting means for detecting a match with the last address on the address bus of the processing means and outputting a match signal, and outputting a bank switching signal to the bank switching means based on the matching signal of the address holding matching detecting means. It is characterized in that it is configured to be transmitted.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of an analysis data collection system using a bank memory system according to the present invention, wherein 1 is an analyzer, and 2 is an analysis data collection CP.
U, 3 is a host system, 4 is an address holding matching circuit,
5 is a bank switching circuit, 6 and 7 are memory banks, 8 to 11
Indicates a data bus, and 12 to 15 indicate address buses.

In FIG. 1, an analyzer 1 analyzes a sample under predetermined analysis conditions, such as an electron beam analyzer, a mass analyzer, an NMR (nuclear magnetic resonance) apparatus, and the like. The analysis data collection CPU 2 includes the analysis device 1
Is collected at predetermined intervals, for example, according to analysis conditions, and the collected analysis data is written to one of the memory banks 6 and 7. When a match signal is received from the address holding / matching circuit 4, the address holding / matching circuit 4 holds the final addresses of the memory banks 6, 7 into which the analysis data has been written, and
A bank switching signal is sent to the bank switching circuit 5. When switching to the other memory bank 6, 7 is newly performed by the switching signal, analysis data of the next cycle can be collected and written to the other memory bank 6, 7.

The host system 3 has an analysis data collection CP
When the data is collected by the U2 and written into the memory banks 6 and 7, the analysis data is read and noise removal is performed by integration processing, and qualitative analysis, quantitative analysis, and other analysis processing (analysis processing) are performed. The address holding coincidence circuit 4 is controlled by the analysis data collection CPU 2 to
7 holds the final address of the analysis data written in the memory bank 7, detects the final address of the analysis data read by the host system 3 from the memory banks 6 and 7, and when the final addresses match, a match signal is collected. This is sent to the CPU 2. The bank switching circuit 5
Receiving the bank switching signal from the analysis data collection CPU 2, the data buses 10, 11, address buses 14, 15 of the memory banks 6, 7 and the data bus 8, address bus 12, of the analysis data collection CPU 2, and the data bus of the host system 3 9, for switching the bus connection with the address bus 13;

Next, the process of collecting analysis data of a sample from the analyzer by the analysis data collection CPU will be described. FIG. 2 is a diagram for explaining the flow of processing by the analysis data collection CPU. First, the data bus 10 and the address bus 14 of the memory bank 6 are connected to, for example, the data bus 8 and the address bus 12 of the analysis data collection CPU 2 by the bank switching circuit 5, and analysis conditions are set (step S1).
1) When the analysis of the sample by the analyzer 1 is started (step S12), the analysis data collection CPU 2 writes the collected analysis data into the memory bank 6 (step S1).
3). When the analysis data collection CPU 2 collects the analysis data corresponding to the analysis once or according to the divided analysis of one unit according to the setting of the analysis condition and writes it in the memory bank 6, it is determined whether the data collection is completed (step S14). ), And there is further collection of analysis data (N in step S14).
O) In the case, it is determined whether or not there is a match signal of the address holding match circuit 4 (step S15). Then, it waits for the coincidence signal to be output, that is, waits for the host system 3 to finish reading the analysis data, and sends a switching signal to the bank switching circuit 5 (step S16). By sending the switching signal, the bank switching circuit 5 switches the bus of the memory bank 6 to the bus of the host system 3 and switches the bus of the memory bank 7 to the bus of the analysis data collection CPU 2. The final address of the memory bank 6 into which the analysis data has been written is held in the address holding matching circuit 4 (step S
17) Return to step S13 again, and repeatedly write the analysis data to the memory bank until the collection of the analysis data ends.

While the analysis data collection CPU 2 writes the next analysis data collected in the memory bank 7, the host system 3 reads out the analysis data previously written in the memory bank 6 by the analysis data collection CPU 2 and executes the analysis processing. . When the host system 3 reads the analysis data from the memory bank 6 to the last address held in the address holding / matching circuit 4, the address holding / matching circuit 4 sends a match signal to the analysis data collection CPU 2. Therefore, the host system 3 does not need to be aware of the final address and the memory bank to be read.

As described above, the analysis data collection CPU 2
When the analysis data has been collected and written into the memory bank, the host system 3 confirms that the analysis data has been read out by the coincidence signal from the address holding coincidence circuit 4 and sends a switching signal to the bank switching circuit 5. At the same time, the final address of the memory bank into which the analysis data has been written may be held in the address holding matching circuit 4, and the next analysis data may be collected at a predetermined timing. On the other hand, the host system 3 only needs to read the analysis data from the memory bank at a predetermined timing without being aware of the memory bank, and execute the predetermined analysis and analysis processing. Normally, the completion of the reading of the analysis data by the host system 3 is slower than the collection and writing of the analysis data by the analysis data collection CPU 2, but may be earlier.

In the host system 3, for example, if a flag is set in the memory bank from which reading has been completed, it can be recognized as a memory bank which has already been read as long as the flag remains, and the condition is that the memory bank is no longer a flag for reading. Then, it is recognized that the memory bank has been switched, and reading of the next analysis data can be started. Further, by receiving a signal for starting the collection of the next analysis data from the analysis data collection CPU 2, it can be used as a trigger to recognize that the memory bank has been switched, and to start reading the next analysis data. Conversely, if the memory bank is not the read end flag, and if the next analysis data collection start signal is not received from the analysis data collection CPU 2, it can wait for the next analysis data to be read from the memory bank.

The analysis data collection CPU 2 analyzes the sample according to the set analysis conditions, writes the analysis data collected from the analyzer into one memory bank, and reads the host system from the match signal of the address holding match circuit 4. 3 recognizes whether reading of the analysis data previously collected and written in the other memory bank has been completed, and if the host system 3 has finished reading the analysis data from the other memory bank, the bank switching is performed. A switching signal is sent to the circuit 5, and the final address can be held in the address holding matching circuit 4. As a result, the bank is switched, so that it is possible to shift to the collection of the next analysis data. If the analysis data collection CPU 2 writes the analysis data into one of the memory banks and there is no match signal from the address holding matching circuit 4 yet, it sends a switching signal to the bank switching circuit 5 to send the address holding matching circuit. 4 to hold the new final address.

On the other hand, the address holding matching circuit 4
Then, the address bus 13 of the host system 3 is constantly monitored, the address is compared with the final address held by the analysis data collection CPU 2, and a match signal is sent to the analysis data collection CPU 2 only when a match is detected. I just need. When the switching signal is received from the analysis data collection CPU 2, the bank switching circuit 5 connects the bus of the analysis data collection CPU 2 to the bus of the memory banks 6 and 7, and the connection between the host system 3 and the bus of the memory banks 6 and 7. You just need to switch.

The host system 1 reads the contents of the memory banks 6 and 7 at irregular intervals.
If data is read continuously from the beginning to the end of the memory area of the memory banks 6 and 7, DMA can be used, so that the load on the host system 1 can be reduced. Moreover, the host system 1 does not need to be aware of which of the memory banks 5, 6 is being read.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above-described embodiment, the analysis data collection CPU is provided to the bank switching circuit based on the coincidence signal of the address holding coincidence circuit.
Transmitted the bank switching signal, but the host system may transmit the bank switching signal based on the matching signal of the address holding matching circuit so that the analysis data collection CPU does not make the analysis data collection CPU aware of the memory bank.

[0017]

As is apparent from the above description, according to the present invention, the analysis data collecting CPU which collects the analysis data and writes the analysis data into the memory bank holds the final address in the address holding matching circuit. When the analysis data is read by the host system, when the last read address of the host system matches the last address held in the address holding matching circuit, the analysis data collection CPU and the bus of the host system and the bus of the bank are connected based on the match signal. Since the connection is switched, analysis data collection C
Bank switching can be performed between the PU and the host system without handshaking.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of an analysis data collection system using a bank memory system according to the present invention.

FIG. 2 is a diagram for explaining a flow of processing by an analysis data collection CPU;

FIG. 3 is a diagram for explaining a conventional example of an analysis data collection method using a bank memory method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Analyzer, 2 ... Analysis data collection CPU, 3 ... Host system, 4 ... Address holding matching circuit, 5 ... Bank switching circuit, 6, 7 ... Memory banks, 8-11 ... Data bus,
12-15: Address bus

Claims (1)

[Claims] 1. An analysis data collection system using a bank memory system for collecting analysis data from an analyzer using a plurality of memory banks, wherein the analysis data is collected from the analyzer and any one of the memory banks is collected. An analysis data collection unit that writes data to one of the memory banks, a host processing unit that reads analysis data written to one of the memory banks and executes an analysis process, and a data bus and an address bus of the analysis data collection unit and the host processing unit. Bank switching means for alternately switching connections of a plurality of memory banks to a data bus and an address bus based on a bank switching signal; holding the final address of a memory bank to which analysis data has been written by the analysis data collection means; Address of the host processing means for reading analysis data from a bank Address holding / match detecting means for detecting a match with the last address on the bus and outputting a match signal, and transmitting a bank switching signal to the bank switching means based on the matching signal of the address holding / match detecting means. An analysis data collection system using a bank memory system, wherein the analysis data collection system is configured.