JPH09198339A - Bus adapter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten time required for data transfer between an input/output controller executing burst transfer and a main storage device. SOLUTION: While a central processing unit 1 writes input/output control information into the input/output controller 6, a bus adapter device 16 analyzes input/output control information. When the content is data transfer from the main storage device 2 to the input/output controller 6, data transfer request is outputted to the main storage device 2. The bus adapter device 16 receives data transfer from the main storage device 2 and stores it in a data buffer 9. When the input/output controller 6 receives the writing of input/output control information, it outputs the data transfer request to the but adapter device 16. The but adapter device 16 receiving the data transfer request transfers data stored at the time of transferring data to the data buffer 9 to the input/output controller 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus adapter device connected to a data transfer bus in an electronic computer system or the like.

[0002]

2. Description of the Related Art In an electronic computer system or the like, when connecting buses having different byte widths of data that can be transferred at one time or buses having different data transfer rates, data for temporarily storing transfer data It is known to connect a bus adapter device with a buffer between these two buses for bus matching.

12 to 15 are diagrams for explaining such a bus adapter device. FIG. 12 is a diagram showing the configuration of an electronic computer system showing the connection relationship between this bus adapter device and other devices, FIG. 13 is a diagram showing the configuration of the bus adapter device, and FIGS. 14 and 15 show the operation. FIG. In FIG. 12, 1 is a central processing unit, 2 is a main storage device, 3 is a system bus, 4 is a bus adapter device,
Reference numeral 5 is an input / output bus, 6 is an input / output control device, and 7 is an input / output device. The central processing unit 1 and the main storage device 2 are connected to the system bus 3, and the input / output control device 6 is connected to the input / output bus 5. The system bus 3 and the input / output bus 5 are connected via the bus adapter device 4. Although only one type of input / output control device 6 is shown in the figure, a plurality of input / output control devices 6 are generally connected to the input / output bus 5.

Further, in FIG. 13, reference numeral 8 stores an address in the main memory 2 for data transfer when executing an input / output instruction issued from the central processing unit 1 and input / output control information for data transfer. Address buffer, 9 is a data buffer that stores data sent from the system bus 3, 11 is a memory request output circuit that issues a data transfer request to the system bus 3, and 10 is an address buffer 8, data buffer 9, and memory request output circuit 11 Is a data transfer control circuit for controlling.

FIG. 14 is a time-series diagram showing the operation of the system in which the central processing unit 1 directly transfers the input / output control information for data transfer to the input / output control device 6, and FIG. 15 shows the central processing. 6 is a diagram showing, in a time series manner, an operation in a system in which the input / output control device 6 takes in the input / output control information stored in the main storage device 2 by the device 1 from the main storage device 2. FIG.

In FIG. 14, reference numerals 30 and 30a denote writing of input / output control information from the central processing unit 1 to the input / output control unit 6, 30 is from the central processing unit 1 to the bus adapter unit 4, and 30a is a bus. The transfer of the input / output control information from the adapter device 4 to the input / output control device 6 is shown. 3
1 is a data transfer request issued by the input / output control device 6 to the bus adapter device 4, 31a is a data transfer request to the main memory device 2 issued by the bus adapter device 4 which has received the data transfer request 31, and 32 is this data. Data transfer from the main storage device 2 to the bus adapter device 4 in response to the transfer request 31a, 3
2a is a data transfer in which the bus adapter device 4 transfers the data transferred in the data transfer 32 to the input / output control device 6.

Further, in FIG. 15, reference numeral 33 indicates transfer of input / output control information from the central processing unit 1 to the main storage unit 2, and 3
Reference numerals 4 and 34a indicate activation of the input / output operation from the central processing unit 1 to the input / output control unit 6, and this activation is sent from the central processing unit 1 to the bus adapter unit 4 as the input / output activation 34, and this input / output activation It is shown that the bus adapter device 4 having received 34 is sending it to the input / output control device 6 as the input / output activation 34a. Reference numeral 35 is a transfer request for input / output control information sent from the started input / output control device 6 to the bus adapter device 4, and reference numeral 35a is a transfer request 3 for this input / output control information.
5, the bus adapter device 4 receives the request for transfer of the input / output control information sent to the main memory device 2, 36 indicates the data transfer from the main memory device 2 to the bus adapter device 4 in response to the request for transferring the input / output control information, 36 a is a data transfer in which the bus adapter device 4 sends the data transfer 36 from the main storage device 2 to the input / output control device 6. 31, 31a, 3
Since the reference numerals 2 and 32a are the same as those in FIG. 14, the description thereof will be omitted.

Hereinafter, referring to FIGS. 13 to 15,
The operation will be described. A case of data transfer from the main storage device 2 to the input / output control device 6 (so-called WRITE operation in input / output operation) will be described here. (1) Method in which central processing unit 1 directly transfers input / output control information to input / output control device 6 First, central processing unit 1 transfers input / output control information for data transfer to the bus by transferring input / output control information 30. To the adapter device 4, the bus adapter device 4 writes to the input / output control device 6 by the transfer 30a of the input / output control information. As a result, the input / output control device 6 is activated. Input / output control device 6
Analyzes the written input / output control information.

As a result of the analysis, when the content of the input / output control information is data transfer from the main storage device 2 to the input / output control device 6, the input / output control device 6 issues a data transfer request 31 to the bus adapter device 4. To send. Bus adapter device 4
Then, the address on the main storage device 2 to be read, the control information, and the like, which are transmitted in response to the data transfer request 31, are stored in the address buffer 8. Subsequently, the bus adapter device 4 outputs the data transfer request 31 a from the memory request output circuit 11 to the main memory device 2. When the data transfer request is accepted, the bus adapter device 4 outputs the main storage address from the address buffer 8. The main storage device 2 transmits the data stored at the designated address to the bus adapter device 4 by the data transfer 32. The bus adapter device 4 temporarily stores the data transferred from the main storage device 2 in the data buffer 9, and then outputs the data stored in the data buffer 9 to the input / output bus 5 to complete the data transfer 32a.

(2) A method in which the input / output control device 6 reads from the main storage device 2 the input / output control information written in the main storage device 2 by the central processing unit 1. First, the central processing unit 1 inputs / outputs the input / output control information. The control information is written 33 to the main storage device 2. Next, the central processing unit 1 makes the bus adapter unit 4 start 34 of the input / output operation for data transfer and start 3 of the input / output operation.
The bus adapter device 4 which received 4 transmits this to the input / output control device 6 as the activation 34a of the input / output operation. As a result, the input / output control device 6 is activated. The activated input / output control device 6 issues a transfer request 35 of the input / output control information to the bus adapter device 4. In response to this, the bus adapter device 4 issues a transfer request 35a for input / output control information to the main storage device 2. The main storage device 2 transfers the input / output control information 36 to the bus adapter device 4, and in response to this, the bus adapter device 4 transfers the input / output control information 36a to the input / output control device 6. After analyzing this input / output control information, the input / output control device 6 outputs a data transfer request 31 to the bus adapter device 4. For the operation after this,
This is the same as after the data transfer request 31 is output when the central processing unit 1 transfers the input / output control information to the input / output control device 6.

[0011]

Since the conventional bus adapter device operates as described above, the bus adapter device operates as the main storage device 2 after the input / output control device is activated.
However, there is a problem that it takes a long time to issue a data transfer request, and as a result, it takes a long time from when the input / output control device is activated until the input / output control device receives the data transfer.

Further, in order for the bus adapter device to transfer data to the input / output control device, it is necessary to further acquire the bus right of the system bus after acquiring the bus right of the output bus. Only then will data transfer be possible. Therefore, in this method, the time from the output of the I / O controller to the data transfer request until the I / O controller receives the data transfer becomes long,
There is a problem that the performance when the I / O controller performs burst transfer does not improve.

The present invention has been made to solve the above problems, and when an input / output device for performing burst transfer is connected to the input / output bus, the input / output control device is input from the central processing unit. When the output control information is transferred, the bus adapter itself analyzes the I / O control information, and if the result is data transfer from the main memory to the I / O controller, before the I / O controller issues a data transfer request. , By starting the data transfer request from the bus adapter device so as to transfer the data from the main memory device, the time from the activation of the input / output control device to the reception of the data transfer by the input / output control device is shortened. The purpose is to obtain a bus adapter device.

Further, in order to shorten the time from when the data transfer request is issued from the input / output control device until the data is received, the data of consecutive addresses in the main storage device are prefetched and stored in the data buffer of the bus adapter device. In this way, a bus adapter device that enables data transfer to the input / output control device without issuing a memory request to the main storage device each time a data transfer request from the input / output control device is received is obtained. That is also the purpose.

[0015]

In the bus adapter device according to the present invention, one is connected to a central processing unit and a main memory control device via a system bus, and the other is connected to an input / output control device via an input / output bus. In the connected bus adapter device, a table in which a flag indicating whether or not the I / O control device performs burst transfer is stored in association with the device address of the I / O control device, and the input from the main storage control device is performed. Data storage means for storing data to be transferred to the output control device and input / output control information issued from the central processing unit to the input / output control device are analyzed to output the input / output operation indicated by the input / output control information. Based on the address of the output operation detecting means for detecting the operation and the address of the input / output control device for performing the output operation detected by the output operation detecting means, Search and includes a judging means for judging whether or not the input-output control unit burst transfer,
Before the data transfer request is received from the input / output control device, the data to be transferred to the input / output control device is prefetched and stored in the data storage means.

Further, in the bus adapter device, one of which is connected to the central processing unit and the main memory control device via a system bus, and the other of which is connected to the input / output control device via an input / output bus. A flag indicating whether or not to perform burst transfer and a storage address of the input / output control information on the main storage device in association with the device address of the input / output control device, and a table from the main storage control device. Data storage means for storing data to be transferred to the writing output control device, and an address on the main storage device which the input / output control device has requested for fetching input / output control information is detected and held. Address detection means for comparing whether or not it matches the storage address of the output control information, and a notification of the match from the address detection means, Output operation detecting means for analyzing the read input / output control information to detect that the input / output operation indicated by the input / output control information is an output operation, and before performing the output operation detected by the output operation detecting means Before the data transfer request is received from the input / output control device, and a determination means for searching the table based on the address of the input / output control device to determine whether or not the input / output control device performs burst transfer. In addition, the data to be transferred to the input / output control device is pre-stored in the data storage means.

Further, only the address of the input / output control device for carrying out the burst transfer is stored in the table.

Further, the output operation detecting means is configured to analyze based on the data on the input / output bus.

Further, the output operation detecting means is configured to analyze based on the data on the system bus.

Further, the central processing unit is provided with a shift register for setting the data to be stored in the table, the table is configured by the shift register, and the data is set in the table by using the shift register when the system is activated. It was done like this.

Further, the table is composed of a plurality of registers, an interface circuit is provided for interfacing the registers with the central processing unit, and data is set in the table from the central processing unit. .

Further, the address on the main memory device in which the input / output control information is stored is held, the data on the system bus is monitored, the storage operation for the address is detected, and the output operation is performed. An address register for notifying the detecting means is provided.

Further, an address register for setting an address on the main storage device in which the input / output control information is stored, an address detecting means for monitoring address data on the system bus, the address register and the address detection. Comparing means with the detection address of the means, and notifying the output operation detecting means of the coincidence.

Further, a recognition means for recognizing that a failure has occurred in the storage operation of the input / output control information from the central processing unit to the main storage device is provided, and when the recognition means recognizes the occurrence of the failure, the operation is started. The transfer of data from the main storage device is stopped.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. 1 and 2 are diagrams for explaining an embodiment of a bus adapter device according to the present invention. FIG. 1 is a diagram showing the configuration of the bus adapter device, and FIG. 2 is a diagram showing the operation of the bus adapter device in chronological order. Is. In FIG. 1, 1 is a central processing unit, 2 is a main storage device, 3 is a system bus, 5 is an input / output bus, 6 is an input / output control device, and 16 is a bus adapter device. The bus adapter device 16 is an address buffer 8 for storing an address in the main storage device 2 for data transfer and an input / output control information for data transfer when executing an input / output instruction issued from the central processing unit 1, a system. Bus 3
A data buffer 9 for storing data sent from
A memory request output circuit 11 that issues a data transfer request to the system bus 3, an address buffer 8, a data transfer control circuit 12 that controls the data buffer 9 and the memory request output circuit 11, and a central processing unit 1 are connected to the input / output bus 5. The device address, which is a number for identifying the input / output control device 6 and the information indicating whether or not the input / output control device 6 performs burst transfer, and the input / output control information Is detected by the output operation detection circuit 15 and the output operation detection circuit 15 for detecting that the content of the above indicates a data transfer request from the main memory device 2 to the input / output control device 6 (so-called WRITE operation in input / output operation). , A decision circuit 13 for deciding whether or not the input / output control device 6 which is a data transfer destination performs burst transfer. That.

In FIG. 2, reference numeral 30 indicates writing of input / output control information by the central processing unit 1 to the bus adapter device 16, and reference numeral 30a indicates writing of input / output control information by the bus adapter device 16 to the input / output control device 6. , 31 is a data transfer request issued by the input / output control device 6 to the bus adapter device 16, 31a is a data transfer request issued by the bus adapter device 16 to the main memory device 2, and 32 is a data transfer request from the main memory device 2 to the bus adapter device 16. Data transfer to the input / output control device 6 from the bus adapter device 16 is shown.

The operation will be described below with reference to the drawings. Since the present invention is applied only to the so-called WRITE operation, only the case of transferring data from the main storage device 2 to the input / output control device 6 will be described here. Further, here, the byte width number of data that can be transferred at a time by each bus is 4 bytes (32 bits) for the input / output bus and 8 bytes (64 bits) for the system bus.

First, the central processing unit 1 transfers the input / output control information 30 to the bus adapter unit 16.
The bus adapter device 16 transfers this input / output control information to the input / output control device 6 by the transfer 30a of the input / output control information. During the transfer 30a of the input / output control information, the output operation detection circuit 15 of the bus adapter device 16 fetches the input / output control information output to the input / output bus 5 (for example,
(By recognizing that the data on the I / O bus 5 is the I / O control information by monitoring a specific bit), the data is stored in the address buffer 8 and the content is analyzed to confirm that the content of the I / O control information is In the case of data transfer from the main storage device 2 to the input / output control device 6, the central processing unit 1 included in the input / output control information controls the input / output control device 6 connected to the input / output bus 5. The device address, which is a number for identification, is output to the determination circuit 13. Judgment circuit 13
The device table 14 is searched based on the device address input from the output operation detection circuit 15 to see if a matching device address is on the table 14. If the corresponding device address exists, the I / O controller 6 having the device address determines whether or not to perform the burst transfer, based on the flag data on the device table 14. As a result of the determination, when the input / output control device 6 of the device address is to perform burst transfer,
The determination circuit 13 notifies the data transfer control circuit 12 to start data transfer. The data transfer control circuit 12 controls the data transfer memory request output circuit 11 to output a data transfer request from the bus adapter device 16 to the main memory device 2.

As a result, the bus adapter device 16 executes the data transfer request 31a based on the address on the main storage device 2 designated by the input / output control information stored in the address buffer 8. This data transfer request 31a
On the other hand, the data transfer 32 is executed from the main storage device 2 to the bus adapter device 16. The bus adapter device 16 is
The 64-bit (8-byte) data transferred from the main storage device 2 is stored in the data buffer 9.

Since the data transfer in this embodiment is performed in bursts, the memory request output circuit 1
When No. 1 receives the data transfer 32 from the main storage device 2, it outputs the data transfer request 31a to the address on the main storage device immediately succeeding.

On the other hand, the input / output control device 6 analyzes the input / output control information written by the transfer 30a of the input / output control information, and the content is data transfer from the main storage device 2 to the input / output control device 6. Data transfer request 31
Is output to the bus adapter device 16.

Data transfer request 3 from the input / output control unit 6
The bus adapter device 16 that has received 1 has already transferred the data necessary for transfer to the input / output control device 6 to the main storage device 2.
Since it is stored in the data buffer 9 in advance,
The data is read from the data buffer 9 and the data transfer 32a is executed to transfer 4 bytes (32 bits) of data to the input / output control device 6. Since 8 bytes (64 bits) of data are stored in the data buffer 9 by one data transfer 32, two data transfer requests 31 from the input / output control device 6 can be handled.

Since the I / O controller 6 is burst transfer,
Upon receiving the data transfer 32a from the bus adapter device 16, immediately, the next data transfer request 31 is transmitted to the bus adapter device 16.

In the first embodiment, the device table 14 is provided with the device address and the flag indicating whether or not the device corresponding to the device address makes the burst transfer. However, the device table 14 has the burst transfer. It is also possible to set only the device address for performing the above, and to judge by the device having the device address not set in the device table 14 by not performing the burst transfer. This also applies to the following embodiments.

As described above, according to the first embodiment, when the input / output control information is written from the central processing unit 1 to the input / output control device 6, the bus adapter device 16 takes in this input / output control information. Since the data transfer request can be issued to the main storage device 2, the bus adapter device 16 is activated after the input / output control device 6 is activated.
The time taken to issue a data transfer request to the main storage device can be shortened.

Before the data transfer request 31 from the input / output control device 6 is received, the bus adapter device 16 fetches the data to be transferred from the main storage device 2 and stores it in the data buffer 9. Therefore, it becomes possible to immediately send data to the data transfer request from the input / output control device 6. Therefore, the time from when the input / output control device 6 is activated until the bus adapter device 16 issues a data transfer request to the main storage device 2 can be shortened.

Since the data transfer from the continuous addresses on the main memory 2 to the data buffer 9 has already been performed and is buffered until the data buffer 9 becomes the buffer full state, the burst transfer is performed. In this case, since it is sufficient to read the data from the data buffer, the time required for the input / output control device to output the data transfer request and receive the data transfer is shortened.

Embodiment 2 FIG. 3 is a diagram showing the configuration of another embodiment of the bus adapter device according to the present invention. In the first embodiment, the contents of the device table 14 cannot be changed after being set once.
In the second embodiment, the contents of the device table 14 can be set when the system is activated.

In FIG. 3, reference numeral 1a denotes a central processing unit, 16
a is a bus adapter device according to the second embodiment, and the bus adapter device 16a includes a device table 14a including a shift register for holding information as to whether or not the input / output control device 6 performs burst transfer. Shift register 17 for transferring information of input / output control device 6 set in table 14a, device table 14
It has a scan control circuit 18 for controlling a and the shift register 17. The same parts as those in FIG. 1 according to the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

The operation of the second embodiment will be described below with reference to the drawings. When the system is started up, the central processing unit 1a writes in the shift register 17 a device address for the input / output control device 6 and information as to whether or not the input / output control device 6 designated by the device address makes a burst transfer. I do. When the writing to the shift register 17 is completed, the central processing unit 1a reports the completion of writing to the bus adapter device 16a. Upon receiving the completion report, the scan control circuit 18 of the bus adapter device 16a outputs a clock signal and a control signal, shifts the information set in the shift register 17 bit by bit, and transfers the information to the device table 14a. This operation is repeated for the required number of input / output control devices 6. In this way, by shifting the contents of the shift register 17 to the device table 14a, it is possible to create the device table 14c that the determination circuit 13 refers to when executing the input / output instruction. The subsequent operation is the same as that in the first embodiment, and therefore its explanation is omitted.

In the second embodiment, the register for transferring the write data to the device table 14a is composed of the shift register, but the connection signal line between the central processing unit 1a and the bus adapter device 16a is used. Alternatively, the number of may be increased to form a normal register.

As described above, according to the second embodiment, since the device table 14a is set by using the scan path when the system is started up, the connected I / O controller 6 bursts. It becomes possible to set an appropriate device table 14a at the time of starting the system for information as to whether or not to transfer it, so that a flexible system can be constructed.

Embodiment 3. FIG. 4 is a diagram showing the configuration of still another embodiment of the bus adapter device according to the present invention. In the second embodiment, a special signal line is provided between the central processing unit and the bus adapter device to set the device table, but in the third embodiment, the central processing unit and the bus adapter device are set. This device table is set without providing a special signal line between and.

In FIG. 4, reference numeral 16b denotes the third embodiment.
Bus adapter device in
6b is composed of a plurality of registers for holding information as to whether or not the I / O controller 6 performs burst transfer, and each of the registers has a device table 14 having an address which can be directly accessed from the central processing unit 1.
b, it has an interface circuit 19 with a system bus for transferring information of the input / output control device 6 set in the device table 14b to the device table 14b. The same parts as those in FIG. 1 according to the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

The operation of the third embodiment will be described below with reference to the drawings. The central processing unit 1
Information about whether or not the input / output control device 6 set in the device table 14b performs burst transfer is prepared, and the device table 14b is transmitted via the bus interface circuit 19.
Transfer to The above operation is performed as many times as necessary and for the number of input / output control devices. In this way, predetermined data in the device table 14b, that is, information indicating whether or not the input / output control device 6 performs burst transfer is set. After this,
Since the operation is the same as that of the first embodiment, the description thereof will be omitted.

As described above, according to the third embodiment, the device table 14 can be provided without providing a special signal line between the central processing unit 1 and the bus adapter unit 16b.
It is possible to set information indicating whether or not the input / output control device 6 performs burst transfer in b from the central processing unit 1.
Therefore, the device table 14b can be set even when the system is not activated, and flexibility can be provided by constructing the system.

Fourth Embodiment 5 and 6 are diagrams showing the configuration of still another embodiment of the bus adapter device according to the present invention. FIG. 5 is a diagram showing the configuration of the bus adapter device according to the fourth embodiment, and FIG. 6 is a diagram for explaining the operation of the bus adapter device in chronological order. In the fourth embodiment, an output operation detection circuit 20 for detecting data on the system bus 3 is provided instead of the output operation detection circuit 15 for detecting data on the input / output bus 5 in the first embodiment. It is a thing.

In FIG. 5, 1b is a central processing unit, 16
c is a bus adapter device, 20 is an output operation detection circuit for detecting that the content of the input / output control information is data transfer from the main storage device 2 to the input / output control device 6, and 21 is from the central processing unit 1 to the main storage device. This is a control signal line for notifying the device 2 to write the input / output control information.

Further, in FIG. 6, 37 is a central processing unit 1b which the central processing unit 1 sends to the bus adapter unit 16c.
From the central processing unit 1b to the main storage device 2 to write the input / output control information to the main storage device 2 for writing the input / output control information to the main storage device 2, and 38 to the bus adapter device 16c. Is a data transfer request issued by the bus adapter device 16c to the main storage device 2, 32 is a data transfer from the main storage device 2 to the bus adapter device 16c, and 34 is a central part. Input / output operation to the input / output control device 6 from the processing device 1b to the bus adapter device 16c is started, and 34a is an input / output operation from the bus adapter device 16c to the input / output control device 6 which receives the input / output operation start 34. , 35 is a transfer request of the input / output control information from the input / output control device 6 to the bus adapter device 16c, and 36a is the bus adapter device 16c. From the input / output control device 2 to the input / output control device 2, 31 is a data transfer request issued by the input / output control device 6 to the bus adapter device 16c, and 32a is data transfer from the bus adapter device 16c to the input / output control device 6. Is.

The operation will be described below with reference to the drawings. When writing the input / output control information to the main memory 2, the central processing unit 1b first sets the control signal line 21.
The write notification 37 of the input / output control information to the main storage device 2 is executed to the bus adapter device 16c via the and the output operation detection circuit 20 is notified. Next, the central processing unit 1b
Executes the writing 33 of the input / output control information to the main storage device 2. At this time, the output operation detection circuit 20 of the bus adapter device 16c analyzes the data output on the system bus 3 (for example, by detecting ON / OFF of a specific bit, or by writing a notification of input / output information). Three
7 and write 33 of the input / output control information (by preventing other instructions from interrupting), and if this data is the input / output control information, the execution of the input / output control information fetch 38 is instructed. Then, the input / output control information is stored in the data buffer 9. Alternatively, another instruction cannot be interrupted between the input / output information write notification 37 and the input / output control information write 33, so that the next instruction of the input / output information write notification 37 is the input / output control. As the information writing 33, the execution of the input / output control information fetching 38 is instructed to store the input / output control information in the data buffer 9. At the same time, the output operation detection circuit 20 analyzes the content of the input / output control information to detect whether or not the data is transferred from the main storage device 2 to the input / output control device 6. When it is detected that the data is transferred from the main storage device 2 to the input / output control device 6, the output operation detection circuit 20 causes the device address of the input / output control device 6 of the data transfer destination indicated by the input / output control information. Is output to the determination circuit 13. The determination circuit 13 searches the device table 14 on the basis of the input device address to determine whether a matching device address is on the device table 14. If a corresponding device address is found as a result of the search, the I / O controller 6 having that device address determines whether or not to perform burst transfer, based on the flag data on the device table 14. As a result of the determination, when the input / output control device 6 of the device address is to perform burst transfer, the determination circuit 13 determines that the data transfer control circuit 1
2 is notified to start data transfer. The data transfer control circuit 12 controls the data transfer memory request output circuit 11 from the bus adapter device 16 to the main memory device 2.
The data transfer request 32 is controlled to be output. After this, the bus adapter device 16c performs data transfer until the data buffer 9 becomes the buffer full state as in the first embodiment.

In the central processing unit 1b, after the writing 33 of the input / output control information to the main memory 2 is executed, the activation 34 of the input / output control device is executed to the bus adapter device 16c. In response to the activation 34 of the input / output control device, the bus adapter device 16c executes the activation 34a of the input / output control device for the input / output control device 6.

The input / output control device 6 having received the activation 34a of the input / output control device reads the input / output control information.
The data transfer request 35 of the input / output control information is executed. Since the input / output control information is already stored in the data buffer 9 of the bus adapter device 16c, the data transfer 36a of the input / output control information is immediately executed. This data transfer 36
Upon receiving a, the input / output control device 6 causes the data transfer request 3
1 for the bus adapter device 16c. In response to the data transfer request 31, the bus adapter device 16c
Executes the data transfer 32a to transfer the data already pre-stored in the data buffer 9 from the main storage device 2 to the input / output control device 6. Since the operation thereafter is the same as that of the first embodiment, the description thereof is omitted.

As described above, according to the fourth embodiment, when the input / output control information is written from the central processing unit to the main storage device, the bus adapter device fetches the input / output control information and the input / output control device is fetched. Since the data transfer request can be issued to the main storage device before the start-up, the processing time of the output operation can be shortened and the system throughput is improved.

Embodiment 5 FIG. 7 is a diagram showing the configuration of still another embodiment of the bus adapter device according to the present invention. In the figure, 16d is a bus adapter device, 22
Is an address detection circuit that monitors the address of the main memory 2 when writing data from the central processing unit 1 to the main memory 2 and detects the address corresponding to the storage address of the input / output control information. The same parts as those in Embodiment 4 are designated by the same reference numerals and the description thereof will be omitted. In the fifth embodiment,
The fourth embodiment is applied when the address on the main memory 2 where the input / output control information is stored is fixed.

The operation of the fifth embodiment will be described below with reference to the drawings. When the input / output control information is stored at a fixed address on the main storage device 2,
The address detection circuit 22 constantly monitors the address of the main memory 2 when writing data from the central processing unit 1 to the main memory 2. Therefore, when the address detection circuit 22 detects that writing has been performed to the address corresponding to the address in which the input / output control information is stored, the central processing unit 1 writes the input / output control information in the main storage device 2. Then, the output operation detection circuit 20 is notified. Since the operation thereafter is the same as that of the fourth embodiment, the description thereof will be omitted.

As described above, according to the fifth embodiment, the same effect as that of the fourth embodiment can be obtained without providing a specific signal line between the central processing unit 1 and the bus adapter device 16c. You can

Embodiment 6 FIG. FIG. 8 is a diagram showing the configuration of still another embodiment of the bus adapter device according to the present invention. In FIG. 8, 16e is a bus adapter device, 2
3 is an address detection circuit for detecting an address of data transfer from the central processing unit 1 to the main storage device 2, 24 is an address register for setting a main storage address for storing input / output control information, and 25 is a detection circuit 23 for detection. It is a comparison circuit that determines whether or not the generated main memory address is the main memory address in which the input / output control information is stored. The same components as those in the fifth embodiment are designated by the same reference numerals and the description thereof will be omitted.

The operation of the sixth embodiment will be described below with reference to the drawings. When the input / output control information is not stored in the fixed address on the main storage device 2, the central processing unit 1 writes the address of the main storage device 2 where the input / output control information is stored in the address register 24. The address detection circuit 23 detects an address on the main storage device 2 during data transfer performed on the system bus 3,
It outputs to the comparison circuit 25. The comparison circuit 25 compares the detected address in the main memory device 2 with the address in the main memory device 2 set in the address register 24 and stores the input / output control information in the main memory device 2. If the above condition applies, the output operation detection circuit 20 is notified. Since the operation thereafter is the same as that of the fourth embodiment, the description thereof will be omitted.

As described above, according to the sixth embodiment, an address to be detected can be freely set even when the address on the main storage device in which the input / output control information is stored is not a fixed address. Therefore, the system construction becomes flexible.

Embodiment 7 FIG. FIG. 9 is a diagram showing the configuration of still another embodiment of the bus adapter device according to the present invention. In FIG. 9, 1c is a central processing unit, 16f is a bus adapter device, and 29 is a failure notification signal line for notifying that a failure has occurred when writing data from the central processing unit 1 to the main memory 2. In the seventh embodiment,
In the fourth embodiment, error processing is added. The same parts as those in Embodiment 4 are designated by the same reference numerals and the description thereof will be omitted.

The seventh embodiment will be described below with reference to the drawings.
The operation will be described. Since the normal operation is the same as the operation in the fourth embodiment, it is omitted and only the operation peculiar to the seventh embodiment will be described.

When the central processing unit 1c writes the input / output control information to the main memory device 2, the central processing unit 1c writes the input / output control information via the control signal line 21 to the bus adapter device 16f. To notify. The bus adapter device 16f that received the notification is the central processing unit 1c.
When the I / O control information is written to the main memory device 2, the I / O control information is stored in the data buffer 9 and at the same time, the output operation detection circuit 20 analyzes the contents of the I / O control information, It is detected whether or not the data is transferred to the input / output control device 6. In the case of data transfer from the main storage device 2 to the input / output control device 6, the output operation detection circuit 20
Outputs the device address of the input / output control device 6 of the data transfer destination to the determination circuit 13. The determination circuit 13 determines whether or not the input device address is burst-transferred, based on the flag data on the device table 14. If the device address input / output control device performs burst transfer, the determination circuit 13 outputs a data transfer request from the main storage device 2 to the bus adapter device 16f to the memory request output circuit 11. To control.

By the way, if any error occurs when the central processing unit 1c writes the input / output control information in the main storage device 2, the failure notification signal line is sent to the data transfer control circuit 12 of the bus adapter device 16f. 29 notifies that a failure has occurred in the writing of the input / output control information from the central processing unit 1c to the main storage device 2. Upon receiving this failure notification, the data transfer control circuit 12 controls the memory request output circuit 11 so as not to output a data transfer request to the main storage device 2.

Further, with respect to the data transfer request output before receiving the notification of the failure through the failure signal line 29, the transferred data is controlled not to be buffered.

As described above, according to the seventh embodiment, when the bus adapter device receives an error of any kind, the data transfer is prevented from being performed, so that erroneous data is not transferred.

Embodiment 8. 10 and 11 are diagrams for explaining still another embodiment of the bus adapter device according to the present invention. FIG. 10 is a diagram showing the configuration of the bus adapter device, and FIG. 11 shows its operation in time series. It is a figure. FIG.
In 0, 16 g is a bus adapter device, 26 is an output operation detection circuit for detecting that the content of the input / output control information is a data transfer request from the main storage device 2 to the input / output control device 6, and 27 is a main storage device. An address detection circuit for detecting that the request from the input / output control device is a transfer request of the input / output control information based on the address on the device 2. In addition, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

Further, in FIG. 11, reference numeral 33 denotes writing of input / output control information from the central processing unit 1 to the main storage unit 2,
Reference numeral 34 is a start-up of the input / output control device 6 output from the central processing unit 1 to the bus adapter device 16g, and reference numeral 34a is a start-up 34 of the input / output control device 6, and the bus adapter device 16g outputs the input / output control device 6 to the input / output control device 6. Output operation is started, 35 is a request for transfer of input / output control information from the input / output control device 6 to the bus adapter device 16g, 35a is request for transfer of input / output control information from the bus adapter device 16g to the main storage device 2, and 36 is Transfer of input / output control information from the main storage device 2 to the bus adapter device 16g; 36a, transfer of input / output control information from the bus adapter device 16g to the input / output control device 2; 31; A data transfer request issued to the device 16g, 31a a data transfer request issued to the main storage device 2 by the bus adapter device 16g, and 32 a bus adapter device 1 from the main storage device 2. Data transfer to the g, 32a is a data transfer to the output device 6 from the bus adapter device 16g.

The operation of the eighth embodiment will be described below with reference to the drawings. After the central processing unit 1 writes 33 the input / output control information to the main storage device 2, it sends an input / output activation 34 to the input / output control device 6 to the bus adapter device 16g. The bus adapter device 16g having received the input / output activation 34 transmits it to the input / output control device 6 as the input / output activation 34a. The input / output control device 6 sends a transfer request 35 of the input / output control information to the bus adapter device 16g to fetch the input / output control information from the main storage device 2. In response to this request, the bus adapter device 16g stores in the address buffer 8 the address on the main storage device 2 for reading the sent input / output control information, and the input / output control for the main storage device 2 is performed. An information transfer request 35a is sent. Further, the address detecting circuit 27 detects whether or not this address is an address in which the input / output control information is stored, and when the address is an address in which the input / output control information is stored, detects an output operation. The circuit 26 is notified that the input / output control information is read.

Upon receiving the input / output control information transfer request 35a, the main storage device 2 executes the input / output control information transfer 36 and sends the input / output control information to the bus adapter device 16g.
The bus adapter device 16g executes the input / output control information transfer 36a to transfer the received input / output control information to the input / output control device 6. As a result, the input / output control device 6 is activated. Further, the detection circuit 26 of the bus adapter device 16g analyzes the content of the input / output control information transferred from the main storage device 2 and then transfers the input / output control device 6 from the main storage device 2.
In the case of data transfer to, the device address of the data transfer destination is sent to the determination circuit circuit 13. The determination circuit 13 searches the device table 14 based on the device address input from the detection circuit 26 to determine whether a matching device address is on the table 14. When the corresponding device address exists, whether the I / O controller 6 having the device address makes a burst transfer or not is determined by the flag data on the device table 14. If the result of the determination is that the input / output control device 6 of the device address is to perform burst transfer, the determination circuit 1
3 notifies the data transfer control circuit 12 to start data transfer. The data transfer control circuit 12 controls the data transfer memory request output circuit 11 to output a data transfer request from the bus adapter device 16g to the main storage device 2. After this, the bus adapter device 16g
Is the data buffer 9 as in the first embodiment.
Data is transferred to and from the main memory 2 until the buffer becomes full.

On the other hand, the input / output control device 6 issues the data transfer request 31 when receiving the input / output control information transfer 36a.
At this time, since the data transfer 32 has already been completed, the bus adapter device 6 performs the data transfer 32a.

As described above, according to the eighth embodiment,
When the I / O control information is transferred from the main memory to the I / O controller, the bus adapter device can issue a data transfer request to the main memory. The time until the device issues a data transfer request to the main memory can be shortened.

Needless to say, the above-described respective embodiments can be implemented in various combinations.

[0072]

As described above, in the bus adapter device according to the present invention, a table storing a flag indicating whether or not the input / output control device performs burst transfer in association with the address of the input / output control device, Data storage means for storing data to be transferred from the main storage control device to the input / output control device and the input / output control information issued from the central processing unit to the input / output control device are analyzed, and the input / output control information indicated by this input / output control information is analyzed. The output operation detecting means for detecting that the output operation is the output operation, and the input / output control apparatus searches the table based on the address of the input / output control apparatus performing the output operation detected by the output operation detecting means, and the input / output control apparatus bursts. And a determination means for determining whether or not to perform the transfer. The bus adapter device is mainly used before the input / output control device issues a data transfer request to the bus adapter device. Since as can issue a data transfer request to the device, since it takes activated output control unit bus adapter device it is possible to shorten the time until issuing a data transfer request. Further, it becomes possible to pre-store the data to be transferred to the input / output control device in the data storage means before receiving the data transfer request from the input / output control device, thus improving the throughput of the system.

A table in which a flag indicating whether or not the I / O controller performs burst transfer is stored in association with the address of the I / O controller, and data to be transferred from the main memory controller to the I / O controller are stored. Whether or not it matches the storage address of the input / output control information, which stores and stores the data storage means for storing and the address on the main storage device that the input / output control device has requested to fetch the input / output control information When the address detection means for comparing the above and the address detection means receives the notification of the coincidence from the address detection means, the input / output control information read from the main storage device is analyzed, and the input / output operation indicated by the input / output control information is output. The table is searched based on the addresses of the output operation detecting means for detecting the operation and the input / output control device for the output operation detected by the output operation detecting means. The control device is so provided judging means for judging whether or not to perform burst transfer, and exhibits the same effect.

Further, since only the address of the input / output control device for performing the burst transfer is stored in the table, the capacity of the table can be reduced and the input / output control device performs the burst transfer. It is possible to shorten the determination time of whether or not.

Since the output operation detecting means is configured to analyze the data on the input / output bus, the data on the bus can be input / output by monitoring a specific bit on the input / output bus. It can be recognized as control information.

Further, since the output operation detecting means is configured to analyze based on the data on the system bus,
It is possible to recognize that the data on the bus is the input / output control information at an earlier timing.

Further, the central processing unit is provided with a shift register for setting the data to be stored in the table, the table is constituted by the shift register, and the data is set in the table by using the shift register when the system is started. As a result, the system configuration can be made flexible.

Further, since the table is composed of a plurality of registers and an interface circuit for interfacing the registers with the central processing unit is provided and data is set in the table from the central processing unit, the table is always available. You can change the table,
More flexible system configuration is possible.

Further, by holding the address on the main storage device in which the input / output control information is stored, monitoring the data on the system bus and detecting the storage operation for the address, the input / output control information is stored in the main storage device. Since the timing of storing the I / O information is detected, it is effective when the input / output control information is stored in a fixed address on the main storage device.

Further, an address register for setting an address on the main memory device in which the input / output control information is stored, an address detecting means for monitoring the address data on the system bus, and a detection address for the address register and the address detecting means. Since the timing at which the input / output control information is stored in the main storage device is detected by comparing the above, it is effective even if the address on the main storage device where the input / output control information is stored is not fixed.

Further, a recognition means for recognizing that a failure has occurred in the operation of storing the input / output control information from the central processing unit to the main storage device is provided, and when the recognition means recognizes the occurrence of the failure, it is started. Since the data transfer from the main storage device is stopped, erroneous data will not be transferred to the input / output device.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of a bus adapter device according to the present invention.

FIG. 2 is a diagram showing an operation in the first embodiment in time series.

FIG. 3 is a diagram showing a configuration of a second embodiment of a bus adapter device according to the present invention.

FIG. 4 is a diagram showing a configuration of a third embodiment of a bus adapter device according to the present invention.

FIG. 5 is a diagram showing a configuration of a fourth embodiment of a bus adapter device according to the present invention.

FIG. 6 is a diagram showing an operation in the first embodiment in time series.

FIG. 7 is a diagram showing a configuration of a fifth embodiment of a bus adapter device according to the present invention.

FIG. 8 is a diagram showing a configuration of a sixth embodiment of a bus adapter device according to the present invention.

FIG. 9 is a diagram showing a configuration of a seventh embodiment of a bus adapter device according to the present invention.

FIG. 10 is a diagram showing a configuration of an eighth embodiment of a bus adapter device according to the present invention.

FIG. 11 is a diagram showing an operation in the eighth embodiment in time series.

FIG. 12 is a diagram showing a configuration of a conventional computer system.

FIG. 13 is a diagram showing a configuration of a conventional bus adapter device.

FIG. 14 is a diagram illustrating an example of an operation of a bus adapter device in a conventional example in time series.

FIG. 15 is a diagram for explaining another example of the operation of the bus adapter device in the conventional example in time series.

[Explanation of symbols]

1, 1a, 1b, 1c Central processing unit, 2 main storage devices, 3 system buses, 16, 16a, 16b, 16
c, 16d, 16e, 16f, 16g bus adapter device, 5 input / output bus, 6 input / output control device, 8 address buffer, 9 data buffer, 11 memory request output circuit, 12 data transfer control circuit, 13 determination circuit, 14, 14a, 14b device table, 15
Output operation detection circuit, 17 shift register, 18 scan control circuit, 19 bus interface circuit, 20
Output operation detection circuit, 21 control signal line, 22, 23
Address detection circuit, 24 address register, 25 comparison circuit, 26 output operation detection circuit, 27 address detection circuit, 28 comparison circuit, 29 failure notification signal line.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Ken Sanbe 2-3-3 Marunouchi, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd. (72) Hidetoshi Funakura 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd.

Claims (10)

[Claims] 1. A bus adapter device, one of which is connected to a central processing unit and a main memory controller via a system bus, and the other of which is connected to an I / O controller via an I / O bus. Table storing a flag indicating whether or not to perform burst transfer in association with the device address of the input / output control device, and data storage means for storing data to be transferred from the main storage control device to the input / output control device And an output operation detecting unit that analyzes the input / output control information issued from the central processing unit to the input / output control apparatus to detect that the input / output operation indicated by the input / output control information is an output operation. The table is searched based on the address of the input / output control device that performs the output operation detected by the output operation detection means, and the input / output control device performs the burst transfer. Determining means for determining whether or not the data to be transferred to the input / output control device is stored in advance in the data storage means before receiving a data transfer request from the input / output control device. Characteristic bus adapter device. 2. A bus adapter device, one of which is connected to a central processing unit and a main storage controller via a system bus, and the other of which is connected to an input / output controller via an input / output bus. A table indicating whether or not a burst transfer is to be performed and a storage address of the input / output control information on the main storage device in association with the device address of the input / output control device; A data storage unit for storing data to be transferred to the writing / outputting control unit; and an input / output control unit for detecting and holding an address on the main storage unit requested by the input / output control unit to fetch the input / output control information. Address detection means for comparing whether or not it matches the storage address of the output control information, and a notification of the match from the address detection means, By analyzing the crowded only input and output control information,
The output operation detecting means for detecting that the input / output operation indicated by the input / output control information is an output operation, and the table based on the address of the input / output control device for performing the output operation detected by the output operation detecting means. And a determining unit that determines whether or not the input / output control device performs burst transfer, and the input / output control device in the data storage unit before receiving a data transfer request from the input / output control device. A bus adapter device characterized in that it pre-stores data to be transferred to the device. 3. The bus adapter device according to claim 1, wherein only the address of the input / output control device that performs burst transfer is stored in the table. 4. The bus adapter device according to claim 1, wherein the output operation detecting means is configured to analyze based on the data on the input / output bus. 5. The bus adapter device according to claim 1, wherein the output operation detecting means is configured to analyze the data on the system bus. 6. The central processing unit is provided with a shift register for setting data to be stored in the table, the table is configured by the shift register, and data is set in the table by using the shift register when the system is started. The bus adapter device according to any one of claims 1 to 5, wherein 7. The table is composed of a plurality of registers, an interface circuit is provided for interfacing the registers with the central processing unit, and data is set in the table from the central processing unit. The bus adapter device according to any one of claims 1 to 5. 8. An output operation is performed by holding an address on the main storage device in which the input / output control information is stored, monitoring data on the system bus, detecting a storage operation for the address, and outputting the output operation. The bus adapter device according to claim 5, further comprising an address register for notifying the detecting means. 9. An address register for setting an address on the main memory in which the input / output control information is stored,
Address detecting means for monitoring address data on the system bus, and comparing means for comparing the address detected by the address register and the detecting address of the address detecting means and notifying the output operation detecting means of coincidence are provided. The bus adapter device according to claim 5, wherein 10. A recognition means is provided for recognizing that a failure has occurred in the storage operation of the input / output control information from the central processing unit to the main storage device, and when the recognition means recognizes the occurrence of the failure, it is started. 10. The bus adapter device according to any one of claims 1 to 9, characterized in that the data transfer from the main storage device that has been stopped is stopped.