JPH11284201A - Fully inverted soi mosfet - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-performance transistor which constitutes the next- generation semiconductor integrated circuit for which superhigh-density integration and extremely low power consumption are required. SOLUTION: In a fully inverted SOI MOSFET, the termination of an electric force line from a gate in an ionized impurity in a space charge layer is eliminated by distinguishing the space charge layer by making a top silicon layer sufficiently thin and, in addition, the termination of the electric force line from the gate to substrate charges is suppressed by making the top silicon layer and an insulating film between substrates sufficiently thicker. Since the top silicon layer is made sufficiently thinner in the SOI MOSFET, the top silicon layer underlying the gate is set to an inverted state in which the space charge area is distinguished over the whole area of the top silicon layer when the transistor is operated and the control of channel charges by means of a gate electric field can be made more efficient. Consequently, an improvement of characteristics, such as the suppression of short-channel effects, etc., can be expected from the transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI MOSFET.
In the above, the top silicon layer under the gate is made sufficiently thin to make the top silicon layer under the gate into an inverted state in which the space charge region disappears over the entire region during the operation of the transistor, and the channel charge is efficiently controlled by the gate electric field. As a result, improved transistor characteristics, especially low threshold voltage, low subthreshold coefficient, and high transconductance at high doping levels can be expected, and ultra-high density, high integration, and ultra-low power consumption are required. It is useful as a component of a next-generation semiconductor integrated circuit.

2. Description of the Related Art A conventional MOSFET-related technique is as follows. << Threshold voltage >> With the miniaturization of transistors, the doping level must be increased in accordance with the scaling rule, but as a result, the threshold voltage is also increased, which makes the transistor unsuitable for a low power consumption circuit. Also, the fluctuation of the threshold voltage with respect to the fluctuation of the gate length also has a narrow sense “short channel effect” that increases as the gate length decreases. << Sub-threshold coefficient and transconductance >> As transistor characteristics, low sub-threshold coefficient and high transconductance are desirable, but in general, these two properties are in a trade-off relationship, and if one property is improved, If so, the other characteristic tends to deteriorate.
For example, M using Schottky barrier for source and drain
The OSFET can reduce the subthreshold coefficient, but decreases the transconductance. Also SOIM
In the OSFET, the top silicon layer is completely depleted in all regions except the channel.
In the case of "ET", the subthreshold coefficient can be reduced to a value close to the theoretical limit, but high transconductance cannot be obtained. << Gate Configuration >> In order to efficiently control channel charges by the gate electric field, XMOS, SGT (Surro
Undoing Gate Transistor, cone-capture type MOSFET, DELTA (Fully)
DepletedLean channel SOI
Although various transistors such as MOSFETs have been proposed, each has a complicated structure, and accordingly, a high-level fabrication process is required, and it is difficult to say that it is suitable for high integration. << Control of Substrate Doping Level >> In a MOSFET, the fluctuation of the threshold voltage with respect to the fluctuation of the gate length is reduced by changing the doping level of the substrate immediately below the gate in the depth direction.

The problems to be solved by the present invention are summarized as follows. (1) A method for realizing a MOSFET having a low threshold voltage on a substrate having a high doping level. (2) A method for realizing a MOSFET having a low subthreshold coefficient and a high transconductance. (3) A method for realizing the above (1) and (2) by a simple structure and a simple process.

Means for Solving the Problems] fully inverted type according to the present invention in FIG. 1 (FI: F ully I nverted ) SOI
1 shows a conceptual diagram of a MOSFET. The lines of electric force from the gate are shown in the figure. In general, the lines of electric force from the gate terminate in any of (a) channel charges, (b) ionized impurities in the space charge layer, and (c) substrate charges. MOS in the first place
Since FET is a transistor that controls the channel charge by the gate electric field, the lines of electric force from the gate are
(A) It is desirable to terminate only at the channel charge.
For that purpose, the fully inverted type (Fully In
In a (verted) MOSFET, first, the top silicon layer is made sufficiently thin to eliminate the space charge layer, thereby eliminating the termination of the electric flux lines from the gate to (b) ionized impurities in the space charge layer. Top silicon layer,
By sufficiently increasing the thickness of the insulating film between the substrates, the termination of the lines of electric force from the gate to (c) substrate charge is suppressed. As a result, it is expected that a low threshold voltage, a low subthreshold coefficient, and a high transconductance can be simultaneously obtained in a substrate having a high doping level. SO
Considering quantitatively the conditions for the IMOSFET to function as a complete inversion type, the conditions of the top silicon layer for completely eliminating the space charge layer are as shown in FIG. On the assumption that all the top silicon layers are space charge layers, ionization impurities in the space charge layer (in FIG. 3, equation (3)
-1)) from the line of electric force from the gate (in FIG. 3, equation (3-
2)). Here, V is a voltage applied to the top silicon layer. The top silicon layer thickness t _Si under the condition where both are balanced is determined by SOI MOSFET
As a simple indicator of the conditions for performing the complete inversion type of
Fully inverted critical thickness ^{_{t c FI (FICT: F ully}} I
nverted C ritical T hicknes
s). The critical inversion critical film thickness t _c ^FI is shown in FIG.
It is obtained as in the equation (3-3). That is, as a first approximation, the top silicon layer thickness t _Si is equal to the perfect inversion critical thickness t t.
When it becomes thinner than _c ^FI, it can be said that the SOI MOSFET acts as a perfect inversion type. FIG. 2 shows a completely inverted SO.
The specific structure of the IMOSFET is shown. Both the source, drain and gate structures are extremely simple,
It can be made sufficiently by the basic process of a normal MOSFET.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Completely inverted SOI MOSFE shown in FIG.
About 3D device simulator "CADDE"
The characteristics obtained by performing a two-dimensional device simulation using "TH" are shown below. The parameters assumed in the simulation are as shown in FIG. That is, the doping concentration of the top silicon layer and the substrate is common, and the P type is 10 ¹⁷ (cm ⁻³ ) and 10 ^18.
(Cm ⁻³ ), the top silicon layer and the insulating film between the substrates are fixed to a sufficiently thick 10,000 (Å), and then the top silicon layer and the gate length are changed. The behavior of coefficient and transconductance was investigated. First, assuming the 1 [V] for the voltage V easy across the top silicon layer, an acceptor doping concentration _{N A} is ¹⁰ 18 ^(cm -3), ¹⁰
FIG. 3 shows the ^results obtained for the critical thickness t _C ^FI of the complete inversion in the SOI MOSFET in the case of ¹⁷ (cm ⁻³ ). 4 and 5 show a gate length _{L G} dependence of the threshold voltage _{V th} in the SOI MOSFET. Acceptor doping concentration _{N A} is ^{10 18 (cm -3), 10} 17
(Cm ⁻³ ) In each case, the top silicon layer thickness t
It can be seen that the threshold voltage decreases as _Si becomes thinner, and that the fluctuation of the threshold voltage with respect to the fluctuation of the gate length in the short channel region is also suppressed. These effects it is seen remarkably when the acceptor doping concentration _{N A} is ¹⁰ 18 ^{(cm -3),} in particular the top silicon layer thickness _{t Si}
Is smaller than the critical thickness t _c ^FI for perfect inversion, ie, S
This is noticeable when the OI MOSFET is fully inverted. 6 and 7 show the dependency of the threshold voltage _{Vth on} the top silicon film thickness t _Si in the SOI MOSFET. The top silicon layer thickness t _Si is the critical thickness t _{c for} perfect inversion.
^It can be seen that the dependence of the threshold voltage _{Vth on} the top silicon film thickness t _Si greatly increases when the thickness is smaller than that of ^FI , that is, when the SOI MOSFET becomes a completely inverted type. This long as you precise control over the top silicon film thickness t _Si, the threshold voltage V by a top silicon film thickness t _Si
th can be controlled, which means that the degree of freedom in transistor design is greatly increased. Showing the gate length _{L G} dependence of mutual conductance _gm of the SOI MOSFET having a different gate oxide thickness tBOX in FIG. The thinner the gate oxide film thickness t _{FOX, the} higher the transconductance _gm can be obtained. However, in order to eliminate the influence of the tunnel current of the gate oxide film, the following calculation is performed by fixing t _FOX to a slightly thicker 70 (Å). . 9 and FIG.
4 shows the dependence of the transconductance _{gm on} the top silicon film thickness t _Si in the OI MOSFET. Acceptor doping concentration _{N A} is ^{10 18 (cm -3), 10} 17
(Cm ⁻³ ) In each case, the top silicon layer thickness t
_{Although the} transconductance gm increases as the _Si becomes thinner, this tendency is particularly observed when the top silicon layer thickness t _Si becomes thinner than the perfect inversion critical thickness t _c ^FI , ie, SO
This is noticeable when the IMOSFET becomes fully inverted. FIGS. 11 and 12 show the top silicon film thickness t _Si of the subthreshold coefficient S in the SOI MOSFET.
Show dependencies. Acceptor doping concentration _{N A} is 10
^{18 (cm -3), 10 17} (cm -3) In either case, the sub-threshold coefficient S as the top silicon layer thickness _{t Si} is reduced to decrease, but in particular the top silicon layer thickness _{t Si} is completely reversed the critical film When the thickness becomes thinner than t _c ^FI , that is, when the SOI MOSFET becomes a fully inverted type, the subthreshold coefficient S decreases extremely sharply, and when the top silicon layer thickness t _Si is sufficiently thin, the theoretical limit value at room temperature is 60 (mV / m 2). dec). In order to clarify the physical picture of the behavior of the transistor characteristics, carrier charges in the top silicon layer are shown in FIGS. FIG.
3. FIG. 14 shows the distribution of carrier charges in the top silicon layer in the depth direction in the SOI MOSFET. When the thickness of the top silicon layer t _Si becomes smaller than the critical thickness for complete inversion t _c ^FI , that is, when the SOI MOSFET becomes a complete inversion type, the space charge layer completely disappears in all regions in the top silicon layer. You can see that. FIG.
5 the sum of the carrier charge induced in the top silicon layer in the SOI MOSFET into _{N S} i.e. 13,
The top silicon film thickness t _Si of the total charge amount obtained by integrating the carrier charge in the top silicon layer in the depth direction in FIG.
Show dependencies. Acceptor doping concentration _{N A} is 10
^{In each case of 18} (cm ⁻³ ) and 10 ¹⁷ (cm ⁻³ ), the top silicon layer thickness t _Si is equal to the perfect inversion critical thickness t _c.
^It can be seen that when the thickness becomes thinner than ^FI , that is, when the SOI MOSFET becomes a complete inversion type, the total electric charge induced by the gate electric field increases rapidly.

[Brief description of the drawings]

FIG. 1. Fully depleted type
MOSFET and Full Invert (Fully Invert)
ed) It is a conceptual diagram of MOSFET.

FIG. 2 shows the structure of a perfect inversion type MOSFET and parameters assumed in the embodiment.

FIG. 3 shows the critical thickness of the fully inverted layer (Fully Invctrt).
ed CriticalThickness) and the acceptor doping concentration N _A 10 ¹⁸ (cm
^-3 ) and N _A 10 ¹⁷ (cm ^-3 ) complete inversion type S
This is the critical thickness of the complete inversion in the OI MOSFET.

FIG. 4 shows an acceptor doping concentration N _A 10 ¹⁷ (c
m ⁻³ ) threshold voltage V in an SOI MOSFET
_th depends on the gate length LG.

FIG. 5 shows an acceptor doping concentration N _A 10 ¹⁸ (c
m ⁻³ ) threshold voltage V in an SOI MOSFET
a gate length _{L G} dependent _th.

FIG. 6 shows an acceptor doping concentration N _A 10 ¹⁷ (c
m ⁻³ ) threshold voltage V in an SOI MOSFET
_th is dependent on the top silicon film thickness t _Si .

FIG. 7 shows an acceptor doping concentration N _A 10 ¹⁸ (c
m ⁻³ ) threshold voltage V in an SOI MOSFET
_th is dependent on the top silicon film thickness t _Si .

FIG. 8 shows SOs with different gate oxide thicknesses t _BOX
It is gate length LG dependence of the transconductance _{gm in IMOSFET} .

FIG. 9 shows an acceptor doping concentration N _A 10 ¹⁷ (c
m ⁻³ ) is the dependence of the transconductance _{gm on} the top silicon film thickness t _Si in the SOI MOSFET.

FIG. 10: Acceptor doping concentration N _A 10
^{It is} a top silicon film thickness _tSi dependence of the transconductance gm in ¹⁸ (cm ^<-3> ) SOI MOSFET.

FIG. 11 shows an acceptor doping concentration N _A 10
¹⁷ _{shows the} dependence of the sub-threshold coefficient S on the top silicon film thickness t _Si in a ¹⁷ (cm ⁻³ ) SOI MOSFET.

FIG. 12 shows an acceptor doping concentration N _A 10
^{It is} a top silicon film thickness _tSi dependence of the sub-threshold coefficient S in an ¹⁸ (cm ⁻³ ) SOI MOSFET.

FIG. 13 shows an acceptor doping concentration N _A 10
^{18 is} a depth direction distribution of carrier charges in a top silicon layer in an ¹⁸ (cm ⁻³ ) SOI MOSFET.

FIG. 14 shows an acceptor doping concentration N _A 10
^{17 is} a depth direction distribution of carrier charges in a top silicon layer in a ¹⁷ (cm ⁻³ ) SOI MOSFET.

FIG. 15 shows an acceptor doping concentration N _A 10
¹⁸ (cm ⁻³ ) and the acceptor doping concentration N
A top silicon film thickness _{t Si} dependence of total _{N S} of the carrier charge induced in the top silicon layer in the SOI MOSFET of _A 10 ^{17 (cm -3).}

 ──────────────────────────────────────────────────続 き Continuation of the front page (71) Applicant 598057567 Miki Ikeda 450 Kawanishi, Yamakita-machi, Ashigara-kami-gun, Kanagawa Prefecture (72) Inventor Takuo Sugano 2-2-3 Sakura, Setagaya-ku, Tokyo (72) Inventor Toru Toritanibe Kokubunji, Tokyo 4-1 Nishimachi Keyakidai Danchi 34-205 (72) Inventor Tatsuro Hanashiri 30-1 Renjakucho, Kawagoe-shi, Saitama 509 Kawagoe Condominium 509 (72) Inventor Miki Ikeda 450 Kawanishi, Yamakita-machi, Ashigarugami-gun, Kanagawa Prefecture

Claims (5)

[Claims] 1. An SOI MOSFET having a top silicon layer that is extremely thin so that the top silicon layer under the gate is in an inverted state in which the space charge region has disappeared over the entire region during operation of the transistor. 2. The semiconductor device according to claim 1, wherein an insulating film layer having a thickness sufficiently large between the top silicon layer and the substrate silicon so that electric lines of force from the gate do not penetrate into the substrate silicon.
OIMOSFET. 3. The method according to claim 1, wherein the threshold voltage can be controlled by the thickness of the top silicon layer, and the threshold voltage is suppressed while keeping the doping level of the top silicon layer highly doped by making the top silicon layer extremely thin. SOI MOSFET. 4. The SOI MOSFET according to claim 1, wherein a low sub-threshold coefficient S (mV / dec) near a theoretical limit at room temperature is realized. 5. The SOI MOSFET according to claim 1, wherein a high transconductance gm can be realized.