JPH11284177A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH11284177A JPH11284177A JP10082148A JP8214898A JPH11284177A JP H11284177 A JPH11284177 A JP H11284177A JP 10082148 A JP10082148 A JP 10082148A JP 8214898 A JP8214898 A JP 8214898A JP H11284177 A JPH11284177 A JP H11284177A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- oxide film
- semiconductor device
- source region
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
ゲート酸化膜およびゲート上にこれらを覆うゲート保護
酸化膜を設け、Ｐ＋コンタクト領域及びＮ＋ソース領域
の導電層側の面は前記ゲート酸化膜およびゲートより上
方に位置するように設けることによってワイヤボンディ
ング時の衝撃に起因するトラップがゲート酸化膜に発生
するのを防止できるようにしたものである。The present invention relates to a semiconductor device,
A gate protection oxide film covering the gate oxide film and the gate is provided on the gate, and the surfaces of the P + contact region and the N + source region on the conductive layer side are provided above the gate oxide film and the gate. Is prevented from being generated in the gate oxide film due to the impact of the semiconductor device.
【０００２】[0002]
【従来の技術】従来の半導体装置としては、例えば、特
開平９−１０２６０７号に記載されたものが知られてい
る。この半導体装置においては、半導体基板上に形成さ
れたＮ＋ソース領域とゲートとゲート酸化膜とは同じ高
さになっている。また、従来の半導体装置のその他の例
としては、特開平６−２２４４３８号に記載されたもの
があり、この半導体装置においても、半導体基板上に形
成されたソース領域とゲートとゲート酸化膜は同じ高さ
になっている。2. Description of the Related Art As a conventional semiconductor device, for example, a device described in JP-A-9-102607 is known. In this semiconductor device, the N + source region, the gate, and the gate oxide film formed on the semiconductor substrate have the same height. Another example of a conventional semiconductor device is described in Japanese Patent Application Laid-Open No. 6-224438. Also in this semiconductor device, the source region, the gate and the gate oxide film formed on the semiconductor substrate are the same. Height.
【０００３】[0003]
【発明が解決しようとする課題】ところが、特開平９−
１０２６０７号の半導体装置においては、Ｎ＋ソース領
域とゲート上に形成されたアルミニウム層に金属ワイヤ
をボンディングする時に、衝撃がゲート酸化膜に直接伝
わり、ゲート酸化膜中にトラップを発生させるという問
題があった。また、特開平６−２２４４３８号に記載の
半導体装置においても、ボンディング時の衝撃を受けた
時に、ゲート酸化膜中にトラップが発生していた。SUMMARY OF THE INVENTION However, Japanese Patent Application Laid-Open No.
In the semiconductor device of No. 102607, when a metal wire is bonded to the N + source region and the aluminum layer formed on the gate, a shock is directly transmitted to the gate oxide film, and a trap is generated in the gate oxide film. Was. Also, in the semiconductor device described in JP-A-6-224438, traps are generated in the gate oxide film when subjected to an impact during bonding.
【０００４】本発明は、上記事情に鑑みてなされたもの
で、ワイヤボンディング時に受ける衝撃に起因するトラ
ップがゲート酸化膜に発生するのを防止できる半導体装
置を提供することにある。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device capable of preventing traps from being generated in a gate oxide film due to an impact received during wire bonding.
【０００５】[0005]
【課題を解決するための手段】請求項１記載の発明は、
トランジスタのドレインとしての働きをするＮ＋半導体
基板上に、Ｐ＋コンタクト領域、Ｎ＋ソース領域、ゲー
ト酸化膜、ゲートが設けられ、さらにこれらの上に金属
ワイヤと接続される導電層が設けられてなる半導体装置
において、前記ゲート酸化膜およびゲート上にこれらを
覆うゲート保護酸化膜が設けられ、かつ前記Ｐ＋コンタ
クト領域及びＮ＋ソース領域の前記導電層側の面は前記
ゲート酸化膜およびゲートより上方に位置するように設
けられていることを特徴とする半導体装置を上記課題の
解決とした。According to the first aspect of the present invention,
A semiconductor in which a P + contact region, an N + source region, a gate oxide film, and a gate are provided on an N + semiconductor substrate serving as a drain of a transistor, and a conductive layer connected to a metal wire is provided thereon. In the device, a gate protection oxide film is provided on the gate oxide film and the gate to cover the gate oxide film and the gate, and surfaces of the P + contact region and the N + source region on the conductive layer side are located above the gate oxide film and the gate. A semiconductor device characterized by being provided as described above has solved the above problem.
【０００６】請求項２記載の発明は、前記Ｐ＋コンタク
ト領域及びＮ＋ソース領域が、前記Ｎ＋半導体基板をな
す材料と同じ硬さの材料から構成されていることを特徴
とする請求項１記載の半導体装置を上記課題の解決手段
とした。請求項３記載の発明は、前記ゲート保護酸化膜
が前記Ｎ＋半導体基板をなす材料より柔らかい材料から
構成されていることを特徴とする請求項１または２記載
の半導体装置を上記課題の解決手段とした。According to a second aspect of the present invention, the P + contact region and the N + source region are made of a material having the same hardness as the material forming the N + semiconductor substrate. An apparatus is a means for solving the above-mentioned problem. According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the gate protection oxide film is made of a material softer than a material forming the N + semiconductor substrate. did.
【０００７】請求項４記載の発明は、前記Ｐ＋コンタク
ト領域及びＮ＋ソース領域がシリコンと同じ硬さの材料
から構成され、かつ、前記ゲート保護酸化膜がシリコン
より柔らかい材料から構成されていることを特徴とする
請求項３記載の半導体装置を上記課題の解決手段とし
た。According to a fourth aspect of the present invention, the P + contact region and the N + source region are made of a material having the same hardness as silicon, and the gate protection oxide film is made of a material softer than silicon. A semiconductor device according to a third aspect of the present invention is a means for solving the above problem.
【０００８】[0008]
【発明の実施の形態】以下、本発明の実施の形態を詳し
く説明する。かかる実施形態は、本発明の一態様を示す
ものであり、本発明を限定するものではなく、本発明の
範囲で任意に変更可能である。図１ないし図２は、本発
明の半導体装置の一実施形態を示す図である。なお、図
１は、後述するゲート酸化膜５、ゲート６、コンタクト
ホール９の位置関係の示す平面図であり、Ｐ＋コンタク
ト領域３、Ｎ＋ソース領域４、アルミニウム層１０、金
属ワイヤ１１は図示していない。実施形態の半導体装置
は、トランジスタのドレインとしての働きをするＮ＋半
導体基板１上に、Ｐ−ボディ２、Ｐ＋コンタクト領域
３、Ｎ＋ソース領域４が設けられている。Ｎ＋半導体基
板１をなす材料としては、シリコン等が用いられる。Ｐ
＋コンタクト領域３およびＮ＋ソース領域４をなす材料
としては、Ｎ＋半導体基板１と同じ硬さの材料が用いら
れ、Ｎ＋半導体基板１がシリコンからなる場合、シリコ
ンと同じ硬さの材料が用いられる。Embodiments of the present invention will be described below in detail. Such an embodiment shows one aspect of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the present invention. 1 and 2 are views showing one embodiment of the semiconductor device of the present invention. FIG. 1 is a plan view showing the positional relationship between a gate oxide film 5, a gate 6, and a contact hole 9, which will be described later. A P + contact region 3, an N + source region 4, an aluminum layer 10, and a metal wire 11 are shown. Absent. In the semiconductor device of the embodiment, a P− body 2, a P + contact region 3, and an N + source region 4 are provided on an N + semiconductor substrate 1 that functions as a drain of a transistor. As a material forming the N + semiconductor substrate 1, silicon or the like is used. P
As a material forming + contact region 3 and N + source region 4, a material having the same hardness as N + semiconductor substrate 1 is used. When N + semiconductor substrate 1 is made of silicon, a material having the same hardness as silicon is used.
【０００９】また、これらＰ＋コンタクト領域３、Ｎ＋
ソース領域４の下方にはゲート酸化膜５、ゲート６が形
成されている。さらに、これらゲート酸化膜５、ゲート
６の直上には、これらを覆うようにシリコンより柔らか
いゲート保護酸化膜７が配置されている。ゲート保護酸
化膜７をなす材料としては、上記Ｎ＋半導体基板１をな
す材料よりも柔らかい材料からなるものである。Ｎ＋半
導体基板１がシリコンからなる場合、ゲート保護酸化膜
７をなす材料としては、シリコンより柔らかい材料が用
いられる。これらゲート酸化膜５、ゲート６、ゲート保
護酸化膜７は、半導体基板１に溝を形成した後に形成さ
れたものである。In addition, these P + contact regions 3, N +
Below the source region 4, a gate oxide film 5 and a gate 6 are formed. Further, a gate protection oxide film 7 which is softer than silicon is disposed just above the gate oxide film 5 and the gate 6 so as to cover them. The material forming the gate protection oxide film 7 is a material softer than the material forming the N + semiconductor substrate 1. When the N + semiconductor substrate 1 is made of silicon, a material softer than silicon is used as a material forming the gate protection oxide film 7. The gate oxide film 5, the gate 6, and the gate protection oxide film 7 are formed after forming a groove in the semiconductor substrate 1.
【００１０】さらにＰ＋コンタクト領域３、Ｎ＋ソース
領域４、ゲート保護酸化膜７の上には、層間酸化膜８と
アルミニウム層（導電層）１０が形成されている。図中
符号９は、コンタクトホールである。Ｎ＋ソース領域４
は、アルミニウム層１０と直接、接していて、半導体装
置外部とつながっている。また、Ｎ＋半導体基板１は、
半導体チップの裏面を介して半導体装置外部とつながっ
ている。Further, an interlayer oxide film 8 and an aluminum layer (conductive layer) 10 are formed on P + contact region 3, N + source region 4, and gate protection oxide film 7. Reference numeral 9 in the figure is a contact hole. N + source region 4
Is in direct contact with the aluminum layer 10 and is connected to the outside of the semiconductor device. The N + semiconductor substrate 1
The semiconductor device is connected to the outside of the semiconductor device via the back surface of the semiconductor chip.
【００１１】そして、アルミニウム層１０に金属ワイヤ
１１がボンディングされる。なお、図１に示した金属ワ
イヤ１１の大きさは、実際の寸法比よりも小さく図示し
ている。金属ワイヤ１１の実際の寸法は、１つの半導体
素子の平面寸法が１０μｍぐらいに対して接続された金
属ワイヤ１１の底面部は１００μｍ程度である。Then, a metal wire 11 is bonded to the aluminum layer 10. The size of the metal wire 11 shown in FIG. 1 is smaller than the actual dimensional ratio. The actual size of the metal wire 11 is about 100 μm at the bottom portion of the connected metal wire 11 when the plane size of one semiconductor element is about 10 μm.
【００１２】この実施形態の半導体装置では、トランジ
スタのドレインとしての働きをするＮ＋半導体基板１、
Ｎ＋ソース領域４、Ｐ−ボディ２、ゲート酸化膜５、ゲ
ート６の構造を有し、ＭＯＳトランジスタとして機能す
る。In the semiconductor device of this embodiment, an N + semiconductor substrate 1 serving as a drain of a transistor,
It has a structure of an N + source region 4, a P- body 2, a gate oxide film 5, and a gate 6, and functions as a MOS transistor.
【００１３】実施形態の半導体装置によれば、＋コンタ
クト領域３及びＮ＋ソース領域４のアルミニウム層１０
側の面はゲート酸化膜５およびゲート６より上方に位置
するように設けられたことにより、金属ワイヤ１１をボ
ンディングする時の衝撃は、Ｐ＋コンタクト領域３およ
びＮ＋ソース領域４で受け止められる。一方、ゲート酸
化膜５上にこれを覆うゲート保護酸化膜７が設けられ、
かつ、ゲート保護酸化膜７が柔らかい材料から構成され
たことにより、ボンディング時の衝撃はゲート保護酸化
膜７にて緩和されゲート酸化膜５に直接伝わることがな
い。従って、実施形態の半導体装置によれば、ゲート酸
化膜５部にボンディング時の衝撃が直接伝わらないの
で、ボンディング時の衝撃を避けることができ、ボンデ
ィング時にゲート酸化膜に発生していたトラップの発生
を抑える事が出来る。According to the semiconductor device of the embodiment, the aluminum layer 10 of the + contact region 3 and the N + source region 4
Since the side surface is provided above gate oxide film 5 and gate 6, the shock at the time of bonding metal wire 11 is received by P + contact region 3 and N + source region 4. On the other hand, a gate protection oxide film 7 covering the gate oxide film 5 is provided,
In addition, since the gate protection oxide film 7 is made of a soft material, the shock at the time of bonding is reduced by the gate protection oxide film 7 and is not directly transmitted to the gate oxide film 5. Therefore, according to the semiconductor device of the embodiment, since the impact at the time of bonding is not directly transmitted to the gate oxide film 5, the impact at the time of bonding can be avoided, and the trap generated at the gate oxide film at the time of bonding can be generated. Can be suppressed.
【００１４】[0014]
【発明の効果】以上説明したように本発明の半導体装置
によれば、＋コンタクト領域及びＮ＋ソース領域の導電
層側の面はゲート酸化膜およびゲートより上方に位置す
るように設けられたことにより、金属ワイヤをボンディ
ングする時の衝撃は、Ｐ＋コンタクト領域およびＮ＋ソ
ース領域で受け止められる。一方、ゲート酸化膜上にこ
れを覆うゲート保護酸化膜が設けられたことにより、ボ
ンディング時の衝撃はゲート保護酸化膜にて緩和されゲ
ート酸化膜に直接伝わることがない。従って、実施形態
の半導体装置によれば、ゲート酸化膜部にボンディング
時の衝撃が直接伝わらないので、ボンディング時の衝撃
を避けることができ、ボンディング時にゲート酸化膜に
発生していたトラップの発生を抑える事が出来る。As described above, according to the semiconductor device of the present invention, the surface on the conductive layer side of the + contact region and the N + source region is provided so as to be located above the gate oxide film and the gate. The impact when bonding the metal wire is received by the P + contact region and the N + source region. On the other hand, since the gate protection oxide film is provided on the gate oxide film, the impact at the time of bonding is reduced by the gate protection oxide film and is not directly transmitted to the gate oxide film. Therefore, according to the semiconductor device of the embodiment, since the impact at the time of bonding is not directly transmitted to the gate oxide film portion, the impact at the time of bonding can be avoided, and the trap generated at the gate oxide film at the time of bonding can be prevented. Can be suppressed.
【図１】 本発明の実施形態の半導体装置のゲート酸化
膜、ゲート、コンタクトホールの位置関係を示す平面図
である。FIG. 1 is a plan view showing a positional relationship among a gate oxide film, a gate, and a contact hole of a semiconductor device according to an embodiment of the present invention.
【図２】 図１の半導体装置のＡ−Ａ線断面図である。FIG. 2 is a sectional view taken along line AA of the semiconductor device of FIG. 1;
１・・・Ｎ＋半導体基板、２・・・Ｐ−ボディ、３・・・Ｐ＋コ
ンタクト領域、４・・・Ｎ＋ソース領域、５・・・ゲート酸化
膜、６・・・ゲート、７・・・ゲート保護酸化膜、８・・・層間
酸化膜、１０・・・アルミニウム層（導電層）、１１・・・金
属ワイヤ。1 ... N + semiconductor substrate, 2 ... P-body, 3 ... P + contact region, 4 ... N + source region, 5 ... Gate oxide film, 6 ... Gate, 7 ... Gate protection oxide film, 8: interlayer oxide film, 10: aluminum layer (conductive layer), 11: metal wire.
【手続補正書】[Procedure amendment]
【提出日】平成１１年４月５日[Submission date] April 5, 1999
【手続補正１】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】特許請求の範囲[Correction target item name] Claims
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【特許請求の範囲】[Claims]
【手続補正２】[Procedure amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００５[Correction target item name] 0005
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【０００５】[0005]
【課題を解決するための手段】請求項１記載の発明は、
トランジスタのドレインとしての働きをするＮ＋半導体
基板上に、Ｐ＋コンタクト領域、Ｎ＋ソース領域、ゲー
ト酸化膜、ゲートが設けられ、さらにこれらの上に金属
ワイヤと接続される導電層が設けられてなる半導体装置
において、前記ゲート酸化膜およびゲート上にこれらを
覆うゲート保護酸化膜が設けられ、かつ前記Ｐ＋コンタ
クト領域及びＮ＋ソース領域の前記導電層側の面は前記
ゲート酸化膜およびゲートより上方に位置するように設
けられ、前記ゲート保護酸化膜上で、かつ該ゲート保護
酸化膜と前記導電層との間に層間酸化膜が設けられてい
ることを特徴とする半導体装置を上記課題の解決とし
た。According to the first aspect of the present invention,
A semiconductor in which a P + contact region, an N + source region, a gate oxide film, and a gate are provided on an N + semiconductor substrate serving as a drain of a transistor, and a conductive layer connected to a metal wire is provided thereon. In the device, a gate protection oxide film is provided on the gate oxide film and the gate to cover the gate oxide film and the gate, and surfaces of the P + contact region and the N + source region on the conductive layer side are located above the gate oxide film and the gate. Provided on the gate protection oxide film and the gate protection oxide film.
An interlayer oxide film is provided between the oxide film and the conductive layer.
The semiconductor device according to claim Rukoto was solving the problems.
【手続補正３】[Procedure amendment 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００６[Correction target item name] 0006
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【０００６】請求項２記載の発明は、前記Ｐ＋コンタク
ト領域及びＮ＋ソース領域が、前記Ｎ＋半導体基板をな
す材料と同じ硬さの材料から構成されていることを特徴
とする請求項１記載の半導体装置を上記課題の解決手段
とした。請求項３記載の発明は、前記ゲート保護酸化膜
が前記Ｎ＋半導体基板より柔らかいものであることを特
徴とする請求項１または２記載の半導体装置を上記課題
の解決手段とした。According to a second aspect of the present invention, the P + contact region and the N + source region are made of a material having the same hardness as the material forming the N + semiconductor substrate. An apparatus is a means for solving the above-mentioned problem. According to a third aspect of the present invention, there is provided a semiconductor device according to the first or second aspect, wherein the gate protection oxide film is softer than the N + semiconductor substrate.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００７[Correction target item name] 0007
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【０００７】請求項４記載の発明は、前記Ｐ＋コンタク
ト領域及びＮ＋ソース領域がシリコンと同じ硬さの材料
から構成され、かつ、前記ゲート保護酸化膜がシリコン
より柔らかいものであることを特徴とする請求項３記載
の半導体装置を上記課題の解決手段とした。According to a fourth aspect of the present invention, the P + contact region and the N + source region are made of a material having the same hardness as silicon, and the gate protection oxide film is made of silicon.
A semiconductor device according to claim 3 which is softer is a means for solving the above problem.
Claims (4)
するＮ＋半導体基板上に、Ｐ＋コンタクト領域、Ｎ＋ソ
ース領域、ゲート酸化膜、ゲートが設けられ、さらにこ
れらの上に金属ワイヤと接続される導電層が設けられて
なる半導体装置において、 前記ゲート酸化膜およびゲート上にこれらを覆うゲート
保護酸化膜が設けられ、前記Ｐ＋コンタクト領域及びＮ
＋ソース領域の前記導電層側の面は前記ゲート酸化膜お
よびゲートより上方に位置するように設けられているこ
とを特徴とする半導体装置。1. A P + contact region, an N + source region, a gate oxide film, and a gate are provided on an N + semiconductor substrate serving as a drain of a transistor, and a conductive layer connected to a metal wire is provided thereon. In the semiconductor device provided, a gate protection oxide film is provided on the gate oxide film and the gate to cover the gate oxide film and the gate.
A semiconductor device, wherein a surface of the + source region on the side of the conductive layer is provided above the gate oxide film and the gate.
領域が、前記Ｎ＋半導体基板をなす材料と同じ硬さの材
料から構成されていることを特徴とする請求項１記載の
半導体装置。2. The semiconductor device according to claim 1, wherein said P + contact region and N + source region are made of a material having the same hardness as a material forming said N + semiconductor substrate.
基板をなす材料より柔らかい材料から構成されているこ
とを特徴とする請求項１または２記載の半導体装置。3. The semiconductor device according to claim 1, wherein said gate protection oxide film is made of a material softer than a material forming said N + semiconductor substrate.
領域がシリコンと同じ硬さの材料から構成され、かつ、
前記ゲート保護酸化膜がシリコンより柔らかい材料から
構成されていることを特徴とする請求項３記載の半導体
装置。4. The P + contact region and the N + source region are made of a material having the same hardness as silicon, and
4. The semiconductor device according to claim 3, wherein said gate protection oxide film is made of a material softer than silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10082148A JPH11284177A (en) | 1998-03-27 | 1998-03-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10082148A JPH11284177A (en) | 1998-03-27 | 1998-03-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11284177A true JPH11284177A (en) | 1999-10-15 |
Family
ID=13766364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10082148A Pending JPH11284177A (en) | 1998-03-27 | 1998-03-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11284177A (en) |
-
1998
- 1998-03-27 JP JP10082148A patent/JPH11284177A/en active Pending
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