JPH04179256A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04179256A JPH04179256A JP30817490A JP30817490A JPH04179256A JP H04179256 A JPH04179256 A JP H04179256A JP 30817490 A JP30817490 A JP 30817490A JP 30817490 A JP30817490 A JP 30817490A JP H04179256 A JPH04179256 A JP H04179256A
- Authority
- JP
- Japan
- Prior art keywords
- mold
- resin
- power
- exterior
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 229920005989 resin Polymers 0.000 claims abstract description 17
- 239000011347 resin Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910000679 solder Inorganic materials 0.000 abstract description 6
- 239000003822 epoxy resin Substances 0.000 abstract description 4
- 229920000647 polyepoxide Polymers 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000005476 soldering Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 241000277269 Oncorhynchus masou Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 210000005069 ears Anatomy 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、基板にパワーミニモールドを表面実装した半
導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a power mini-mold is surface-mounted on a substrate.
第１１図はパワーミニモールドの斜視図である。 FIG. 11 is a perspective view of the power mini mold.
リード４ａ、４ｂ、４ａが互いに平行に配置されている
。Leads 4a, 4b, 4a are arranged parallel to each other.
トランジスタ及びダイオード等の素子が形成された半導
体チップ４Ｃの底面電極がリード４ｂ上にボンディング
されており、半導体チップ４Ｃの素子はリード４ａ、４
ａ とワイヤ４ｄ、４ｄを介して接続されている。そし
てこれらはエポキシ樹脂でモールドされており、直方体
状のモールド外装４ｅを形成している。The bottom electrode of the semiconductor chip 4C on which elements such as transistors and diodes are formed is bonded onto the leads 4b, and the elements of the semiconductor chip 4C are bonded to the leads 4a and 4.
a through wires 4d, 4d. These are molded with epoxy resin to form a rectangular parallelepiped mold exterior 4e.
以上の如く構成されたパワーミニモールドは、半導体チ
ップ４ｃの底面電極が大きく、これに対応させてリード
４ｂの面積を広くしており、半導体チップ４ｃからリー
ド４ｂに向けて効率良く放熱することができる、パワー
ミニモールドを基板に表面実装するときのはんだ付は面
積が広くなって基板に対する固着力が大きくなる等の特
長がある。In the power mini mold configured as described above, the bottom electrode of the semiconductor chip 4c is large, and the area of the leads 4b is correspondingly large, so that heat can be efficiently dissipated from the semiconductor chip 4c toward the leads 4b. When surface mounting the Power Mini Mold on a board, the soldering area has the advantage of increasing the adhesive strength to the board.
第１２図はパワーミニモールドを基板に実装した従来の
半導体装置を示す斜視図、第１３図は第１２図のＸ■−
ｘ■線線入大断面図第１４図は第１３図のＸＩＶ−×■
線線入大断面図ある。Fig. 12 is a perspective view showing a conventional semiconductor device in which a power mini mold is mounted on a board, and Fig. 13 is a
Figure 14 is a large cross-sectional view of the
There is a large cross-sectional view with lines included.
図中１は基板であり、基板１上に電極２が形成されてお
り、電極２の上にパワーミニモールド４のリード４ａ、
４ａ、４ｂがはんだ３付けされている。In the figure, 1 is a substrate, on which an electrode 2 is formed, and on top of the electrode 2 are leads 4a of a power mini mold 4,
4a and 4b are soldered 3.
そして全体がエポキシ系樹脂でコーティングされており
、装置外装５を形成している。The entire device is coated with epoxy resin to form the device exterior 5.
前述した半導体装置は使用環境の条件により、基板１が
反って第１４図に示した矢符のように装置外装５から外
側に向かって力が働く。モールド外装４ｅと装置外装５
とは材質が同一であり、接着性が良く、固着力が強いの
で１．装置り（装５に応力が働くと、これに応動してモ
ールド外装４ｅとリード４ｂとの接着面及びパワーミニ
モールド４と基板１とのはんだ付は面に力が働く。リー
ト４ ｂのはんだイづけ面積は広いのでパワーミニモー
ルド４と基板１とのはんだ付は而は固着力が大きく、歪
みはこれより固着力が小さいモールド外装４ｅとリート
４ｂとの接着面に集中する。その結果、接着面にクラッ
クが生じ、次にモールド外装４ｅ、半導体チップ４ｃ、
基板１間に応力が働き、一番弱い半導体ヂンブ４ｃが横
方向に破断する。In the above-described semiconductor device, the substrate 1 is warped depending on the usage environment conditions, and a force is exerted outward from the device exterior 5 as indicated by the arrow shown in FIG. Mold exterior 4e and device exterior 5
1. is made of the same material, has good adhesion, and has strong adhesion. When stress is applied to the device 5, force is applied to the bonding surface between the mold exterior 4e and the lead 4b and the soldering surface between the power mini mold 4 and the board 1.Soldering of the lead 4b Since the soldering area is large, the soldering force between the power mini mold 4 and the board 1 is large, and the distortion is concentrated on the bonding surface between the mold exterior 4e and the lead 4b, which has a smaller bonding force.As a result, Cracks occur on the adhesive surface, and then the mold exterior 4e, the semiconductor chip 4c,
Stress acts between the substrates 1, and the weakest semiconductor dimple 4c breaks in the lateral direction.
本発明は斯かる事情に鑑みなされたものであり、パワー
ミニモールドと装置の外装樹脂との間に緩衝層を形成す
ることにより外装樹脂からパワーミニモー／ｌ川に及ぶ
力を緩和した半導体装置を提供することをＬｌ的とする
。The present invention has been made in view of the above circumstances, and provides a semiconductor device in which the force exerted from the exterior resin to the power minimold is alleviated by forming a buffer layer between the power minimold and the exterior resin of the device. The purpose of Ll is to provide the following.
本発明に係る半導体装置は、基板に表面実装したパワー
ミニモールＩ・の表面に緩衝層を形成してその上に外装
が形成してあることを特徴とする。The semiconductor device according to the present invention is characterized in that a buffer layer is formed on the surface of a power mini-mall I. which is surface-mounted on a substrate, and an exterior is formed on the buffer layer.
本発明においては、」３導体装置の外装樹脂とパワーミ
ニモールドの外装樹脂との間に緩衝層が設けられており
、緩衝層ですべるので夕）装樹脂からパワーミニモール
ドに及ぶ力が緩和される。In the present invention, a buffer layer is provided between the exterior resin of the 3-conductor device and the exterior resin of the power mini mold, and since the buffer layer slides, the force exerted from the exterior resin on the power mini mold is alleviated. Ru.
以下、本発明をその実施例を示す図面に基づき具体的に
説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof.
第１図は本発明に係る半導体装置を示す斜視図、第２図
は第１図のＩＩ−ＩＩ線拡大断面図である。FIG. 1 is a perspective view showing a semiconductor device according to the present invention, and FIG. 2 is an enlarged sectional view taken along the line II--II in FIG.
図中１は基板であり、基板１−１−に電極２が形成され
ており、電極２の」二にパワーミニモールド４のリート
’４ａ、４ａ、４ｂがはんだ３付けされている。リーＦ
’４ａ、４ｂ、４ａが互いに平行に配置されている。Ｉ
・ランソスク及びグイオート等の素子が形成された゛１
三導体デツプ４ｃの底面電極かり−Ｆ４ｂＪ二にボンテ
ィソゲされており、半導体チップ４Ｃの素子はリード４
ａ、４ａ とりイヤ４ｄ、４ｄを介して接続されている
。In the figure, reference numeral 1 denotes a substrate, and an electrode 2 is formed on the substrate 1-1-, and leads 4a, 4a, and 4b of a power mini-mold 4 are soldered to the second side of the electrode 2. Lee F
'4a, 4b, and 4a are arranged parallel to each other. I
・Elements such as Lansosc and Guioto were formed゛1
The bottom electrode of the three-conductor depth 4c is bonded to F4bJ2, and the element of the semiconductor chip 4C is bonded to the lead 4.
a, 4a are connected via ears 4d, 4d.
そしてこれら（よエボキン樹脂でモールドされており、
直方体状のモールド外装４Ｃを形成している。And these (molded with Yo Evokin resin,
A rectangular parallelepiped mold exterior 4C is formed.
モールド外装４ｅの表面にはシリコン系樹脂からなる緩
衝層６が塗布されている。そして全体がエボキン系樹脂
でコーティングされており、装置外装５を形成している
。A buffer layer 6 made of silicone resin is applied to the surface of the mold exterior 4e. The entire device is coated with Evoquin resin to form the device exterior 5.
次に、本発明に係る半導体装置の製造方法について説明
する。Next, a method for manufacturing a semiconductor device according to the present invention will be explained.
第３図〜第７図は本発明に係る半導体装置の製造過程を
示す断面図、第８図、第９図、′ＰＪ１０図は夫／ン第
３図、第４図、第５図の平面図である。3 to 7 are cross-sectional views showing the manufacturing process of the semiconductor device according to the present invention, and FIGS. It is a diagram.
まず、Ｊ、９板１に、パワーミニモールド４を実装でき
るようにリード４ｂ及びリート４ａ、４ａの形状に合わ
ゼて電極２をバターニングする（第３図及び第８図）。First, the electrode 2 is patterned on the J9 board 1 to fit the shape of the lead 4b and the leads 4a, 4a so that the power mini mold 4 can be mounted (FIGS. 3 and 8).
次に、パワーミニモールド４のはんり付ケ部にり・）応
させて、はんだ粉、フラフクス、）８削等からなるはん
だペースト３を例えば印刷法等により電極２」二に付着
さ一ロる（第４図及び第９図）。Next, a solder paste 3 made of solder powder, fluff, etc. is applied to the electrode 2'' by a printing method or the like, corresponding to the soldering part of the power mini mold 4. (Figures 4 and 9).
そして、パワーミニモールド４を所定の位↑なに配置し
て加熱し、はんだペースト３中のはんだを再溶融して、
パワーミニモールド４を電極２−１−４こはんだ３付け
する（第５図及び第１０図）。Then, place the power mini mold 4 at a predetermined position and heat it to remelt the solder in the solder paste 3.
The power mini mold 4 is attached with the electrode 2-1-4 solder 3 (FIGS. 5 and 10).
次に、パワーミニモールド４のモールド外装４ｅに沿っ
てシリコン系樹脂を塗布し、緩衝層６を形成する（第６
図）。Next, silicone resin is applied along the mold exterior 4e of the power mini mold 4 to form the buffer layer 6 (sixth
figure).
最後に、全体をエボキン系樹脂でコーティングし、装置
外装５を形成する（第７図）。Finally, the entire device is coated with Evoquin resin to form the device exterior 5 (FIG. 7).
以上の如くにして本発明に係る半導体装置を製造するこ
とができる。そしてこの装置を使用して装置外装５に応
力が生した場合、緩衝層６にてすべるので、装置外装５
からパワーミニモールド４に及ぶ力が緩和される。The semiconductor device according to the present invention can be manufactured in the manner described above. When stress is generated in the device exterior 5 using this device, the device exterior 5 slips on the buffer layer 6.
The force exerted on the power mini mold 4 is alleviated.
なお、本発明の実施例では緩衝層としてソリコン樹脂を
使用する場合につき説明しているが、何らこれに限定さ
れるものではなく、装置外装樹脂及びモールド外装樹脂
に対する接着性が良好であり、これらの間に働く力を緩
和する樹脂であわばよい。In the examples of the present invention, a case is explained in which a solicon resin is used as a buffer layer, but the invention is not limited to this in any way. It is best to use a resin that relieves the force exerted during the process.
［発明の効果］
以上の如く本発明に係る半導体装置においては、パワー
ミニモールドと装置の外装樹脂との間に緩衝層を形成す
ることにより１．外装樹脂からパワーミニモールドに及
ふ力が緩和され、パワーミニモール（−の半導体装ノブ
が破断することか防止されて信頼性が高くなる等、本発
明は優れた効果を奏するものである。[Effects of the Invention] As described above, in the semiconductor device according to the present invention, by forming a buffer layer between the power mini mold and the exterior resin of the device, 1. The present invention has excellent effects, such as reducing the force exerted on the power mini-mold from the exterior resin, preventing the power mini-mold semiconductor knob from breaking, and increasing reliability.
第１図は本発明に係る半導体装置を示す斜視図、第２図
は第１図の■ ■線拡大断面図、第３図〜第７図は本発
明に係る半導体装置の製造過程を示す断面図、第８図は
第３同の千面し１、第９図は第４図の平面図、第１０図
は第５図の平面図、第１１図はパワーミニモールドの斜
視図、第１２図は従来の゛しＩ体装置を示す斜視図、第
１３図は第１２図のＸＩ［ｉ−Ｘ Ｉｎ線世人断面図、
第１４閲は第１２図の）訊ｌ−×■線拡人１す１面図（
＆＋る。
’ ””ｒｓ 払ｊ２ ・電極 ４ パワ−ミニモー
ル［５・・・装置外装 ６・・緩衝層
なお、図中、同一符号は同一、又は相当部分を示す。
代理人 大 岩 増 雄第 ２
図
第 ３ 図
第 ４ 図
第 ５ 図
］
第 ６ 図
第 ７ 図
第 ８ 図
第 ９ 図
第 １１ 図
第 １２ 図
第 １３ 図
第 １４ 図
平成 年 月 日FIG. 1 is a perspective view showing a semiconductor device according to the present invention, FIG. 2 is an enlarged sectional view taken along line 1 in FIG. 1, and FIGS. Fig. 8 is a plan view of Fig. 4, Fig. 8 is a plan view of Fig. 3, Fig. 10 is a plan view of Fig. 5, Fig. 11 is a perspective view of the power mini mold, Fig. 12 The figure is a perspective view showing a conventional I-body device, and FIG. 13 is a sectional view taken along the
The 14th review is the one-page view of Figure 12)
&＋ru. ``''rs pay j2 Electrode 4 Power Mini Mall [5... Apparatus exterior 6... Buffer layer Note that in the drawings, the same reference numerals indicate the same or equivalent parts. Agent Masu Oiwa 2nd
Fig. 3 Fig. 4 Fig. 5] Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 11 Fig. 12 Fig. 13 Fig. 14 Fig. 14
Claims (1)
コーティングした半導体装置において、前記樹脂と前記
パワーミニモールドとの間に、前記樹脂から前記パワー
ミニモールドに及ぶ力を緩和する緩衝層を形成してある
ことを特徴とする半導体装置。(1) In a semiconductor device in which a power mini-mold surface-mounted on a substrate is coated with resin, a buffer layer is formed between the resin and the power mini-mold to relieve the force exerted from the resin to the power mini-mold. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30817490A JPH04179256A (en) | 1990-11-13 | 1990-11-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30817490A JPH04179256A (en) | 1990-11-13 | 1990-11-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04179256A true JPH04179256A (en) | 1992-06-25 |
Family
ID=17977798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30817490A Pending JPH04179256A (en) | 1990-11-13 | 1990-11-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04179256A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5442521A (en) * | 1991-09-19 | 1995-08-15 | Nokia Mobile Phones Ltd. | Circuit board assembly |
| EP3451374A1 (en) * | 2017-09-01 | 2019-03-06 | TDK-Micronas GmbH | Semiconductor device package |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6442356U (en) * | 1987-09-09 | 1989-03-14 | ||
| JPH028077B2 (en) * | 1980-04-01 | 1990-02-22 | Nordiskafilt Ab | |
| JPH02241041A (en) * | 1989-03-15 | 1990-09-25 | Matsushita Electric Works Ltd | Mounting method of semiconductor element |
-
1990
- 1990-11-13 JP JP30817490A patent/JPH04179256A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH028077B2 (en) * | 1980-04-01 | 1990-02-22 | Nordiskafilt Ab | |
| JPS6442356U (en) * | 1987-09-09 | 1989-03-14 | ||
| JPH02241041A (en) * | 1989-03-15 | 1990-09-25 | Matsushita Electric Works Ltd | Mounting method of semiconductor element |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5442521A (en) * | 1991-09-19 | 1995-08-15 | Nokia Mobile Phones Ltd. | Circuit board assembly |
| EP3451374A1 (en) * | 2017-09-01 | 2019-03-06 | TDK-Micronas GmbH | Semiconductor device package |
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