JPH11282764A - Memory error point cut-off circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a fault of CPU operation at the time of a memory error. SOLUTION: The device is provided with second circuits 17, 18 and 19 for outputting a first signal when there is an error in a cache memory 14. Third circuits 21, 22 and 23, which compare an address with an error and a value of an address bus to each other and output a second signal when they match, are provided. There are provided switches 4, 5, 9 and 25, which switch so that a main memory is accessed when an address with an error of the cache memory 14 is accessed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit when a memory error occurs.

[0002]

2. Description of the Related Art A cache memory is one form of a storage element (hereinafter referred to as a memory). A cache memory is a memory that has a hierarchical structure and realizes high-speed access. That is, a small capacity between a large-capacity, low-speed main memory and a central processing unit (hereinafter referred to as a CPU).
A high-speed cache memory is provided, and data accessed by the CPU is temporarily stored in the cache memory. If the CPU is designed so that it can be accessed from the cache memory with a high probability, it is equivalent to the CPU accessing the main memory at a speed almost equal to the access time of the cache memory. Here, in general, in the conventional cache memory control circuit, when an error occurs in the cache memory, there is no mechanism for immediately separating the error portion, and the software is notified of the error as a parity error.

[0003]

SUMMARY OF THE INVENTION However, CPU
Does not immediately isolate the error location in the cache memory, and the software may attempt to handle the error, causing a more serious failure for the CPU such as an instruction fetch stack or a program runaway. The same applies to the case where there is a general memory error. Therefore, an object of the present invention is to prevent a failure of the CPU operation at the time of a memory error.

[0004]

A first circuit for outputting a first signal when there is an error in a first memory is provided. A second circuit is provided for comparing an address having an error with a value on an address bus and outputting a second signal when the values match. A switch is provided for switching to access the second memory when an error occurs in the address of the first memory based on the first and second signals.

[0005]

FIG. 1 is a diagram showing an embodiment of the present invention. 1 is a control bus which is a write signal or a read signal of the CPU, 2 is an access receiving circuit for processing a signal of the control bus 1, 3 is a cache memory start signal output from the access receiving circuit 2, and 4 and 5 are gates. . Reference numeral 6 denotes a cache memory access control circuit for outputting a cache memory access control signal 7, and 8 denotes an access reception circuit 2.
A main memory start signal output from the
0 is a main memory access control circuit that outputs a main memory control signal 11.

[0006] 12 is an address bus, 14 is a cache memory, 15 is an address decoder, 16 is a data bus, 1
Reference numeral 7 denotes a parity check circuit for checking the parity of output data from the cache memory 14. Reference numeral 18 denotes a write control circuit for writing a parity error signal output from the parity check circuit 17 into the error flag register 19, and reference numeral 20 denotes a parity error occurrence notification signal output from the error flag register 19. 21 is an address bus 1
2 is an address write circuit which inputs the parity error notification signal 20 and writes an address to the index register 22, and 23 is a comparison circuit which compares the value of the index register 22 with the value of the address bus 12. Reference numeral 24 denotes an index match notification signal output from the comparison circuit 23, reference numeral 25 denotes a gate, and reference numeral 26 denotes a control signal for the buffer 27.

Next, the configuration of an embodiment will be described.
The control bus 1 is input to the access receiving circuit 2. The output cache memory start signal 3 of the access receiving circuit 2 is input to one of the AND gates 4 and 5. The output of the AND gate 4 is input to the cache memory access control circuit 6. The output cache memory control signal 7 of the cache memory access control circuit 6 and the address bus 12 are input to the cache memory 14. The address bus 12 is input to an address decoder 15, and the output of the address decoder 15 is input to a cache memory 14.

The data bus 16 to which the output of the cache memory 14 is connected is input to a parity check circuit 17. The output of the parity check circuit 17 is input to the write control circuit 18. The output of the write control circuit 18 is input to the error flag register 19. Parity error occurrence notification signal 20 output from error flag register 19
Is input to one of the address write circuit 21 and the AND gate 25. The address bus 12 is also input to the address write circuit 21. The output of the address write circuit 21 is input to the index register 22, and the output of the index register 22 and the address bus 12 are input to the comparison circuit 23. The output of the index register 22 is input to the buffer 27, and the output of the buffer 27 is connected to the data bus 16. Further, the control signal 2 of the buffer 27
As 6, the output of the access receiving circuit 2 is input.

The output index match notification signal 24 of the comparison circuit 23 is input to the other of the AND gate 25. The output of the AND gate 25 is connected to the other negative logic input of the AND gate 4 and is input to the other end of the AND gate 5.

An output main memory start signal 8 of the access receiving circuit 2 is input to one of the OR gates 9 and
The output of the AND gate 5 is input. The output of the OR gate 9 is input to the main memory access control circuit 10, and the output of the main memory control circuit 10 becomes the main memory control signal 11.

Next, the operation will be described with reference to FIG. First, a normal operation in which a parity error has not occurred in the cache memory 14 will be described. The access receiving circuit 2 recognizes the access from the control bus 1 to the memory, and outputs the cache memory start signal 3 when judging the access to the cache memory 14 and outputs the main memory start signal 8 when judging the access to the main memory (not shown). I do.

The main memory access control circuit 10 outputs a main memory control signal 11 based on the main memory start signal 8.

The cache memory start signal 3 is notified to the cache memory access control circuit 6 in the case of normal access. Thereafter, the cache memory access control circuit 6 activates the cache memory control signal 7, and the cache memory 14 stores the address bus 12 and the address decoder 1
5, the data is output to the data bus 16.

Next, a case where an error occurs in the cache memory 14 will be described. The output of the cache memory 14 is output to the data bus 16, and this data is checked by the parity check circuit 17. The parity check circuit 17 performs a parity check on the output data every time the cache memory 14 is accessed, and if there is an error, the write control circuit 18 stores the error in the error flag register 19.

The address write circuit 21 writes the value of the address bus 12 to the index register 22 when the parity error occurrence notification signal 20 is received. The comparison circuit 23 compares the value of the index register 22 with the value of the address bus 12 and outputs an index match notification signal 24 when they match.

The cache memory access control circuit 6 and the main memory access control circuit 10 can know that an error has occurred in the cache memory 14 from the parity error occurrence notification signal 20 and the index match notification signal 24. Further, a parity error occurrence notification signal 2
0 and the index match notification signal 24
5 and 9, the CPU (not shown)
When the error location 4 is accessed, the cache memory start signal 3 is switched to the main memory control signal. That is, the location where the error has occurred is separated from the cache memory 14. And to the place where the error is occurring,
A main memory (not shown) is accessed.
The memory error detection unit can be performed for each address of the cache memory 14.

The output of the index register 22 is:
The parity error occurrence notification signal 20 is connected to the data bus 16 through a buffer 27. Further, the buffer 27 receives the buffer control signal 2 from the access receiving circuit 2.
7, the location of the error in the cache memory 14 can be known later.

As described above, in one embodiment, since an error location in the cache memory is immediately separated, a serious obstacle to the CPU such as an instruction fetch stack or a program runaway can be avoided.

The cache memory 14 is a general memory, and a main memory (not shown) is backed up.
If it is a memory, even if an error occurs in a general memory, the memory can be switched to a backup memory. That is, CPU
In a system that has a memory, even if an error occurs in the memory, the CPU can avoid a serious obstacle such as runaway,
Normal operation can be continued.

[0020]

As described above, it is possible to prevent a failure of the CPU operation at the time of a memory error. Further, since the buffer is provided, the address of the place where an error has occurred can be known, which is useful for trouble search.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment.

[Explanation of symbols]

 2 access reception circuit 6 cache memory access control circuit 10 main memory access control circuit 14 cache memory 15 address decoder 17 parity check circuit 18 write control circuit 19 error flag register 21 address write circuit 22 index Register 23: Comparison circuit 27: Buffer

Claims (2)

[Claims] 1. A circuit in which a central processing unit accesses a first memory and switches access to an address having an error in the first memory to a second memory, wherein the first memory has an error. A first circuit that outputs a first signal, a second circuit that compares the address with the error and the value of the address bus, and outputs a second signal when they match, a first circuit that outputs the first signal; A switch for switching to access a second memory when an address of the first memory having an error is accessed based on the signal of (a). 2. A buffer according to claim 1, wherein an output from said circuit is used as a control signal, and a buffer is provided for outputting said address having said error and said first signal to a data bus.
The described memory error location isolation circuit.