JP3500561B2 - Shared data buffer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared data buffer, and more particularly, to a shared data buffer for buffering data in an inter-node connection device that interconnects a plurality of nodes. 2. Description of the Related Art Generally, a super computer is defined as one node, and a plurality of nodes may be mutually connected to form a cluster system. In this system, an inter-node connection device is used to perform communication between nodes and transfer a large amount of data. In the inter-node connection device, when there is no input data buffer at a cross point, data of a plurality of destinations is buffered in one input data buffer. That is, as shown in FIG. 2, an inter-node connecting device 100 is provided corresponding to the data transmitting nodes N2 and N3 and the data receiving nodes N0 and N1, and transfer is performed via the inter-node connecting device 100. Data is exchanged. In FIG. 1, transfer data and control codes transmitted from data transmitting nodes N2 and N3 are transmitted to an inter-node connecting device 100. Node connection device 1
Reference numeral 00 denotes an input data buffer unit N21 provided corresponding to the node N2 for buffering transfer data from the node N2, and a node N3 provided corresponding to the node N3.
And an input data buffer unit N31 for buffering transfer data from the CPU. The inter-node connecting device 100 is provided corresponding to the data receiving side node N0, and is provided with a buffer unit N21.
Output data selection circuit N01 that selects the output of buffer unit N31 and the output of buffer unit N31 and outputs the same to node N0 as transfer data.
And an output data selection circuit N11 provided corresponding to the data receiving node N1 for selecting an output of the buffer unit N21 and an output of the buffer unit N31 and outputting the selected data as transfer data to the node N1. It is configured to include arbitration circuits N02 and N12 for arbitrating data transfer requests from the buffer units N21 and N31. In the conventional system shown in FIG. 1, when a failure occurs in one of the data receiving nodes, the data receiving node is disconnected from the system, repaired, and then re-installed, the normally operating data is restored. It is necessary to stop the operation of the transmitting node, the inter-node connecting device, and other data receiving nodes, and empty the input data buffer unit. Therefore, in this system, there is a problem that the performance of the entire system is greatly reduced even if a failure occurs in one of the data receiving nodes which is a part of the system. Further, an internal configuration of the input data buffer section in FIG. 2 will be described with reference to FIG. In FIG. 1, an input control code register 2 is a register for storing a control code output from a data transmitting node.
The input data register 3 is a register for storing transfer data output from the data transmitting node. The input data valid register 1 is a register indicating whether the contents of the input control code register 2 and the contents of the input data register 3 are valid or invalid. The RAM 7 is a RAM for storing transfer data such as control codes output from the data transmitting node and stored in the input control code register 2 and the input data register 3. The output control code register 5 is R
This is a register for storing the control code read from AM7. The output data register 6 is a register for storing data read from the RAM 7. Output data Vali
The d register 4 is a register indicating whether the contents of the output control code register 5 and the contents of the output data register 6 are valid or invalid. Hereinafter, a case of a two-node switching system will be described as an example. In this case, since there are two receiving nodes, the control code is 4 bits. From the left, the contents are a data start line bit for the receiving node N0, a data end line bit for the receiving node N0, a data start line bit for the receiving node N1, and a data end line bit for the receiving node N1. The start line bit and the end line bit are required because the transfer data length is variable. The AND circuits 8 to 11 are circuits that output a transfer request to the arbitration circuit N02 or N12 when the control code stored in the output control code register 5 is valid. The data transfer flag 14 for the node N0 is a flag indicating that the logical product circuit 12 and the OR circuit 16 are performing data transfer from the start line to the end line of the data for the node N0, that is, the data transfer to the node N0. The data transfer flag 15 for the node N1 is a flag indicating that the logical product circuit 13 and the logical sum circuit 17 indicate from the start line detection to the end line detection of the data for the node N1, that is, the data transfer for the node N1 is being performed. The AND circuits 18 and 19 and the OR circuit 20
This circuit generates a read strobe signal of the RAM 7, a set signal of the output data Valid register 4, and a strobe signal of the read pointer register 25 from the output of the comparison circuit 24, the output of the output data Valid register 4, and the output of the OR circuit 23. Inverter circuit 2
Reference numerals 9 and 30 denote circuits for inverting the node N0 failure notification signal and the node N1 failure notification signal, respectively. Selection circuits 21 and 2
A selection circuit 2 switches between a transfer permission signal (read strobe of the RAM 7) during normal operation and a transfer permission signal (read strobe of the RAM 7) at the time of a node failure by a node failure notification signal. Read pointer register (RP)
Reference numeral 25 denotes a register indicating a read address of the RAM 7. The write pointer register 26 (WP) is a register indicating a write address of the RAM 7. The comparison circuit 24 is a circuit that compares the address indicated by the read pointer register 25 with the address indicated by the write pointer register 26. The adders 27 and 28 are circuits for updating the values of the read pointer register 25 and the write pointer register 26, respectively. In such a configuration, control of writing data to the RAM 7 will be described first. Control code, transfer data, and input data V output from the data transmitting node
The valid signal is output to the input control code register 2, the input data register 3, and the input data Valid register 1, respectively. The write strobe of the RAM is asserted by the output of the input data valid register 1, the value of the write pointer register 26 is updated by the adder circuit 28, and the input control code register 2 and the input code register 3 are updated.
Is stored in the RAM 7. Next, control of reading data from the RAM 7 will be described. The value of the write pointer register 26 and the value of the read pointer register 25 are compared by the comparison circuit 24 to determine the presence or absence of unread data in the RAM 7. RAM
7 are read out in the following three cases. That is, if there is unread data as a result of the comparison in the comparison circuit 24 and the output data Valid register 4 indicates that the output control code register 5 and the output data register 6 are invalid, the result of the comparison in the comparison circuit 24 is unread. When the transfer data is present and the output data valid register 4 is valid, and the transfer permission signal is output from the arbitration circuit in the normal operation state, the comparison result in the comparison circuit 24 indicates that there is unread data. This shows that the Valid register 4 is valid, and the transfer destination node failure notification signal is asserted. When data is read from the RAM 7, the set signals of the output data Valid register 4, the strobe signal of the read pointer register 25, and the read strobe signal of the RAM 7 are asserted by the AND circuits 18, 19 and the OR circuit 20. You. Next, control when a failure occurs in one of the receiving nodes will be described. Here, for simplicity, it is assumed that a failure has occurred in the node N0. The failure notification signal of the node N0 is asserted, and the selection circuit 21
Is switched, and thereafter, when the data destined for the node N0 is read out to the output control code register 5 and the output data register 6, the data is sequentially read from the RAM 7 irrespective of the transfer permission signal,
The contents of the output control code register 5 and the output data register 6 are overwritten and discarded. In this way, it is possible to prevent the data destined for the node N1 in the RAM 7 from becoming unreadable. Next, control in the case where the node N0 recovers and is incorporated into the system again will be described. There is a possibility that invalid data destined to be discarded and transferred to the node during the failure of the node N0 should remain in the RAM 7.
Therefore, the transfer from the transmitting node is stopped, and after the unread data is exhausted from the RAM 7, the node N0 fault notification signal is negated, and the selection circuit 21 is switched to select the transfer permission signal in the normal operation. After that, the restored node N0 is reassembled, and the data transfer from the transmitting node is restarted. [0015] In the above-mentioned conventional system, when one of the data receiving nodes fails and is separated from the system and re-installed after repair,
It is necessary to stop the operation of the data transmitting node, the inter-node connecting device, and the other data receiving nodes that are operating normally, and empty the input data buffer. This method has the disadvantage that the performance of the entire system is greatly reduced even if a failure occurs in one of the data receiving nodes which is a part of the system. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a system in which a failure occurs in one node which is a part of the system and the system is re-installed after the restoration of the node. An object of the present invention is to provide a shared data buffer that can reduce the overall effect. A shared data buffer according to the present invention is provided corresponding to each node as a computer, and determines whether or not the corresponding node is incorporated in the system and can operate normally. A node configuration register for holding information indicating the input data, an input data field for storing data output from the node ,
Data field provided in the data field.
Information that indicates whether the data stored in the
The input configuration field to be retained and the input data
A method to retrieve and store the data stored in the field
Memory and the data stored in the memory
The output data field to be stored and the output data field.
Field and stored in the output data field.
An output that holds information indicating whether the data
And power configuration fields, the input configuration fields the node configuration register corresponding to the input data field data when the node corresponding to the register failure is stored when the identification information indicates that the ready to operate normally And control means for making the state invalid. By doing so, when a failure occurs in one node that is a part of the system and the node recovers after disconnection from the system, the node is re-entered without stopping the operation of the other nodes. It can be incorporated. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a shared data buffer according to the present invention. In the figure,
3 are denoted by the same reference numerals, and detailed description of those portions will be omitted. The difference between the shared data buffer shown in FIG. 3 and that shown in FIG. 3 is that the node configuration registers 33 and 34 indicate whether each node is incorporated in the system and is in a state in which it can operate normally. AND circuits 35 and 36 for performing an AND operation with the corresponding node failure notification signal, a node configuration field 37 of the data buffer input control code register, a node configuration field 38 of the data buffer output control code register, and the RAM 7 are provided. In that a node configuration field (not shown) provided and AND circuits 31 and 32 for performing a logical product of the node configuration field 38 of the data buffer output control code register and the corresponding node failure notification signal are added. is there. That is, the present system solves the drawbacks of the conventional technology as described below without significantly increasing the hardware in the conventional system (FIG. 3). In this configuration, when a failure occurs at the node N0, a node N0 failure notification signal is asserted, and the input control is performed by the AND circuit 35 (or the AND circuit 36 when a failure occurs at the node N1). The node N0 configuration field 37 provided in the code register 2 is invalidated and stored in the RAM 7. The node N0 configuration register 33 indicates that the node N0 has been disconnected from the system, and the data transferred from the transmitting node thereafter is stored in the RAM 7 with the node N0 configuration field 37 being invalidated. When the node N0 fault notification signal is asserted, the selection circuit 21 is switched, and data destined for the node N0 is read out to the output control code register 5 and the output data register 6 in the same manner as in the prior art. Then, the data is sequentially read from the RAM 7 regardless of the transfer permission signal, and the contents of the output control code register 5 and the output data register 6 are overwritten and discarded. At this time,
The transfer data to the node N1 is transferred normally. Next, control in the case where the node N0 recovers and is incorporated into the system again will be described. In the RAM 7, there is a possibility that invalid data destined for the node N0 to be discarded and transferred during the node N0 failure may remain.
However, these data are discarded when read into the output control code register 5 and the output data register 6 because the node N0 configuration field 37 is invalid. That is, the data is read out to the RAM 7 and overwritten regardless of the transfer permission signal. Therefore, after restoration of the node N0, the node N0 failure notification signal can be negated without worrying about the timing. After that, when the restored node N0 is re-installed, the node N0 configuration register 33 is made valid. By doing so, the data destined for the node N0 transferred from the transmitting node thereafter is written into the RAM 7 with the node N0 configuration field 37 being valid, and is normally handled without being discarded. As described above, according to the present invention, information is provided which is provided for each node and indicates whether or not the corresponding node is in a state where it can operate normally. If it indicates that it is operational,
When a failure occurs in a corresponding node, a configuration field corresponding to a data field in which data is stored is invalidated, so that one node that is a part of the system fails and is separated from the system. After restoration, re-installation can be performed without stopping operations of other nodes and the like, and the effect on the entire system can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an internal configuration of a shared data buffer according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of a computer system using a general shared data buffer. FIG. 3 is a block diagram showing an internal configuration of a shared data buffer in FIG. 2; [Description of Signs] 1 Input data Valid register 2 Input control code register 3 Input data register 4 Output data Valid register 5 Output control code register 6 Output data register 7 RAM 14, 15 Data transfer flags 21, 22 Selection circuits 33, 34 Config registers 37, 38 Config fields N0-N3 nodes

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 11/16-11/20 G06F 12/08 G06F 13/00 G06F 15/16-15/177 JSTPLUS file (JOIS)

Claims (1)

(57) [Claim 1] A node provided corresponding to each node as a computer and holding information indicating whether the corresponding node is incorporated in the system and is in a state where it can operate normally. A configuration register, an input data field for storing data output from the node, and the input data field.
Data field provided in the data field.
Information that indicates whether the data stored in the
The input configuration field to be retained and the input data
A method to retrieve and store the data stored in the field
Memory and the data stored in the memory
The output data field to be stored and the output data field.
Field and stored in the output data field.
An output that holds information indicating whether the data
And power configuration fields, the input configuration fields the node configuration register corresponding to the input data field data when the node corresponding to the register failure is stored when the identification information indicates that the ready to operate normally A shared data buffer, comprising: control means for invalidating the shared data buffer.