JPH11282701A - Ecc system for generating crc syndrome to random data in computer storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid a waiting time that is related to access to a data buffer which is for nonrandomizing data before generating a cyclic redundancy check(CRC) syndrome by performing CRC check of randomized data. SOLUTION: Randomized data is subjected to CRC check. In this error correction processor, an error checking and correction(ECC) decoder uses an ECC redundancy signal and corrects an error in the randomized data. A syndrome generator 17 responds to the randomized data and generates a verification syndrome. A correction verifier 19 compares the verification syndrome with prescribed value and verifies the effectiveness and completeness of correction to the randomized data. A nonrandomizer nonrandomizes the randomized data after the verifier 19 shows that correction of the randomized data is effective and complete.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction system for computer storage, and more particularly, to a cyclic redundancy check (C) before data is randomized during a write operation.
(RC) An efficient method and apparatus for proving the validity and completeness of correction for multidimensional codes, such as product codes, by performing a CRC on random data when symbols are generated.

[0002]

2. Description of the Related Art In computer storage devices (magnetic disk drives and optical disk drives), the bandwidth of the recording channel is limited as well as the signal power. To achieve performance gains, various coding techniques are used to increase the effective signal-to-noise ratio (SNR) by increasing the system's immunity to noise. Therefore, the storage capacity can be increased by increasing the storage density while maintaining an arbitrary low bit error rate.

At present, there are generally two types of codes used in recording apparatuses. A channel code and an error correction code (ECC). Channel codes are for noise caused by certain characteristics of the recording channel. For example, run-length limited (RL
L) codes are channel codes designed to attenuate noise to intersymbol interference by limiting the minimum spacing between pulses representing data symbols in an analog carrier signal. The spectral content of the recorded data can also adversely affect the system's ability to accurately detect the data when read back. As a result, some data sequences may be more difficult to detect than others. To account for this phenomenon,
Channel codes for randomizing data are used in recording devices. Such recording devices effectively "opaque" the data by randomizing the data before writing it to a disk storage medium.
n) ". Upon readback, the recording channel can detect random data with a lower bit error rate than if the data were not randomized. Data read from the storage medium is non-randomized before being transferred to the host.

[0004] In error correction coding (ECC), recorded binary data is mathematically processed,
Generate redundant symbols that are added to the data to form codewords that are written to the disk storage medium. At the time of reading back, the recorded codeword is evaluated (detected) from the read signal, and the redundant symbols are used to decode the evaluated codeword into the first recorded user data. In effect, the redundant symbols provide a buffer that protects the code word from noise as it passes through the recording channel. If enough noise "penetrates" this buffer, the noise changes the written codeword to a different received codeword, resulting in errors when decoded into user data.

[0005] The more redundant symbols used in an error correction code, the larger the buffer around the codeword and the more noise that can be tolerated before a decoding error occurs. However, the performance of any given recording channel, known as "channel capacity," which refers to the maximum user data rate (or recording density) achievable for a given channel while maintaining an arbitrarily low bit error rate, There is an upper limit. Ultimately, channel capacity is a function of channel bandwidth and signal-to-noise (SNR) ratio. As described above, the channel code and the error correction code are effective S
This is a means for improving performance by increasing NR.

[0006] In order to maximize the reliability and efficiency of the recording channel, there are a number of solutions for encoding / decoding user data. The end goal is to design a system that approaches channel capacity while simplifying implementation, lowering costs. Block error correction codes, especially Reed-Solomon block codes, are commonly used in disk storage systems due to their excellent error correction properties and low implementation cost and complexity.

A block code encodes a k-symbol input block of a source data stream into an n-symbol output block or codeword. Here, nk is the number of redundant symbols, and k / n is called a code rate. Next, the codeword is transferred (stored in the communication medium) through the communication medium and decoded by the receiver. The encoding process performs mathematical operations on the input block, and the output codeword is made different from other codewords by a parameter referred to as the minimum distance of the code d _min . The minimum distance d _min between codewords determines the amount of noise that the system can tolerate before a received codeword is incorrectly decoded.

[0008] In Reed-Solomon codes, the data stream is treated as a sequence of symbols, and the symbols are typically selected from a finite field GF (2 ^w ). The parameter w indicates the number of binary data bits per symbol. Each symbol of the k symbol input block indicates a coefficient of the data polynomial D (x). Next, a redundant symbol (also referred to as a polynomial W (x)) is calculated as the remainder division of the input data polynomial D (x) divided by the generator polynomial G (x).

[0009]

(Equation 1) Here, m is the order of the generator polynomial equal to the number of redundant symbols. Next, the redundant polynomial W (x) is added to the data polynomial D (x) to generate a codeword polynomial C (x).

[0010]

(Equation 2) It will be appreciated by those skilled in the art that the encoder circuit that performs the above operations is a linear feedback shift register (LFS).
R) with minimal cost.

After encoding, the codeword C (x) is transferred over the noise communication channel and the received codeword C ′
(X) is an error polynomial E in the transferred codeword C (x).
It is equal to the sum of (x). The received codeword C ′ (x) is corrected according to the following steps.
(1) Calculate the error syndrome S _i . (2) Calculate the coefficients of the error locator polynomial using the error syndrome Si. (3) Calculate the root of the error locator polynomial. Logarithm of the route is an error position L _i. (4) Calculate the error value using the error syndrome S _i and the root of the error locator polynomial.

The error syndrome Si is represented by a generator polynomial G
Received codeword polynomial C ′ divided by a factor of (x)
Calculated as remainder division of (x).

[0013]

(Equation 3) At this time

[0014]

(Equation 4) Where α is a basic element of the finite field GF (2 ^w ). Techniques for performing the other steps of the decoding process, calculating the error locator polynomial, calculating the root of the error locator polynomial, and calculating the error value are well known to those skilled in the art and are necessary to understand the present invention. is not. For example, "COEFFICIENT UPDATING METHOD AND APPA
See U.S. Patent No. 5,446,743, referenced below, entitled "RATUS FOR REED-SOLOMON DECODER."

Another technique known in the art to further increase error tolerance is to adapt the codeword to what is known as a multidimensional or product code. Digital video disk (DVD) storage systems, for example, typically use the two-dimensional product code shown in FIG. 3A. The codewords are adapted to intersecting horizontal (row or Q) and vertical (column or P) codewords, and the decoding process is performed in an iterative pass. First, a pass is made to the horizontal codeword to correct as many errors as possible. All uncorrectable horizontal codewords are left unchanged. Next, a pass is made to the vertical codeword to correct as many errors as possible. Here, the symbol corrected in the vertical codeword also corrects the corresponding symbol for the intersecting horizontal codeword. As a result, the horizontal codeword may be correctable in the next horizontal pass. Similarly, a symbol that is corrected in a horizontal pass may make a previously uncorrectable vertical codeword correctable in the next vertical pass. This iterative process continues until the full product code is corrected or cannot be corrected.

The two-dimensional product code of FIG. 3A also has CRC redundancy symbols that are used to check the validity of the correction for the row and column codewords. CRC redundancy is typically generated by processing user data according to the following equation:

[0017]

(Equation 5) Here, P (x) is user data represented as a polynomial having coefficients in a finite field GF (2 ^m ), nk is the number of CRC redundant symbols, and G
(X) is a generator polynomial. Next, CRC redundancy is
The resulting codeword C (x) is added to the user data before being written to the disc. During a read operation, data read from the disk is processed according to the following equation:
Generate CRC syndrome S _CRC .

[0018]

(Equation 6) Here, C ′ (x) is read from the disk (C
(Including RC redundancy) received codeword polynomial. Codeword C '
If there is no error in (x), the syndrome S _CRC will be zero.

CRC redundancy is typically generated on data during a write operation before encoding the ECC redundancy symbols, and the CRC syndrome is generated after the ECC redundancy is used to correct the product code. , Generated during a read operation. Thus, the CRC syndrome operates to verify the correction and detect a correction error. This is a very important function. This is because this feature allows the error correction system to prevent "bad data" from passing through the host system.

FIG. 1 shows an overview of a conventional error correction system typically found in CD / DVD optical disk storage systems. During a write operation (assuming the device is not read-only), user data received from the host system is stored in data buffer 1. Next, C
The RC generator and correction verifier 2 reads the user data from the buffer via the line 3, generates a CRC redundant symbol, and stores the user data with the redundant symbol added back to the data buffer 1. Then, the data (C
(Including RC redundancy) are read out again from the data buffer 1 and randomized by the data randomizer 4, and the random data is stored again in the data buffer 1. Next, the P / Q encoder / decoder 5 reads random data from the data buffer 1, and the ECC / syndrome generator 12 performs
Generate a C redundant symbol to form the two-dimensional product code shown in FIG. 3A. The individual P and Q codewords are stored again in data buffer 1 after adding ECC redundancy symbols. When the full product code is generated, the full product code is read from the data buffer 1 and written to the optical storage medium 6.

The system is a compact disk (CD)
When configured for data format, C1 and C
Additional redundancy, referred to as 2, is generated and added to the data before it is written to disk. Therefore, to facilitate the CD recording format, the error correction system uses a C1 encoder / decoder 7, a C2 encoder / decoder 8, and the well-known cross-interleaved Reed-Solomon code (CIRC). It has an interleaver / non-interleaver 9 for realization. Typically, the static RAM (SRAM) 10 has a CI
Used to implement the RC coding process,
SRAM is much faster than dynamic RAM (DRAM), the latter being used to implement the data buffer 1.

During a read operation, the process proceeds in reverse.
When configured for the CD format, the C1 and C2 decoders correct the random data in advance when the random data is read from the optical disk 6 and stored in the data buffer 1. Once the complete product code is available in data buffer 1, P / Q decoder 5
Start an iterative pass for the P and Q codewords to make further corrections. ECC / syndrome generator is on line 1
3 to generate an ECC syndrome transferred to the error corrector 14. The error corrector uses the ECC syndrome to correct errors in individual codewords as described above. At the end of the P or Q pass, the ECC error syndrome will be all zeros, meaning that the product code contains no errors (if there are no correction errors), and the random data will be read from data buffer 1. And is de-randomized by the de-randomizer 4. While the data is de-randomized, it is processed by the CRC generator and correction verifier 2 to generate a CRC syndrome. CR
If the C syndrome is zero, then P and Q
The correction to the codeword means valid and complete, the data is again read from the data buffer 1 and the non-randomized, non-randomized data is
Transferred to host system. If the CRC syndrome is not zero, this indicates that there was a product code correction error, and the CRC generator and correction verifier 2 forwards the error message to the host system via line 11;
The host system initiates a retry operation (ie, an attempt to read data from the disk again).

[0023]

A basic disadvantage of the conventional error correction system shown in FIG. 1 is that the data must be de-randomized before performing the CRC verification step. This requires reading the full product code, de-randomizing the data, and further accessing the buffer to generate the CRC syndrome, as described above. Obviously, this increases the latency of the storage system, and in particular, in order to achieve smooth and uninterrupted performance, large blocks of audio / video data must be read from the storage system in a continuous stream. Less desirable for media applications.

Therefore, when the verification symbols are generated before the randomization and the ECC symbols are generated after the randomization, it is necessary to prove the validity and completeness of the correction for a multidimensional code such as a CD / DVD product code. There is a need for an error correction system in computer storage that avoids the associated latency.

[0025]

SUMMARY OF THE INVENTION An error correction processor according to the present invention is an error correction processor for correcting an error in randomized data read from a disk storage medium, the error correction processor comprising: The data includes an ECC redundancy symbol generated for the randomized data and a check symbol generated for the data before being randomized, the error correction processor comprising:
(A) an ECC decoder for correcting an error in the randomized data using the ECC redundant symbol;
(B) a syndrome generator for generating a verification syndrome in response to the randomized data;
(C) comparing the verification syndrome with a predetermined value to determine the validity of the correction on the randomized data (validit
y) and a corrective verifier to verify integrity;
(D) a non-randomizer for non-randomizing the randomized data after the correction verifier indicates that the correction to the randomized data is valid and complete. Thus, the above object is achieved.

(A) said randomized data comprises first and second sets of intersecting codewords; and (b) said ECC decoder comprising said first set of codewords and said second set of codewords. The error in the randomized data may be corrected by processing the two sets of codewords in a sequential pass.

(A) said syndrome generator generates a data verification syndrome during a first pass for said first set of codewords; (b) said syndrome generator comprises:
The EC to correct the randomized data
Generating an error verification syndrome using the correction value generated by the C decoder; and (c) the syndrome generator combines the data verification syndrome with the error verification syndrome and compares the data verification syndrome with the predetermined value. A final verification syndrome to be performed may be generated.

(A) at the same time as the ECC decoder processes the randomized data, the syndrome generator generates a partial verification syndrome; and (b) the syndrome generator generates the partial verification syndrome. An offset controller for adjusting the partial verification syndrome depending on the location of the particular randomized data symbol being processed by the generator.

The ECC decoder generates a correction value for correcting a randomized data symbol, and (a) the offset controller generates a correction value according to a position of the corrected data symbol. Adjust
(B) The syndrome generator may update the partial verification syndrome using the correction value.

(A) The check symbol is generated according to a generating polynomial G (x) of a finite area, and (b) the offset controller transmits X ^{K to the} partial verification syndrome.
Adjust the partial verification syndrome by multiplying by modG (x), where K is an offset value and m
The od operator may perform modulo division.

(A) The check symbol may be generated according to a generator polynomial in a finite area, and (b) the predetermined value may be based on the generator polynomial.

(A) The non-randomizer generates a random pattern according to a predetermined seed value,
(B) The random pattern may be combined with the randomized data to de-randomize the randomized data.

(A) The check symbol may be generated according to a generator polynomial in a finite area, and (b) the predetermined value may be based on the generator polynomial and the random pattern.

The check symbol is a cyclic redundancy code (CR
C).

A method according to the invention for correcting an error in randomized data read from a disk storage medium, wherein the randomized data is Including a generated ECC redundancy symbol and a check symbol generated for the data before being randomized, the method comprising: (a) using the ECC redundancy symbol in the randomized data; Correcting the error; and (b) generating a verification syndrome in response to the randomized data;
(C) comparing the verification syndrome with a predetermined value to verify the validity and completeness of the correction to the randomized data; and (d) the correction verifier verifies the randomized data. De-randomizing the randomized data after indicating that the correction to is valid and complete, thereby achieving the above objective.

(A) said randomized data comprises first and second sets of intersecting codewords; and (b) said correcting comprises: said first set of codewords and said second set of codewords.
May be corrected in the randomized data by processing the set of codewords in a sequential pass.

The step of generating the verification syndrome includes: (a) generating a data verification syndrome during a first pass for the first set of codewords;
(B) generating an error verification syndrome using a correction value for correcting the randomized data; and (c) combining the data verification syndrome with the error verification syndrome to generate the predetermined value. Generating a final verification syndrome that is compared to

The step of generating the verification syndrome includes the steps of: (a) processing the randomized data to generate an EC;
Generating a partial verification syndrome at the same time as generating the C error syndrome; and (b) responding to a position of a particular randomized data symbol being processed to generate the ECC error syndrome. Adjusting the partial verification syndrome.

The step of generating the verification syndrome includes: (a) adjusting the partial verification syndrome in accordance with the position of the corrected data symbol; and (b) the correction used to correct the data symbol. By value,
Updating the partial verification syndrome.

(A) the check symbol is generated according to a generating polynomial G (x) of a finite area; and (b) the step of adjusting the partial verification syndrome is performed by adding X ^K modG (x) to the partial verification syndrome. Multiplying, where K is an offset value, and the mod operator may perform remainder division.

(A) The check symbol may be generated according to a generator polynomial in a finite area, and (b) the predetermined value may be based on the generator polynomial.

(A) The non-randomizer generates a random pattern according to a predetermined seed value, and (b) combines the random pattern with the randomized data to generate the randomized data. It may be non-randomized.

(A) The check symbol may be generated according to a generator polynomial in a finite area, and (b) the predetermined value may be based on the generator polynomial and the random pattern.

The check symbol is a cyclic redundancy code (CR
C).

Another error correction processor according to the invention is:
An error correction processor for correcting an error in data read from a disk storage medium, the data including an ECC redundancy symbol and a check symbol, wherein the error correction processor comprises: An ECC decoder for correcting errors in the data using the symbols;
(B) a syndrome generator for generating a verification syndrome in response to the data; and (c) comparing the verification syndrome with a predetermined value to verify the validity and completeness of the correction to the data. Correction verifier for
(D) a non-randomizer for non-randomizing the data after the correction verifier indicates that the correction to the randomized data is valid and complete; This achieves the above object.

Another error correction processor according to the invention is:
An error correction processor for correcting an error in randomized data read from a disk storage medium, wherein the randomized data includes an ECC redundancy generated for the randomized data. A symbol and a check symbol generated for the data before being randomized, the error correction processor comprising: (a) data for storing the randomized data read from the disk; A buffer, and (b) connected to receive the randomized data from the data buffer;
To correct errors in the randomized data,
An ECC decoder for generating an ECC error syndrome and correction value; and (c) the randomized data from the data buffer at the same time the ECC decoder receives the randomized data from the data buffer. A syndrome generator connected to receive the data and for generating a verification syndrome; and (d) comparing the verification syndrome to a predetermined value to determine the validity and completeness of correction to the randomized data. A correction verifier for verifying; and (e) connected to receive the randomized data from the data buffer, wherein the correction verifier is correct and valid for the randomized data. Indicating that the randomized data includes a non-randomizer for non-randomizing the randomized data, Serial object is achieved.

[0047] The verification syndrome may be generated according to a cyclic redundancy code (CRC).

[0048] The syndrome generator may update the verification syndrome with a correction value generated by the ECC decoder when a randomized data symbol is corrected.

An error correction system for computer storage is disclosed that avoids the latency associated with proving the validity and integrity of corrections to multidimensional codes. In a preferred embodiment, the verification comprises a cyclic redundancy check (CRC)
It is implemented using. During a write operation, a CRC redundancy symbol is calculated for the user data received from the host system, and after adding the CRC symbol, the data is:
It is randomized by performing an exclusive OR operation with a pseudo random data pattern. Next, an ECC symbol is generated (preferably using a Reed-Solomon code) for the randomized data to form a product code of the row (Q) and column (P) codewords. This product code is then written to disk. When reading back, the product sign is
It is stored in a data buffer and decoded by a P / Q decoder. During the first pass for the Q codeword, the data C
An RC syndrome is generated for the uncorrected randomized data, and the data CRC syndrome is stored in a data CRC register. Further, in the first pass and the next pass, when a correction is made to the P or Q codeword, the correction value is applied to the error CRC register. After processing the complete CRC codeword, the data CRC register and the error CRC register are combined and the final C
An RC syndrome is generated. The final CRC syndrome is compared to a constant to determine whether the correction to the product code is valid and complete. At this time, the constant is
Equivalent to CRC for random data pattern. Thus, a CRC check may be performed on the randomized data. This avoids the latency associated with accessing the data buffer to de-randomize the data before generating the CRC syndrome.

Another advantage provided by the present invention is that P
And the ability to generate a CRC syndrome during execution simultaneously with the correction of the Q codeword. Thus, immediately after processing the CRC codeword, the CRC syndrome is available to check the validity and completeness of the correction. That is,
There is no need to access the data buffer to generate a CRC syndrome.

The enablement aspect of the present invention is to adjust the data and error CRC syndrome during the P and Q passes,
Compensating for the offset within the CRC codeword symbol. For example, when processing a vertical (ie, P) codeword,
It is necessary to adjust the error CRC syndrome by one row of data symbols for each vertical symbol processed. This is because the data and error CR are:
This is performed using a special multiplier circuit that multiplies the C syndrome.

[0052]

(Equation 7) Here, k is an offset (eg, one row of symbols), and G (x) is a CRC generator polynomial.

Individual CRC added to each data sector
For DVD product codes with multiple data sectors with symbols, the SRAM used for C1 and C2 encoding / decoding in CD mode is used to store the partial data and error CRC syndrome for each data sector. . During the P and Q passes, the data and error CRC syndrome registers are loaded with the appropriate partial CRC syndrome, depending on the current data symbol processed by the P / Q decoder. After processing each data sector, the data CRC error syndrome and the error CRC syndrome for each data sector are combined to form a CRS for the pseudo-random data pattern.
It is compared with a constant equal to RC.

The above and other aspects and advantages of the present invention will be more clearly understood by reading the following detailed description of the present invention with reference to the drawings.

[0055]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The U.S. application on which the priority claim of the present invention is based is "AN ECC SYSTEM EMPLOYING A DATA B
UFFER FOR STORING CODEWORD DATA AND A SYNDROME BUF
No. 08 / 970,730, filed concurrently, entitled "FER FOR STORING ERROR SYNDOROMES,"
And "CONCURRENTGENERATION OF ECC ERROR SYNDRO
MES AND CRC VALIDATION SYNDOROMES IN A DVDSTORAGE
Co-filed US patent application Ser. No. 08 / 970,600 entitled “DEVICE” and “COEFFICIENT UPDATING
No. 5,446,743 entitled "METHOD AND APPARATUS FOR REED-SOLOMON DECODER". The aforementioned U.S. patent applications and U.S. patents are incorporated herein by reference.

[Overview of System] FIG. 2 shows an overview of the error correction system of the present invention. The operation of this system is similar to the conventional system described above with reference to FIG. 1, except for the following changes. During a read operation, an ECC error syndrome is generated simultaneously for both the horizontal and vertical codewords of the product code in a first horizontal pass. E
The CC error syndrome is stored in the SRAM 15,
The SRAM 15 uses the CIRC when decoding the CD product code.
Also used for error correction. This greatly reduces the waiting time of the storage device. This is because there is no need to access the data buffer 1 to reproduce the ECC error syndrome during the next horizontal or vertical pass. Another important modification of the present invention is to generate the CRC syndrome concurrently with the correction of the product code, and the CRC before de-randomizing the data stored in the data buffer.
To test for the syndrome. Thereby, CR
There is no need to read the entire product code from the data buffer 1 to generate the C syndrome, and the latency of the storage system is further reduced.

Components different from the conventional error correction system of FIG. 1 are an SRAM 15, a P / Q decoder 16 (ECC
/ Syndrome generator 17 and error corrector 18), and a CRC generator and correction verifier 19. The ECC / syndrome generator 17 uses the SRAM 15 in generating and storing ECC syndromes that are transferred to the error corrector via line 20. The correction value generated by the error corrector 18 for correcting the codeword stored in the data buffer 1 is also communicated via the line 21 to the ECC / syndrome generator 17 used when updating the ECC syndrome. Is done. The CRC generator and correction verifier 19 also uses the SRAM 15 to store 16 bits for the 16 data sectors of the DVD product code.
The partial CRC syndromes are stored. SRAM 15
The partial CRC syndrome stored in is updated with the correction value generated by the error corrector 18. The correction value is communicated via line 21 to the CRC generator and correction verifier 19.

[Data Format] FIG. 3A shows a data format of a two-dimensional product code typically used in a DVD storage device. The product code has 16 data sectors, each data sector having 12 horizontal codewords (Q
Codeword). Each horizontal codeword has ten ECC redundant symbols, preferably generated according to a Reed-Solomon code. 182 vertical codewords (P codewords)
, Each having 16 redundant symbols as shown. ECC redundant symbols also form ECC codewords. That is, the ECC redundant symbol can be corrected similarly to the user data. Thus, on the right side there are a total of 182 vertical codewords, including 10 ECC codewords, and on the lower side, 208, including 16 horizontal ECC codewords.
There are horizontal codewords.

At the end of each of the 16 data sectors, there are four CRC symbols used to prove the validity and completeness of the correction to the codeword using ECC redundant symbols. As described above, during a write operation,
CRC symbols are typically generated for user data before the data is randomized and before adding ECC redundancy symbols. Therefore, the CRC symbol is EC
Does not cover the C symbol. In addition, conventional error correction systems must de-randomize the data before performing a CRC check.

FIG. 3B shows further details of the first two data sectors of the product code of FIG. 3A. The technique of the present invention for generating a CRC syndrome simultaneously with correcting an ECC codeword will be described below with reference to FIG. 3B.

Data Randomizer / Derandomizer The error correction system of the present invention opaques user data and prevents data sequences that are difficult to detect from being recorded on the disc. As described above with reference to FIG. 2, the user data stored in the data buffer 1 is randomized after the CRC symbol is generated. Next, the ECC / syndrome generator 12 processes the randomized data and generates P and Q of the product code shown in FIG. 3A.
Generate ECC redundancy for the codeword. When reading back,
The product code is corrected and the correction is confirmed. If the correction is valid and complete, the data is de-randomized and transferred to the host system.

Circuits for randomizing / de-randomizing data are well known to those skilled in the art and are illustrated in FIGS. 3C and 3D.
Shows this circuit. The circuit has a random pattern generator for generating a pseudo-random data sequence provided on line 23. During a read operation, the user data and CRC symbols stored in the data buffer 1 are added to a random data sequence in an adder 24 (exclusive OR operation), thereby randomizing the data before the data is written to the disk. Become
Upon readback, the random pattern generator 22 adds to the data read from the disk in an adder 25 (exclusive OR), thereby de-randomizing the data before transferring it to the host system. I do.

Preferably, the pseudo-random data sequence is generated using 8-bit symbols (the symbol size of the ECC code). A preferred embodiment for generating a pseudo-random data sequence is a linear feedback shift register (LFS), as shown in FIG. 3D.
R). The LFSR circuit operates on line 26
And the pseudo-random data sequence is different depending on the seed value. A different seed value is used for each DVD product code shown in FIG. 3A.

[Simultaneous Generation of Horizontal and Vertical ECC Syndromes] A circuit and a flowchart for simultaneously generating ECC and CRC syndromes and updating ECC and CRC syndromes with correction values are disclosed below. There are two embodiments for the ECC syndrome generator 17 of the present invention. In a first embodiment, a syndrome is generated for a horizontal codeword during a horizontal pass while EC
A C syndrome is generated for the vertical code path.
As described in further detail below, the SRAM 15
Facilitates the generation of vertical syndrome. Thus, since the ECC syndrome for the vertical codeword is available in the SRAM 15 immediately after the horizontal pass, the vertical codeword is corrected without accessing the data buffer to generate the ECC syndrome, thereby causing an error. The correction waiting time is greatly reduced. In this embodiment, the correction is
Typically, a large amount of E, such as in a DVD storage device, completes after one pass on the horizontal and vertical codewords.
Particularly suitable for product codes using CC redundancy.

The second embodiment of the ECC syndrome generator 17 is directed to a product code with less ECC redundancy, and thus requires multiple horizontal and vertical passes. In this embodiment, SRAM 15 stores ECC syndromes for both horizontal and vertical codewords. Both sets of ECC syndromes are generated simultaneously during the first horizontal pass, and the ECC syndromes are updated with the correction values. Thus, latency in accessing the data buffer and regenerating the ECC syndrome is avoided for both horizontal and vertical passes. Error correction is performed in a short time. Because
The pass following the first pass only needs to access the data buffer to correct the data.

In the first embodiment of the present invention, only the vertical error syndrome is stored in the SRAM 15, which can be understood by referring to FIGS. FIG. 4 shows the circuitry used to generate error syndromes for the horizontal codeword in each horizontal pass. That is, the horizontal error syndrome is always regenerated and S
It is not stored in the RAM 15. To generate the horizontal error syndrome S _i , the circuit of FIG. 4 calculates the remainder division of each horizontal codeword C ′ (x) by a factor of the generator polynomial G (x) below.

[0067]

(Equation 8) At this time

[0068]

(Equation 9) It is. To do this calculation, the symbol of the horizontal codeword (including the ECC redundancy) are read sequentially from the data buffer 1, through the line 27, the linear feedback shift register (LFSR) 28 ₀ to 28 ₉ Given to the bank. In the preferred embodiment, each horizontal codeword contains 10 ECC redundant symbols, as shown in FIG. 3A, so there will be 10 LFSRs in FIG. Each LFSR is provided with a corresponding α ⁱ coefficient multiplier in the feedback path. Each L
The FSR performs remainder division on each factor of the generator polynomial G (x), thereby generating an error syndrome S _i for the above equation. The circuit disclosed in FIG. 4 is well known to those skilled in the art, and a novel aspect of the present invention is to simultaneously generate error syndromes for vertical codewords. FIG. 5 illustrates this detail.

Mathematically, the error syndrome for a vertical codeword is calculated in the same way as for the horizontal codeword above. That is, the vertical error syndrome S _i is generated by calculating the remainder division of each vertical codeword C ′ (x) by a factor of the generator polynomial G (x). Conventional syndrome generators typically generate vertical error syndromes using the same circuitry as shown in FIG. That is, the vertical codeword (E
Symbols (including CC redundancy) are read continuously from data buffer 1 and shifted through the banks of the LFSR. In the present invention, the vertical error syndrome is generated simultaneously with the generation of the horizontal error syndrome, avoiding accessing the data buffer to read the vertical codeword during the vertical pass.

FIG. 5 shows a circuit for simultaneously generating vertical error syndromes. The operation of this circuit can be understood by referring to the product code shown in FIG. 3A. SRA
M15 is 1 for each of the 182 vertical codewords.
Has the capacity to store the six error syndromes S _i.
The vertical error syndrome S _i in the SRAM 15 is
Initialized to zero at the beginning of the first horizontal pass. When processing the first horizontal codeword, the symbols are read continuously from the data buffer 1 and, via line 27, the LFS of FIG.
R to generate a horizontal error syndrome. The symbols are simultaneously provided to the circuit shown in FIG. 5 via line 27 to generate a vertical error syndrome. Similar to FIG. 4, FIG. 5 illustrates a vertical codeword symbol (each vertical codeword is 16 E) by 16 factors of the generator polynomial G (x).
With a bank of syndrome generating circuits 29 ₀ to 29 ₁₅ for calculating the modular division of having CC redundancy symbols).

The individual syndrome generation circuit 2 shown in FIG.
9₀From 29_FifteenIn order to understand, the first horizontal codeword is
Operation when data is read from the data buffer
Like. The first symbol of the first horizontal codeword is the first vertical code
Corresponds to the first symbol of the word. Therefore, the control line 30
Is 16 vertical error symbols for the first vertical codeword.
The ROM (each 8 bits) is taken out from the SRAM 15. each
The 8-bit vertical ECC syndrome uses the corresponding register
31₀From 31_FifteenAnd the multiplier 32₀From 32_Fifteen
And the corresponding αⁱFeedback Section
Number 33₀From 33 _FifteenMultiplied by On line 27
Is multiplied by the multiplier 34₀From 34_FifteenOutput and
Is selected and the adder 35 is selected.₀From 35_FifteenAt the coefficient
It is added as the output of the multiplier. Adder 35₀From 35
_FifteenThe syndrome updated with the output of
15 is stored again. The second symbol of the first horizontal codeword
, The control line 30 changes the second vertical codeword to
On the other hand, 16 vertical error syndromes
And the above procedure is repeated. This process
Continues for each of the horizontal codewords,
At the end, an error syndrome to correct the vertical codeword
Is stored in the SRAM 15.

If the horizontal codeword is corrected during the horizontal pass, the corresponding vertical error syndrome stored in SRAM 15 must be updated to take into account the corrected symbol. The syndrome generator 17 and error corrector 18 of FIG. 2 preferably operate on adjacent codewords. In other words, the syndrome generator 1
While 7 generates an error syndrome for the current horizontal codeword, error corrector 18 corrects the symbol for the previous horizontal codeword. In addition, error correction tracks the generation of horizontal error syndromes and simplifies adjustment of vertical error syndromes with correction values.

For example, while the syndrome generator 17 corrects the first horizontal codeword while the error corrector 18 corrects the first horizontal codeword, FIG.
Consider generating error syndromes for the second horizontal codeword of. Assume that the syndrome generator 17 has passed the third symbol 36 of the second codeword and the third symbol 37 of the first codeword is erroneous. Error Corrector 1
8 generates a correction value used to correct the third symbol 37 of the first horizontal codeword stored in the data buffer 1, and the correction value is the vertical syndrome generation circuits 29 ₀ to 29 _{15 of} FIG. Via line 21.
Control line 30 takes out is latched in the register 31 ₀ to 31 _15, the vertical error syndromes for the third vertical codeword from SRAM 15. Next, the outputs of registers 31 ₀ through 31 ₁₅ are selected through multipliers 34 ₀ through 34 ₁₅ as inputs to adders 35 ₀ through 35 ₁₅ . The correction value provided via line 21 is
Is selected as the output of the 2 ₀ to 32 _15, are multiplied by the corresponding alpha ⁱ feedback coefficient 33 ₀ to 33 _15, is added to the vertical error syndromes at adder 35 ₀ 35 _15. Α ⁱ feedback coefficient 3 corresponding to the correction value
Multiplying by 3 ₀ to 33 ₁₅ gives the current vertical E
This is necessary to account for the offset between the CC syndrome value and the symbol being corrected (ie, the offset of one symbol in the vertical codeword).

At the end of the horizontal pass, the error syndrome for the vertical codeword is completely generated and immediately available for processing. Thus, to perform a vertical pass, the vertical error syndrome is simply retrieved from SRAM 15 and used by error corrector 18 to correct the vertical codeword. After the vertical pass, if the CRC symbol of the product code indicates that errors still remain, the above process is repeated (ie, the horizontal and vertical error syndromes are regenerated in the next horizontal pass).

In another embodiment of the invention, both horizontal and vertical syndromes are stored in SRAM 15. Because they are generated simultaneously in the first horizontal pass. Thus, there is no need to regenerate the horizontal syndrome during the next horizontal pass as in the above embodiment. Syndromes are simply taken out during the horizontal and vertical passes and used to correct the codeword. This embodiment is particularly advantageous when multiple passes are required to correct the product code (eg, when increasing the recording density reduces ECC redundant symbols or decreases SNR). is there.

FIGS. 6A and 6B show circuits for updating the vertical and horizontal syndromes using the correction values according to the present embodiment, respectively. Since these circuits do not need to consider the offset, the error correction value 21 is represented by α
It operates substantially the same as the circuit of FIG. 5, except that there is no need to multiply by ⁱ . In a preferred embodiment, the first
The circuitry of FIGS. 4 and 5 for first generating horizontal and vertical error syndromes in the horizontal pass is shared with the circuitry of FIGS. 6A and 6B for updating the error syndromes in the next pass. Addressing via control line 30 determines which set of error syndromes (horizontal or vertical) is retrieved from SRAM 15 at the appropriate time.

FIG. 7A is a flowchart for explaining the operation of the present invention, which is executed by a controller (not shown). During the first horizontal pass 37, horizontal and vertical ECC
The syndrome and the data CRC syndrome are simultaneously generated and stored in the SRAM 15. Also, during the first horizontal pass 37, the horizontal coded word is corrected, and the vertical syndrome and the error CRC syndrome stored in the SRAM 15 are updated using the correction value. After the first and next horizontal passes, in step 38 the validity and completeness of the correction to the product code is verified using the final CRC syndrome. If the error remains after the horizontal pass, a vertical pass is performed at step 40 to correct the vertical codeword. Here, the horizontal syndrome stored in the syndrome buffer is updated using the correction value. After the vertical pass, in step 42, the validity and completeness of the correction is verified using the final CRC syndrome. If the error remains after the vertical pass, another horizontal pass is performed at step 44 to correct the horizontal codeword. Depending on the actual application, corrections are made using horizontal syndromes stored in SRAM 15 (ie, horizontal syndromes are not regenerated if they are already available in SRAM 15). The horizontal and vertical passes and the CRC check are repeated until the product code is corrected or determined to be uncorrectable.

FIG. 7B shows a flow diagram for simultaneously generating the horizontal and vertical syndromes and the data CRC syndrome during the first horizontal pass, and also corrects the horizontal codeword during the first pass and converts A flow diagram for updating the vertical syndrome and the error CRC syndrome using the same is shown in FIG. 7C (the flow diagrams of FIGS. 7B and 7C are executed in parallel). Referring to FIG. 7B, at step 46,
The COL and ROW variables are initialized to zero. SRA
M15 is cleared and the block uncorrectable error flag (B
LK_UNC) is cleared and FIRST_PA
The SS flag is set, indicating that this is the first horizontal pass. Next, at step 48, a symbol is read for the ROW horizontal codeword, which is used to generate the horizontal ECC syndrome using the circuit of FIG. 4 and the circuit of FIG. 5, as described above. The vertical ECC syndrome is updated. If the FIRST_PASS flag is set in step 50, this data symbol is also used to update the data CRC syndrome in step 52 by performing the flow diagram of FIG. 7F. Next, at step 54, the COL variable is incremented and the horizontal and vertical ECC syndromes and data CRC syndrome are updated during the first horizontal pass with the next symbol for the current horizontal codeword.

If the COL variable equals 182 at step 56, it means that the last symbol for the current horizontal codeword has been read. A loop is executed at step 58 to wait for the error correction procedure (flow diagram of FIG. 7C) to finish processing the previous horizontal codeword. When the correction of the previous codeword is completed, the correction flag is reset to "not in use" in step 88 of FIG. 7C. In step 60 of FIG. 7B, the correction flag is set to busy, the C_ROW variable is set to the current ROW, the ROW variable is incremented,
The COL variable is reset to zero. At this point, FIG.
A C correction procedure is performed to correct the current horizontal codeword (ie, the C_ROW codeword), while at the same time generating an ECC syndrome for the next horizontal codeword (ie, the ROW codeword).

Referring to FIG. 7C, a loop is executed at step 64 to wait for the syndrome generation procedure of FIG. 7B to finish processing the current horizontal codeword and set the correction flag to in use. At step 66, the C_COL variable tracking the current column during correction is reset to zero (ie, reset to the first symbol of the horizontal codeword being corrected) and the codeword uncorrectable flag (CW_UNC) is cleared. You. At step 68, the ECC syndrome for the horizontal codeword being corrected is retrieved from SRAM 15, an error locator polynomial is generated, and it is determined whether the root corresponds to a valid symbol position. Step 6
If, at 9, the ECC syndrome is zero, indicating no error, the error CRC syndrome is updated at step 71. If, at step 70, the syndrome is too errory or the root of the error locator polynomial points to an invalid symbol, then at step 73, CW_U
The NC and BLK_UNC flags are set, indicating that the codeword and the entire block (product code) contain an uncorrectable error, and in step 71 the error CRC syndrome is updated. If the codeword is correctable at step 70, then at step 72 the ECC syndrome for the C_ROW horizontal codeword is cleared (set to zero). Next, a loop is executed to correct the horizontal codeword of C_ROW. At step 74, if the symbol of C_COL is erroneous, a branch is performed to correct the symbol stored in the data buffer and the vertical syndrome is updated with the corrected value. This correction is made in step 7
At 6, it is delayed until C_COL is less than COL. That is, the error correction procedure of FIG. 7C waits until the syndrome generation procedure of FIG. 7B passes the current correction column C_COL. This is necessary for the circuit of FIG. 5 to work properly. Because the circuit has a correction value of 21
Is multiplied by α ⁱ 33 _i to calculate the offset of one symbol. Step 78 of FIG. 7C
At step 80, the horizontal codeword symbols stored in the data buffer are corrected using the correction values, and at step 80, using the correction values, for the vertical codeword of C_COL as described above in connection with FIG. The vertical syndrome is updated. In step 81, the error CRC syndrome is updated with the correction value (even if the correction value is zero), and in step 82,
The variable C_COL is incremented to the next symbol of the horizontal codeword and the correction loop is executed again.

If C_COL is equal to 182 in step 84, it means that the last symbol of the horizontal codeword has been processed. In order to quickly update the error syndromes for the current horizontal codeword during the next vertical pass, at step 86 these error syndromes are relocated to the first codeword symbol. This is performed by the following calculation.

[0082]

(Equation 10) The circuit that performs the above operation is described in more detail below.

In step 88 of FIG. 7C, the correction in use flag is cleared, and in step 64, the correction procedure waits for the syndrome generation procedure of FIG. 7B to finish generating the error syndrome for the next horizontal codeword. . In the syndrome generation procedure and the error correction procedure, the final horizontal codeword is processed (that is, ROW is 20 in step 62 in FIG. 7B).
8). At this time,
In step 63, the FIRST_PASS flag is cleared and control returns to FIG. 7A. If the error remains after the first horizontal pass in step 38 of FIG. 7A, step 4
At 0, a vertical pass is performed. The flowchart of this procedure is shown in FIG.
D.

At step 90, the correction variables C_COL and C_ROW are reset to zero (ie, reset to the first symbol of the first vertical codeword) and the codeword uncorrectable flag (CW_UNC) is cleared. Next, at step 92, the syndrome for the vertical codeword being corrected is retrieved from the SRAM 15, an error locator polynomial is generated, and it is determined whether the root corresponds to a valid symbol position. If, at step 93, the ECC syndrome is zero, indicating no error, at step 95, the error CRC syndrome is updated. Step 94
If the syndrome is too errory or the root of the error locator polynomial points to an invalid symbol, the CW_UNC and BLK_UNC flags are set at step 97 and the error CRC syndrome is updated at step 95. If the codeword is correctable at step 94, then at step 96 the ECC for the vertical codeword is
The syndrome is cleared (set to zero). Next, a loop is executed to correct the vertical codeword of C_COL. If the symbol C_ROW is incorrect at step 98, a branch is performed to correct the symbol stored in the data buffer at step 100, and the horizontal syndrome is updated with the corrected value at step 102. Using the circuit of FIG. 6A, the horizontal syndrome is updated in a manner similar to that described above with reference to FIG. C_R
The OW horizontal ECC syndrome is extracted from the SRAM 15, multiplied by α ⁱ 33 _i , added to the correction value 35 _i , and returned into the SRAM 15. Although not shown in the flowchart of FIG. 7D, the horizontal syndrome is updated for each symbol of the codeword even when no correction is performed (that is, when the correction value is zero). As a result, FIG.
Is simplified. That is, E
Only the α ⁱ multiplier 33 _i is needed to position the CC syndrome to the next codeword symbol.

In step 104 of FIG. 7D, the error CRC syndrome is updated to the correction value (even if the correction value is zero), and in step 105, the C_ROW variable is incremented to the next symbol of the current vertical codeword. At step 106, the correction room is repeated until C_ROW equals 208, ie, the last symbol of the current vertical codeword has been processed. Once the last symbol has been processed (or if the codeword is uncorrectable at step 94), at step 107, the error syndrome for the C_COL vertical codeword is relocated to the first symbol of the codeword. This is performed by the following calculation.

[0086]

[Equation 11] The circuit that performs the above operation is described in more detail below.

At step 108, the C_COL variable is incremented to the next vertical codeword, and the C_ROW variable is reset to zero to point to the first symbol of the next vertical codeword. The correction procedure of FIG. 7D is repeated until C_COL equals 182 at step 110, indicating that all of the vertical codewords have been processed.

At the end of the vertical pass, if an error remains in the product code in step 42, a horizontal correction pass is executed in step 44. If the horizontal syndrome is not stored in the SRAM 15, the flow diagram of FIG. 7B is executed in step 44, and the horizontal ECC syndrome is regenerated (FIRST_PASS is false). However, SRA
If the horizontal ECC syndrome is stored in M15, the flowchart of FIG. 7E is executed, and the ECC syndrome that simply reduces the latency of the correction system is extracted and processed.

In step 112 of FIG. 7E, the correction variable C_
COL and C_ROW are reset to zero (ie, reset to the first symbol of the first horizontal codeword) and the codeword uncorrectable flag (CW_UNC) is cleared. Next, at step 114, the syndrome for the horizontal codeword being corrected is retrieved from the SRAM 15, an error locator polynomial is generated, and it is determined whether the root corresponds to a valid symbol location. At step 115, E
If the CC syndrome is zero, indicating no error, the error CRC syndrome is updated in step 117. If at step 116 the syndrome is too errory or the root of the error locator polynomial points to an invalid symbol, then at step 119 the CW_UNC and BLK_UNC flags are set and the codeword and the entire block (product code) are uncorrectable Indicates that it contains an error,
At step 117, the error CRC syndrome is updated. At step 116, if the codeword is correctable, then at step 118, the ECC syndrome for the C_ROW horizontal codeword is cleared (set to zero). Next, a loop is executed to correct the horizontal codeword of C_ROW.

If it is determined in step 120 that the symbol of C_COL is erroneous, the branch is executed and step 122 is executed.
The symbol stored in the data buffer is corrected by
At step 124, the vertical syndrome is updated using the correction value. The vertical ECC syndrome is updated using the circuit of FIG. 6B in a manner similar to that described above with reference to FIG. 6A to update the horizontal ECC syndrome during the vertical pass. C_COL vertical ECC syndrome is SR
Taked out of AM 15, multiplied by α ⁱ 33 _i , added to correction value 35 _i , and returned in SRAM 15. FIG. 7E
, The vertical ECC syndrome is updated for each symbol of the codeword even when no correction is made (ie, when the correction value is zero). This simplifies the syndrome update circuit of FIG. 6B. That is, only the α ⁱ multiplier 33 _i is needed to position the ECC syndrome at the next codeword symbol.

In step 126 of FIG. 7E, the error CRC is updated with the correction value (even if the correction value is zero), and in step 127, the C_COL variable is incremented to the next symbol of the current horizontal codeword. . Step 128
If C_COL is equal to 182, it means that the last symbol of the current horizontal codeword has been processed. If the last symbol has been processed (or if the codeword is uncorrectable in step 116), then in step 130, C_
The error syndrome for the ROW horizontal codeword is relocated to the first symbol of the codeword. This is performed by the following calculation.

[0092]

(Equation 12) At step 132, the C_ROW variable is incremented to the next horizontal codeword and the C_COL variable is reset to zero to point to the first symbol of the next horizontal codeword. The correction procedure of FIG. 7E is repeated until C_ROW equals 208 at step 134, indicating that all of the horizontal codewords have been processed.

Referring again to FIG. 7A, if errors remain after the horizontal pass is completed at step 44, another vertical pass is performed at step 40. Repeated horizontal and vertical passes continue until the product code is corrected or determined to be uncorrectable. FIGS. 7G to 7I are flow charts for generating the data CRC syndrome and the error CRC syndrome for each data sector, and the circuits for generating the CRC syndrome are shown in FIGS.
It is shown in FIG. These flow diagrams and circuits operate as follows.

[Generation and Verification of CRC Syndrome] The CRC syndrome for each data sector in FIG.
It is generated in two parts: a data CRC syndrome and an error CRC syndrome. The data CRC syndrome is generated as a CRC for the uncorrected data, and the error CRC syndrome is a CRC for the corrected value.
Is generated as When the processing of the data sector of the product code of FIG. 3A is completed, the data CRC syndrome and the error CR
The C syndrome is combined with the final CRC syndrome to generate and compare to a constant to determine whether the correction for this sector is valid and complete. As described above, the data CRC syndrome and the error CR
The C syndrome is generated simultaneously with correcting the product code for the randomized data. That is, it is not generated after correction and after non-randomization of data as in the related art.

In the conventional error correction system shown in FIG.
The C redundant symbol CRC _RED is generated as remainder division of the data polynomial D (x) divided by the generator polynomial G (x).

[0096]

(Equation 13) CRC redundancy symbol CRC _RED is _converted to data polynomial D (x)
To the pseudorandom data sequence polynomial R
Randomizing the data by adding (x)
As a result, the codeword polynomial C (x) is written to the disk.

[0097]

[Equation 14] When read back, the received codeword polynomial C ′ (x)
Is corrected using ECC redundant symbols, the pseudo-random data sequence R (x) is subtracted from the corrected codeword, and the following CRC syndrome S _CRC is generated.

[0098]

(Equation 15) The CRC syndrome S _CRC is then compared to zero to confirm the validity and completeness of the correction.

In the present invention, the CRC check is performed before de-randomizing the corrected codeword. As a possible modification of the invention, the last CRC syndrome may be compared to the CRC over the pseudo-random data sequence used to randomize / de-randomize the data. This is understood by the following mathematical relationship.

[0100]

(Equation 16) Here, D (x) is a data polynomial, CRC _RED is CRC
Redundancy, and R (x), is a pseudorandom data sequence polynomial added to the data polynomial to randomize the data. The resulting codeword C (x) written to the disk is the same as in the prior art described above. However, dividing the received codeword C ′ (x) by the CRC generator polynomial before de-randomizing the data (ie, before subtracting the pseudo-random data sequence polynomial R (x)) gives: The relationship is guided.

[0101]

[Equation 17] Here, E (x) is an error polynomial. The above equation can be rewritten as:

[0102]

(Equation 18) In the above equation, (D (x) · x ^nk + CRC _RED ) mod
G (x) = 0. Therefore, the following equation is obtained.

[0103]

[Equation 19] Thus, if the received codeword C ′ (x) is completely corrected using ECC redundancy (ie, E (x)
= 0), the final CRC syndrome generated for the received codeword C ′ (x) is the pseudo-random data sequence R (x), as can be seen from the above equation.
It is equal to the remainder division divided by the C generator polynomial G (x).
Since the pseudorandom data sequence R (x) and the generator polynomial G (x) are known, the remainder obtained by dividing the pseudorandom data sequence R (x) by the generator polynomial G (x) is a constant. That is, the last CRC syndrome is simply compared to this constant to determine whether correction using the ECC syndrome is valid and complete. CR
The C syndrome is generated immediately upon correction of the received codeword, so that the CRC syndrome is immediately available. That is, it is not necessary to read the entire codeword from the data buffer in order to generate the CRC syndrome as in the related art.

To generate the CRC syndrome concurrently with the correction of the received codeword, the present invention generates a data CRC syndrome for the uncorrected data during a first horizontal pass, and also generates a horizontal and vertical CRC syndrome. Generate an error CRC syndrome for the correction value during both passes. FIG.
When the processing of the data sector of the product code of A is completed, the data CRC syndrome and the error CRC syndrome are combined to generate a final CRC syndrome, which is compared with a constant (R (x) mod G (x)).

In the present invention, the data CRC syndrome and the error CRC syndrome are stored in a conventional manner (ie, a linear feedback shift register (LFSR)).
Is not generated). This is because data symbols are not sequentially read from the data buffer during the vertical pass. Instead, data and CR
The C syndrome is adjusted to correspond to the position of the data symbol being processed. This adjustment is performed by multiplying the data CRC syndrome and the error CRC syndrome by the following values:

[0106]

(Equation 20) Where k represents the number of symbols that “move” the syndrome across the codeword. For example, when generating the data CRC syndrome during the first horizontal pass, the data CRC syndrome

[0107]

(Equation 21) , Which adjusts the data CRC syndrome to the next symbol of the current horizontal codeword. During the vertical pass, the error CRC syndrome is

[0108]

(Equation 22) , Thereby adjusting the error CRC syndrome to the next symbol of the current vertical codeword. The mathematical basis of this method of generating a CRC syndrome is described below with reference to circuits that implement a CRC generator and a corrective verifier.

As shown in FIG. 3A, there are 16 data sectors, each having CRC redundancy. Thus, 16 data CRC syndromes are generated during the first horizontal pass and 1 during both the horizontal and vertical passes.
Six error CRC syndromes are updated. These syndromes are preferably stored in the SRAM 15,
This enables both the CIRC error correction for the CD-ROM format and the generation of the CRC syndrome for the DVD format using the SRAM 15. As each new sector is processed during the first horizontal pass, the current data CRC syndrome is initialized to a starting value. Before initializing the data CRC syndrome to the starting value for the next sector, the current data CRC syndrome for the previous data sector must be SRA
Stored in M15. Similarly, when processing a vertical codeword, the appropriate error CRC syndrome corresponding to the current data sector is retrieved from SRAM 15 as the error correction system progresses vertically through the 16 data sectors. This process of updating the data and error CRC syndromes according to the current data sector being processed is understood by the flow diagrams of FIGS. 7F to 7J.

FIG. 7F shows a flow diagram for generating a data CRC syndrome during the first horizontal pass for the product code of FIG. 3A. The first two data sectors of this product code are shown in FIG. 3B. The flow chart of FIG.
Is executed each time a new data symbol is read from the data buffer in step 52 of FIG. In step 136 of FIG. 7F, a check is performed to determine whether the data CRC syndrome should be initialized to the first symbol of the next data sector. For example, when processing the first symbol of the first horizontal codeword, at step 138, the data CR
Data register DATA_R for storing C syndrome
The EG is initialized with the first symbol 160 of the first data sector in FIG. 3B. When the next data sector is reached (ie, when ROW is equal to 12 in step 136), the data CRC syndrome for the first data sector is stored in SRAM 15 in step 138 and DATA_REG stores the next horizontal codeword. Is initialized by the first data symbol 204 for

Continuing with the flowchart of FIG. 7F, if the first symbol of the data sector is not processed and if COL is smaller than 172 in step 144, the data CRC syndrome is only one symbol (one column) in step 146. Adjusted to the right, the current data symbol is added to the data CRC syndrome. Step 144
If COL is greater than 171, the current data symbol is not added to the data CRC syndrome. This is because this is an ECC redundancy symbol that is not included in the CRC codeword (ECC redundancy is added after the CRC codeword is generated during a write operation as described above). For example, when the first horizontal codeword of FIG. 3B is processed, the generation of the data CRC syndrome is performed as shown in FIG.
COL is reset to zero in step 60, and the symbol 148 is stopped until the processing of the next horizontal codeword is started. Next, at step 146, before adding the first data symbol 150 of the second horizontal codeword to the data CRC syndrome, the data CRC syndrome is first adjusted one symbol to the right (ie, to symbol 150 of FIG. 3B). You.

When the processing of the last horizontal codeword of the data sector is completed (that is, ROW + 1 m in step 154)
od 12 is equal to 0 and COL is 1 in step 156
When equal to 81), the data CRC syndrome is located at the last symbol of the corresponding data sector.
For example, upon completion of the processing of the first data sector, the data CRC syndrome is positioned with respect to symbol 152 in FIG. 3B. As described above, each corresponding error CRC syndrome is also located at the last data symbol of the data sector before performing a CRC check.

When the processing of the first data sector is completed,
In step 136 of FIG. 7F, ROW is equal to 12 and R
OW mod 12 is equal to zero. Accordingly, at step 138, the current data C for the first data sector
RC syndrome is stored in SRAM15, and DAT
A_REG is derived from the starting position for the second data sector, which is retrieved from the SRAM 15 (ie, FIG.
(B symbol 142). Step 146
, A data symbol for the CRC codeword of the second data sector is added to the data CRC syndrome. This process continues until all 16 data CRC syndromes have been generated and stored in SRAM 15.

FIGS. 7G to 7J show flowcharts for generating the error CRC syndrome during the horizontal and vertical passes. During the first horizontal pass, the error CRC syndrome is updated to the correction value (even if the correction value is zero) in step 81 of FIG. 7C. In step 159 of FIG. 7G, a branch is performed depending on whether the current path is horizontal or vertical. If a horizontal pass is currently being performed, step 16
If 1 and C_ROW is greater than 191, then the error CRC is incorrect because ECC redundancy is not part of the CRC syndrome.
Syndrome is not updated. In the case of a vertical pass, in step 162, the correction column C_COL and the correction row C_ROW
If mod 12 is zero, step 164
In the register for generating the error CRC syndrome ERR_REG, the SRAM1 corresponding to the current data sector is stored.
The partial error CRC syndrome from 5 is loaded.

At step 166, the codeword is uncorrectable (ie, the uncorrectable flag (CW_UNC) is set) or the ECC syndrome for the current horizontal codeword is zero and cannot be corrected. If so, a branch is taken at step 168 depending on whether the codeword is the last horizontal codeword of the current data sector. The last codeword of the data sector (ie, C
If _ROW + 1 mod 12 is equal to zero, then at step 169, the error CRC syndrome for the current data sector is shifted to the right by 171 symbols to the last symbol of the CRC codeword (eg, (From symbol 158 to symbol 152 in FIG. 3B) and C_COL is 17
Set to 2. In order to reduce the number of multiplication tables described later, the error CRC syndrome 17
Shifting one symbol right is performed in a loop that repeats shifting the error CRC syndrome right one symbol 171 times. If the current codeword is not the last codeword of the data sector, at step 170,
The error CRC syndrome is simply adjusted down one line to skip the current horizontal codeword. After this, the control
Returning to E, processing of the next horizontal codeword of the data sector is continued.

At step 166, if the codeword uncorrectable flag (CW_UNC) is not set and the ECC syndrome for the current horizontal codeword is not zero,
In step 172 of H, a branch is performed based on the current value of the correction sequence C_COL. C_COL is 0 to 171
, If the first data symbol of the current horizontal codeword has not been processed (ie, step 174).
If C_COL is not zero at step 176), the error CRC syndrome is adjusted right by one symbol (one column) at step 176 and the correction value for the current data symbol is added to the error CRC syndrome at step 178. This process continues until all of the correction values for the current horizontal codeword have been added to the error CRC syndrome. The ECC symbol of the horizontal codeword is (C_C
OL is 173 to 180), as described above, since these are not part of the CRC codeword,
It is not added to the syndrome. Once the last data symbol of the current horizontal codeword has been processed (ie, when C_COL is equal to 172 in step 172), in step 180, an error CRC syndrome indicates that the current horizontal codeword is the last code of the current data sector. Adjusted based on word. If the codeword is not the last horizontal codeword in the data sector (ie, if (ROW + 1) mod 12 is not 0 in step 180), then in step 182, the error CRC syndrome is adjusted one symbol to the right. For the first symbol of the next horizontal codeword. If the current horizontal codeword is the last codeword of the current data sector, at step 181, DATA_REG is loaded from SRAM 15 with the data CRC syndrome for the current data sector and combined with ERR_REG. As described above, the result is a CR
If it is not equal to C, a block uncorrectable flag (BLK_UNC flag) is set in step 183. Next, in step 184, the error CRC syndrome is 12
Adjusted just above the row and one symbol to the right, it is rearranged relative to the first symbol of the data sector. For example, if the error CRC syndrome is located at the last symbol 152 of the CRC codeword of the first data sector in FIG.
By adjusting up the row only and one symbol to the right, the erroneous CRC syndrome is located at the first symbol 160 of the data sector. Next, step 185
The error CRC syndrome (stored in ERR_REG) for the current data sector is stored again in SRAM 15.

The error CRC update procedure of FIGS. 7G and 7H is repeated until an error CRC syndrome has been generated for all 16 data sectors of FIG. 3A and compared to the CRC over the pseudo-random sequence. At the end of the first horizontal pass, at step 254 in FIG.
The LK_UNC flag is examined to confirm the validity and completeness of the product code correction. If an error remains, a vertical pass is performed and at step 104 in FIG. 7D (or step 95 if the vertical codeword is skipped).
7), the error CRC update procedure of FIG. 7I is executed to update the error CRC syndrome with the correction value applied to the vertical codeword.

At step 159 in FIG. 7G, the control proceeds to FIG.
To update the error CRC syndrome for the vertical path. In step 186 of FIG.
If _COL is greater than 171, nothing is updated because the vertical codeword for the horizontal ECC symbol is not included in the CRC codeword. If C_COL is less than 172 at step 186, a check is made at step 188 to determine if the erroneous CRC syndrome has proceeded down the current vertical codeword to the last row of the current data sector. . Current correction line C_ROW mod
If 12 is equal to zero, at step 190 the partially erroneous CRC syndrome for the current data sector is retrieved from SRAM 15 and loaded into ERR_REG.

If the codeword uncorrectable error flag (CW_UNC) is set in step 192, or if the ECC syndrome for the current vertical codeword is zero, the flow diagram of FIG. Adjust the CRC syndrome right by one symbol (ie, skip the current vertical codeword). In step 193, C_
If COL is not equal to 171 (ie, if the last vertical codeword of the data sector has not been processed), then at step 194, the error CR for the first data sector is
The C syndrome is adjusted right by one symbol (one column). In step 196, the partial error CRC syndrome for the current data sector is stored in SRAM 15,
In step 197, C_ROW is incremented by 12. That is, it is moved to the next data sector. If C_ROW is not greater than 191 at step 198,
In step 200, the ERR_REG is stored in the SRAM 15 with a partial error CRC syndrome for the next data sector.
, The error CRC syndrome is adjusted right by one symbol in step 194, and
At 6, it is stored again in the SRAM 15. This loop is repeated until C_ROW is greater than 191 at step 198, at which point all errors C
The RC syndrome is adjusted right by one symbol (one column), skipping the current vertical codeword.

In step 193 of FIG. 7J, C_COL is 1
If it is equal to 71, the final vertical codeword (before ECC redundancy) will be skipped. Therefore, it is necessary to generate a final CRC syndrome for each data sector for each data sector and set the BLK_UNC flag if errors remain. In step 201, the error C for the current data sector (stored in ERR_REG)
The RC syndrome is adjusted down by 11 data symbols (eg, from symbol 148 to symbol 152 in FIG. 3B). Step 201 is actually ERR_REG
Is adjusted downward by one symbol (D1) as a loop that repeats 11 times. Next, in step 203,
DATA_REG is initialized with the data CRC syndrome for the current data sector from SRAM 15, and the final CRC syndrome is generated by combining DATA_REG with ERR_REG.
If the final CRC syndrome is not equal to the CRC over the pseudo-random sequence, step 205 sets the block uncorrectable flag (BLK_UNC). At step 207, the error CRC syndrome is 1
By adjusting up two rows and one data symbol to the right (eg, from symbol 152 to symbol 160 in FIG. 3B), it is adjusted to the start of the data sector. Error 200 for the next data sector in step 200
The RC syndrome is loaded into ERR_REG and the above procedure is repeated. If C_ROW is greater than 191 at step 198, the CR for each data sector is
A C-check has been performed and the erroneous CRC syndrome should have been relocated to the start of each data sector.

Referring again to FIG. 7I, step 192 is executed.
If the codeword uncorrectable flag (CW_UNC) is not set and the ECC syndrome is not zero, a branch is performed in step 206, and the error CRC syndrome is updated based on the current value of the corrected row C_ROW. If C_ROW is 192 to 207 in step 206, C
Since the RC codeword does not include an ECC redundancy symbol, control simply returns. If C_ROW is 0-191, the current error CRC syndrome is
Is adjusted down by one symbol, and in step 210, the correction value of the next symbol is added to the error CRC syndrome. If the error CRC syndrome is in the first row of the data sector (i.e., if C_ROWmod12 is zero in step 212), step 208 of adjusting the error CRC syndrome down one symbol is skipped.

In step 209, when the last row of the current data sector is reached (that is, C_ROW + 1mod12
Is zero), the error CRC syndrome is adjusted to the top position of the data sector for the next codeword in the vertical direction. This means that the error CRC syndrome is adjusted one symbol down (D1) in step 211, and
Is adjusted one symbol right and 12 symbols upward (UP12_R1). If C_COL is equal to 171 at step 215, the error CRC syndrome is located above the last symbol of the data sector and a CRC check is performed. At step 217, DATA_REG is loaded from SRAM 15 with the data CRC syndrome of the current data sector, combined with ERR_REG, and the final CRC
A syndrome is generated. If the final CRC syndrome is not equal to the CRC on the pseudo-random sequence,
In step 219, the block uncorrectable flag (BLK_U
NC) is set. Then, in step 213, the erroneous CRC syndrome is moved one data symbol right (UP12_R1) on line 12 and relocated on the first symbol of the data sector (eg, moved from symbol 152 to symbol 160 in FIG. 3B). ), At step 214, the error CRC syndrome (ERR_REG) of the current data sector.
Is stored in the SRAM 15.

At the end of the vertical pass, BLK_UN
The C flag is checked in step 254 of FIG. 7K to verify the validity and completeness of the correction for the product code. If there are still errors, the horizontal pass is repeated. ECC syndrome of horizontal codeword is SRAM
When stored in step 15, the flow diagram of FIG. 7E is executed and the error CRC syndrome is updated in steps 117 and 126. If the horizontal codeword ECC syndrome is not stored in the SRAM 15, the flowchart of FIG. 7C is executed, and the error CRC syndrome is updated in steps 71 and 81.

The flow diagram of FIG. 7K illustrates the steps of determining whether the product code has been completely corrected, or whether the product code is uncorrectable at the end of a horizontal or vertical pass. In step 252, the system waits for the ECC_BUSY flag to be cleared before checking the BLK_UNC flag. If in step 254 the block uncorrectable flag (BLK_UNC) is not set, indicating that no uncorrectable error has been encountered during a previous horizontal or vertical pass, the correction procedure is performed in the prior art. Step 258 exits the flow as successful without taking another pass as required.

When the BLK_UNC flag is set in step 254, the pass count variable P is set in step 256.
ASS_CNT is incremented and PASS_CN
If T exceeds a predetermined maximum, the product code becomes uncorrectable and the correction procedure exits the flow at step 266 as failed. If PASS_CNT is less than the predetermined maximum value in step 256 and if no changes were made in the previous horizontal and vertical passes (if no corrections were made) in step 260, no more passes may be made. Because it is useless, the correction procedure exits the flow again as a failure at step 266. If a change has been made at step 260, the BLK_UNC flag is cleared at step 262 and the correction procedure is continued at step 264 by performing another horizontal or vertical pass.

Since the CRC syndrome S _CRC is calculated concurrently with the correction of the product code, the correction procedure can be successfully completed at the end of either the horizontal or vertical pass. Therefore, the present invention does not require another pass required in the prior art to verify whether the correction has been completed. In addition, the present invention de-randomizes the data so that the CRC syndrome S at the end of the correction process.
_No separate path was needed to generate the _CRC . Thus, the present invention provides a significant improvement over the prior art by significantly increasing the throughput of the optical storage device.

[CRC Generator Circuit] The CRC generator and correction verifier 19 of FIG. 2 generate CRC redundancy symbols for the 16 data sectors shown in FIG. The CRC syndrome S used to verify the correction made by the error corrector 18 as described above with reference to FIGS.
Generate _CRC . FIG. 8 shows a conventional linear feedback shift register (LSFR) for generating CRC redundancy symbols during a write operation. LF shown in FIG.
The operation of SR is well known, and this LSFR divides the input polynomial D (x) by the generator polynomial G (x) shown below.

G (x) = g _i x ⁱ + g _i−1 x ⁱ⁻¹ +... + G ₁ x + g ₀ The coefficients of the input polynomial D (x) are serially shifted through the LFSR. Here, the shift number is equal to the number obtained by adding 1 to the degree of the input polynomial. The remainder, or CRC redundancy, is the final state of the shift register. To generate CRC redundancy for each of the data sectors shown in FIG. 3A, k bits of data are represented as coefficients of a polynomial P (x). Therefore, CRC redundancy is calculated as follows.

CRC redundancy = P (x) · x ^nk mod G (x) where ^nk is the number of CRC redundancy symbols and G (x)
Is a generator polynomial. The contents of the register after the last shift are CRC redundancy, which is then added to the user data to form a CRC codeword. This C
The RC codeword is embedded in the product code and then written to disk.

During a read operation, the data read from the disk is processed and a CRC syndrome S _CRC is generated according to the following equation:

CRC syndrome S _CRC = C ′ (x) modG (x) where C ′ (x) is the CR read from the disc.
C codeword (including CRC redundancy). In the prior art,
When the error corrector 14 completes the correction, the data buffer 1
Are read out from the memory and de-randomized by the de-randomizer 4. Since the non-randomized data is subsequently processed serially, the CRC syndrome S _CRC can be generated by the above equation using the same LFSR circuit in FIG.

In the present invention, as described with reference to FIGS. 7A to 7J, the CRC syndrome S _CRC is generated simultaneously with the correction of the product code. Therefore, the LFSR circuit of FIG. 8 cannot be used to generate the CRC syndrome S _CRC because the data is not processed as a series of consecutive bits. Before describing how the CRC syndrome generator of the present invention generates a CRC syndrome S _CRC , an overview of the CRC syndrome generator of the present invention will be given.

FIG._CRCCircuit 300 and E
RROR_CRC2. The CRC syndrome of FIG.
FIG. 2 is a block diagram of a game generator 19. Referring to FIG. 7A
As explained above, DATA_CRCIs the step 37
Thus, the uncorrected data read from the data buffer 1 in FIG.
Using the randomized data, the product code in FIG.
Generated during the first horizontal pass. ERROR
_CRCIs the horizontal and vertical codeword iteration.
Using the correction value generated by the error corrector 18 in between
Generated. When the end of the data sector is reached, DAT
A_CRCAnd ERROR_CRCIs the COMBINE circuit 30
4 and the final CRC syndrome S_CRC3
06 is generated. This final CRC syndrome S_CRC
306 is compared with the constant by the comparator 307 and the data section is
It is determined whether the data still contains errors. CO
The mathematical functions performed by the MBINE circuit 304 are:
DATA _CRCAnd ERROR_CRCSimple exclusive OR of
(XOR).

As described above, the product code of FIG. 3A has 16 data sectors. Therefore, the number of data CRC syndromes and error CRC syndromes stored in the SRAM 15 is 16. CRC check is SRA
Data CRC syndrome and error CRC from M15
Each syndrome is read out, and these data CR
The C and error CRC syndromes are respectively converted to a DATA _CRC circuit 300 and an ERROR _CRC circuit 30.
2 for each data sector. The comparator 307 determines whether the final CRC syndrome S
_{The CRC} is compared to a constant equal to the CRC on the pseudo-random data sequence used to randomize each data sector. Since the pseudo-random data sequence varies from block to block (product code), each time a new block is read from the storage medium, the corresponding CRC constant is loaded into comparator 307.

The data _CRC circuit 300 and ER shown in FIG.
The ROR _CRC circuit 302 is shown in more detail in FIG. The DATA _CRC circuit 300 and the ERROR _CRC shown in FIG.
The circuit 302 receives the received CRC code word polynomial C ′
A data CRC syndrome and an error CRC syndrome are generated by expressing (x) as a linear combination of a plurality of subset polynomials as follows.

C ′ (x) = C _j (x) + C _j−1 (x) +... + C ₀ (x) where each subset polynomial C _k (x) is a codeword polynomial C ′ ( x) contains a predetermined number of bits. In the embodiments disclosed herein, each subset polynomial includes the eight bits of the codeword polynomial C ′ (x) and is represented in hexadecimal as follows:

[0137]

(Equation 23) In this way, the CRC syndrome S _CRC can be conceptually generated as a linear combination of the CRC syndrome of each subset polynomial as follows.

CRC syndrome S _CRC = C ₀ (x) mo
dG (x) + C ₁ (x) modG (x) + ... + C
_j (x) mod G (x) The above equation can also be expressed as follows.

[0139]

(Equation 24) here,

(Equation 25) Is an 8-bit polynomial from the codeword C ′ (x) (ie,

(Equation 26) Is). Another mathematical relationship used in the present invention is:

[0140]

[Equation 27] Referring again to FIG. 3B, using the above equation, the data CRC syndrome for the first symbol 160 of the first data sector during the first pass on the horizontal codeword is calculated. The first symbol 160 is the most significant coefficient of the codeword C ′ (x) and the subset polynomial C _j (x)
Contains the non-zero coefficient of. The first symbol 160 is (adder 310 with zero padding the most significant bit).
10) and loaded into the 32-bit register 308 of FIG. Thereafter, the next symbol 140 of the codeword of FIG. 3B is read, and the multiplier 312 multiplies the contents of register 308 by x ^K modG (x), shifting the data CRC syndrome one symbol right (ie, one symbol right). , K = R1 in step 146 of FIG. 7F). Thereafter, the result of the multiplication is expressed by (adder 310, symbol 1 next to the codeword).
(After starting the CRC syndrome calculation for that particular subset polynomial)
8 is reloaded. This calculation is performed on the remaining symbols and continues until the last symbol 148 of the first horizontal codeword in FIG. 3B is read. Then the CRC
The syndrome stores x ^K modG in the contents of the register 308.
By multiplying by (x), it is adjusted to the location 150 in FIG. 3B. Here, K is equal to the symbol to the right (ie, K = R1 in step 146 of FIG. 7F).
An appropriate value of the offset K is determined by S 3 of the multiplier 312 in FIG.
Selected via the EL control line.

This process continues until the last symbol of the last horizontal codeword of the first data sector in FIG. 3B is read, and the register 308 stores the first symbol of the CRC codeword C ′ (x) ( That is, the subset polynomial C
_j (x)), including the data CRC syndrome that is added to the data CRC syndrome calculated for the other symbols (ie, the other subset polynomials), thereby forming the first data sector. A data CRC syndrome for the entire CRC codeword C ′ (x) is generated. At this time, the data CRC syndrome for the first data sector is located at the last symbol 152 in FIG. 3B. Once the flow diagram of FIG. 7F has been executed again and the first symbol 204 of the next data sector has been processed, at step 138 of FIG.
The data CRC syndrome for the first data sector is stored in SRAM 15 and the first symbol 204 of the next data sector is loaded into register 308. The above process is repeated for the second and subsequent data sectors, at the end of the first horizontal pass, 1
All six data CRC syndromes are generated and S
It is stored in the RAM 15.

ERR of FIG. 9 for generating an error CRC
OR _CRC circuit 302 also includes the circuit of FIG. FIG.
When the correction value is generated by the error corrector 18 of this example, the correction value is added to the register 308 by the adder 310. Multiplier 312 determines whether a correction value is generated when each symbol of the horizontal or vertical codeword is being processed (ie, even if the correction value is zero),
Continue multiplying the contents of register 308 by the appropriate K offset. At the end of each data sector, the data CRC syndrome and the error CRC syndrome are combined to generate a final CRC syndrome S _CRCJ . As described above, this final CRC syndrome S _CRCJ is used to determine whether the correction is valid and complete.

The x ^K mod G (x) multiplier 312 shown in FIG.
A preferred embodiment for realizing is understood with reference to FIG. FIG. 11 shows a table of the remainder generated by the calculation of x ^{K + i} mod G (x). here,
i is equal to {0, ..., 31}. The table of FIG. 11 is generated for each of the K offset values (ie, R1, D1 and UP12_R1) used during the calculation of the CRC syndrome. Thereafter, the register 30 of FIG.
The multiplication is performed by multiplying the contents of 8 by the appropriate table (ie, by multiplying a 32-bit vector by a 32 × 32 matrix).

The actual table for implementing the multiplication of x ^K mod G (x) for the 32-bit CRC generator polynomial G (x) is shown in the VHDL source code of FIGS. 13A-13E. "Constant r1_dvd_
The table denoted as “tbl” implements a one symbol right shift (R1) adjustment, and “constant d1_
The table shown as “dvd_tbl” implements a one-row down shift (D1) adjustment and “constant”
The table indicated as “u12r1_dvd_tbl” has a shift of one symbol right by 12 symbols (UP12_R1).
Realize the adjustment.

The remainder of the VHDL source code of FIGS. 13A-E is multiplied by the appropriate table to the contents of register 308 of FIG.
Multiply by two matrices) to perform the actual multiplication. The product of the input register or vector and matrix is the output vector, where each element of the output vector is the n elements of the ith row of the table (ie, matrix) and the n It is generated by summing the products with the corresponding components. This sum can be expressed as follows.

[0146]

[Equation 28] Where y _i is the output vector of multiplier 312,
a _ik is the 32 bits of the i-th row in the table of FIG. 11, and x _k is 3 bits stored in the register 308 of FIG.
Two bits. Output vector y _i from multiplier 312
Is added to the input bits at adder 310, and the result is stored in register 308.

[SRAM] The structure and operation of the SRAM 15 of FIG. 2 can be understood with reference to FIG. 12A. As described above, the SRAM 15 performs two functions depending on the operation mode. That is, in the CD mode, the SRAM 15
Providing data buffering for C1 / C2 encoding;
In the DVD mode, the SRAM 15 stores the ECC syndrome for the product code and the CR for the CRC verification code.
The C syndrome is stored. In the preferred embodiment in the DVD mode, only 182 vertical ECC syndromes of the product code shown in FIG. 3A are stored in the SRAM 15 together with 16 CRC syndromes corresponding to 16 data sectors. DVD product code 208
The horizontal ECC syndromes are regenerated on each horizontal pass and are not stored in SRAM 15.
One skilled in the art will recognize that this configuration is merely a particular embodiment and that S
The capacity of the RAM 15 is changed according to the vertical and horizontal ECC.
It will be appreciated that the syndrome, and the CRC syndrome, can be increased to store.

Referring to FIG. 12A, SRAM 15 is
More preferably, 16 256 × 8 bit memory cells 314
₀~ 314_FifteenIs realized as a bank. Each memory cell
Is 8 bits to access 256 data bytes
Outputs the input address and the addressed data byte.
And an 8-bit output bus. Address decryption
The converter 316 is configured to operate via a control line 317.
Decodes 12-bit address 318 depending on operation mode
Become In the case of the CD mode, the memory cell 314 ₀~ 31
4_FifteenBanks are addressed as 4k x 8-bit buffers.
Specified. That is, the 12 bits of the address 318 are all
8 bits for C1 / C2 decoding.
Access tabibytes. First 8 bits of address 318
The memory cell 314₀~ 314_FifteenSame from each of
Used to select data bytes. Memory cell
Output of the tri-state buffer 320₀~ 320_Fifteen
Is wired-ORed. address
Using the remaining 4 bits of 318,
Buffer 322 is enabled so that bus 322
Above, the appropriate data bytes used for C1 / C2 decoding
Assert

In the case of the DVD mode, the SRAM 15
Addressed as a 56 × 128 buffer. That is, using only the first 8 bits of the address 318, selects the same data byte from each memory cell 314 _{0-314 15.} The 16 data bytes output from each memory cell are combined at 324 to form 16 ECC syndromes of the vertical codeword as shown in FIGS. 5 and 6B, or as shown in FIG. 3A. Form 4 bytes of CRC syndrome for the data sector.

A preferred mapping of the vertical ECC and CRC syndromes for the DVD mode is shown in FIG. 12B. The first 182 addresses are used to store 16 ECC syndromes of 182 vertical codewords. The next ten addresses are skipped and addresses 192 to 207 are the 4-byte data CRC syndrome and error CRC for the 16 data sectors of the DVD product code of FIG. 3A.
It is used to store 16 syndromes. Accessing the data CRC syndrome and the error CRC syndrome using the addresses 192 to 207 simplifies the decoding circuit because only the three least significant bits of the address are changed. The rest of the SRAM 15 is not used in the DVD mode.

[0151] The objects of the present invention have been fully realized by the embodiments disclosed herein. Those skilled in the art will recognize that various embodiments can achieve various aspects of the present invention without departing from the essential function of the invention. For example, while the product code shown in FIG. 3A is typically used on a digital video disc (DVD), the present invention provides a compact disc (CD)
Is equally applicable to other product code formats, including those used for Further, the present invention can be applied not only to product codes, but also to other multidimensional codes. Thus, the specific embodiments disclosed herein are illustrative and are not meant to limit the scope of the invention, which is properly construed by the appended claims. .

[0152]

According to the present invention, at least the following effects can be obtained.

First, by performing a CRC check on the randomized data, the latency associated with accessing the data buffer for non-randomizing the data before generating the CRC syndrome is avoided.

Further, by generating a CRC syndrome during execution simultaneously with the correction of the P and Q code words,
Immediately after processing the RC codeword, the CRC syndrome is made available to check the validity and completeness of the correction. This eliminates the need to access the data buffer to generate a CRC syndrome.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional error correction system typically used in a CD / DVD optical storage device.

FIG. 2 is a block diagram of the error correction system of the present invention having a CRC generator and a correction verifier that generates a CRC syndrome on the fly for random data.

FIG. 3A is a diagram showing a format of a product code typically used in a DVD optical storage device having 16 data sectors.

FIG. 3B shows the format of the first two data sectors of the product code of FIG. 3A.

FIG. 3C is a diagram showing details of a data randomizer / non-randomizer used in the present invention.

FIG. 3D is a diagram showing details of a data randomizer / non-randomizer used in the present invention.

FIG. 4 is a diagram illustrating a detailed circuit for generating a horizontal codeword error syndrome according to the first embodiment of the present invention;

FIG. 5 is a diagram showing a detailed circuit for generating a vertical codeword error syndrome simultaneously with generation of an error syndrome for a horizontal codeword.

FIG. 6A illustrates a circuit for updating the horizontal and vertical error syndromes, respectively, when the syndrome buffer stores error syndromes for both horizontal and vertical codewords, for another embodiment of the present invention.

FIG. 6B illustrates a circuit for updating the horizontal and vertical error syndromes, respectively, when the syndrome buffer stores error syndromes for both horizontal and vertical codewords, for another embodiment of the present invention.

FIG. 7A is a flowchart outlining the steps performed by the error correction system of the present invention.

FIG. 7B is a flow diagram for simultaneously generating horizontal and vertical error syndromes during a first pass for horizontal codewords and simultaneously generating CRC syndromes for checking the validity and completeness of corrections for product codes. .

FIG. 7C is a flow diagram for correcting a horizontal codeword during a first (and subsequent) horizontal pass and updating the vertical error syndrome stored in a syndrome buffer and a CRC error register with the correction value.

FIG. 7D corrects a vertical codeword during a vertical pass using a vertical error syndrome stored in a syndrome buffer, and uses the corrected value to provide a syndrome buffer and a CRC.
5 is a flowchart for updating a horizontal error syndrome stored in an error register.

FIG. 7E corrects the horizontal codeword during the next horizontal pass using the horizontal error syndrome stored in the syndrome buffer, and uses the correction value to
5 is a flowchart for updating a vertical error syndrome stored in a C error register.

FIG. 7F illustrates data C during a first horizontal pass for a full product code.
5 is a flowchart for generating an RC syndrome.

FIG. 7G is a flowchart for updating an error CRC syndrome using a correction value during a horizontal pass.

FIG. 7H is a flowchart for updating an error CRC syndrome using a correction value during a horizontal pass.

FIG. 71 is a flow diagram for updating an error CRC syndrome using a correction value during a vertical pass.

FIG. 7J is a flowchart for updating an error CRC syndrome using a correction value during a vertical pass.

FIG. 7K is a flow diagram for combining the contents of the CRC data register and the contents of the CRC error register to generate a final CRC syndrome for checking the validity and completeness of the correction at the end of the horizontal and vertical passes.

FIG. 8 shows a conventional linear feedback shift register (LFSR) used to generate CRC redundancy during a write operation and a CRC syndrome during a read operation.
FIG.

FIG. 9 shows a DATA _CRC circuit for calculating a data part of a CRC syndrome, an ERROR _CRC circuit for calculating an error part of the CRC syndrome, and a DATA _C circuit.
FIG. 9 is a block diagram of a CRC correction verification circuit having a circuit for combining a _RC register and an ERROR _CRC register to generate a final CRC syndrome S _CRC that is compared to a constant equal to the CRC for the random data pattern.

FIG. 10 is a detailed block diagram of a DATA _CRC / ERROR _CRC circuit of FIG. 9;

FIG. 11 is a diagram showing a general form of a matrix for a multiplier to calculate x ^K MOD G (x).

FIG. 12A shows the structure of an SRAM and how the SRAM is configured while decoding a C1 / C2 code for storing a partial syndrome for a CD format and a product code, and a CRC verification code for a DVD format. FIG.

FIG. 12B shows a vertical E in a preferred embodiment of the present invention.
SR of CC syndrome and CRC verification syndrome
It is a figure showing AM mapping.

FIG. 13A is a diagram showing VHDL source code for generating an actual table for realizing multiplication of x ^K modG (x) for a 32-bit CRC generating polynomial G (x).

FIG. 13B is a diagram showing VHDL source code for generating an actual table for realizing multiplication of x ^K modG (x) for a 32-bit CRC generation polynomial G (x).

FIG. 13C is a diagram showing VHDL source code for generating an actual table for realizing multiplication of x ^K modG (x) for a 32-bit CRC generating polynomial G (x).

FIG. 13D is a diagram showing VHDL source code for generating an actual table for realizing multiplication of x ^K modG (x) for a 32-bit CRC generating polynomial G (x).

FIG. 13E is a diagram showing VHDL source code for generating an actual table for realizing multiplication of x ^K modG (x) for a 32-bit CRC generating polynomial G (x).

[Explanation of symbols]

 Reference Signs List 1 data buffer 3 line 4 randomizer / non-randomizer 7 C1 encoder / decoder 8 C2 encoder / decoder 9 interleaver / non-interleaver 15 SRAM 16 P / Q decoder 17 ECC / Syndrome generator 18 error corrector 19 CRC generator and correction verifier 20 lines 21 lines

 ────────────────────────────────────────────────── ─── Continuation of front page (71) Applicant 595158337 3100 West Warren Avenue, Fremont, California 94538, U.S.A. S. A.

Claims (24)

[Claims] An error correction processor for correcting an error in randomized data read from a disk storage medium, wherein the randomized data is The ECC redundancy symbol and a check symbol generated for the data before being randomized, the error correction processor comprising: (a) using the ECC redundancy symbol to generate the randomized data; An ECC decoder for correcting errors therein; (b) a syndrome generator for generating a verification syndrome in response to the randomized data; and (c) a predetermined value for the verification syndrome. The validity of the correction to the randomized data (validit
y) and a correction verifier to verify the integrity; and (d) the correction verifier indicates that the correction to the randomized data is valid and complete, and then A non-randomizer for non-randomizing the data. 2. The method according to claim 1, wherein (a) said randomized data is
Including first and second sets of intersecting codewords; and (b) said ECC decoder sequentially passing said first set of codewords and said second set of codewords.
2. The error correction processor according to claim 1, wherein the error correction processor corrects an error in the randomized data. 3. The syndrome generator generates a data verification syndrome during a first pass for the first set of codewords, and (b) the syndrome generator generates the data verification syndrome during a first pass on the first set of codewords. Generating an error verification syndrome using the correction value generated by the ECC decoder to correct the data, and (c) combining the data verification syndrome with the error verification syndrome. 3. The error correction processor according to claim 2, wherein a final verification syndrome is generated that is compared with the predetermined value. (A) at the same time as the ECC decoder processes the randomized data, the syndrome generator generates a partial verification syndrome; and (b) the syndrome generator generates the partial verification syndrome. 3. The error correction processor according to claim 2, further comprising an offset controller for adjusting said partial verification syndrome in response to the position of a particular randomized data symbol being processed by the decoder. 5. The ECC decoder generates a correction value for correcting a randomized data symbol, wherein: (a) the offset controller determines the partial value according to a position of the corrected data symbol. 5. The error correction processor of claim 4, wherein: adjusting a verification syndrome; and (b) the syndrome generator updates the partial verification syndrome with the correction value. 6. The check symbol is generated according to a generator polynomial G (x) of a finite area, and (b) the offset controller multiplies the partial verification syndrome by X ^K mod G (x). Adjust the partial verification syndrome, where K is the offset value and the mod operator is modulo divis
5. The error correction processor according to claim 4, wherein the error correction processor performs ion). 7. The error correction processor according to claim 1, wherein: (a) the check symbol is generated according to a generator polynomial in a finite area; and (b) the predetermined value is based on the generator polynomial. 8. The non-randomizer generates a random pattern according to a predetermined seed value, and (b) combines the random pattern with the randomized data to generate the random pattern. 2. The error correction processor according to claim 1, wherein the randomized data is non-randomized. 9. The error correction processor according to claim 8, wherein (a) the check symbol is generated according to a generator polynomial in a finite area; and (b) the predetermined value is based on the generator polynomial and the random pattern. . 10. The error correction processor of claim 1, wherein the check symbols are generated according to a cyclic redundancy code (CRC). 11. A method for correcting an error in randomized data read from a disk storage medium, wherein the randomized data includes an ECC generated for the randomized data. A redundant symbol and a check symbol generated for the data before being randomized, the method comprising: (a) using the ECC redundant symbol to correct an error in the randomized data; (B) generating a verification syndrome in response to the randomized data; and (c) comparing the verification syndrome with a predetermined value to enable correction of the randomized data. Verifying the correctness and completeness; and (d) after the correction verifier indicates that the correction to the randomized data is valid and complete, Comprising a step of non-randomized data, method. 12. The method according to claim 12, wherein: (a) said randomized data comprises first and second sets of intersecting codewords; and (b) said correcting comprises: The method according to claim 11, wherein errors in the randomized data are corrected by processing a second set of codewords in a sequential pass. 13. The step of generating the verification syndrome comprises: (a) generating a data verification syndrome during a first pass for the first set of codewords; and (b) the randomized syndrome. Generating an error verification syndrome using a correction value for correcting data; and (c) combining the data verification syndrome with the error verification syndrome to generate a final verification syndrome that is compared with the predetermined value. Generating.
3. The method according to 2. 14. The step of generating the verification syndrome includes the steps of: (a) processing the randomized data to generate an ECC error syndrome and simultaneously generating a partial verification syndrome; Adjusting the partial verification syndrome in response to the location of a particular randomized data symbol being processed to generate an ECC error syndrome. 15. The step of generating the verification syndrome includes: (a) adjusting the partial verification syndrome according to the position of the corrected data symbol; and (b) correcting the data symbol. Updating the partial verification syndrome with the correction value. 16. The step (a) wherein the check symbol is generated according to a generator polynomial G (x) of a finite area; and (b) the step of adjusting the partial verification syndrome comprises: X ^K modG (x The method of claim 14, comprising multiplying by K), where K is an offset value and the mod operator performs remainder division. 17. The method of claim 11, wherein (a) the check symbol is generated according to a finite domain generator polynomial; and (b) the predetermined value is based on the generator polynomial. 18. The non-randomizer generates a random pattern according to a predetermined seed value, and (b) combines the random pattern with the randomized data to generate the random pattern. The method of claim 11, wherein the data is non-randomized. 19. The method of claim 18, wherein (a) the check symbol is generated according to a finite domain generator polynomial; and (b) the predetermined value is based on the generator polynomial and the random pattern. 20. The method of claim 11, wherein the check symbols are generated according to a cyclic redundancy code (CRC). 21. An error correction processor for correcting an error in data read from a disk storage medium, wherein the data includes an ECC redundant symbol and a check symbol, wherein the error correction processor comprises: a) an ECC decoder for correcting an error in the data using the ECC redundant symbol; and (b) a syndrome generator for generating a verification syndrome in response to the data. A) a correction verifier for comparing the verification syndrome with a predetermined value to verify the validity and completeness of the correction for the data; and (d) a correction verifier for correcting the randomized data. A non-randomizer for de-randomizing the data after indicating that the data is valid and complete. 22. An error correction processor for correcting an error in randomized data read from a disk storage medium, wherein the randomized data comprises:
An ECC redundancy symbol generated for the randomized data and a check symbol generated for the data before being randomized, the error correction processor comprising: (a) reading from the disk; A data buffer for storing the randomized data, and (b) connected to receive the randomized data from the data buffer, for correcting an error in the randomized data. An ECC decoder for generating an ECC error syndrome and a correction value; and (c) the randomizing data from the data buffer at the same time that the ECC decoder receives the randomized data from the data buffer. A syndrome generator connected to receive the verified data and generating a verification syndrome; and (d) the verification syndrome. A correction verifier for comparing the ROHM with a predetermined value to verify the validity and completeness of the correction to the randomized data; and (e) rewriting the randomized data from the data buffer. A non-randomizer for non-randomizing the randomized data after the correction verifier is connected to receive and indicates that the correction to the randomized data is valid and complete. And an error correction processor. 23. The error correction processor of claim 22, wherein the verification syndrome is generated according to a cyclic redundancy code (CRC). 24. The syndrome of claim 22, wherein the syndrome generator updates the verification syndrome with a correction value generated by the ECC decoder when a randomized data symbol is corrected. Error correction processor.