JP2000306342A - Error correcting encoding apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an error correcting encoding apparatus which can generate encoded data without executing error correcting encoding again even when a recording point is shifted to a succeeding area because of a recording error or the like in a recording system to recording media required to operate in real time. SOLUTION: A data error detection code is added to inputted data, which is stored in a first memory means 102. A parity is generated by a first parity generation means 103. The data are thus error-corrected and encoded. Meanwhile, pattern data determined uniquely to an inputted data ID are generated, error-corrected and encoded and stored in a second memory means 105. The error corrected encoded data in the first memory means 102 and error-corrected encoded pattern data in the second memory means 105 are added by an adding means 107, whereby encoded data are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction coding apparatus for performing error correction coding using a linear code in an error correction method for correcting an error occurring in a recording medium.

[0002]

2. Description of the Related Art In recent years, DVDs (Digital Ver.
With the increase in the capacity of optical disks, magneto-optical disks, and the like, including satellite disks, various applications such as moving image recording are being considered.

FIG. 14 shows an example of a conventional error correction coding device used in a DVD recording device. As a DVD standard, ECMA-272 “120 mm DVD Re
rewritable Disk (DVD-RAM) ", and p. 14 to p. 19 describes a DVD error correction coding system.

In FIG. 14, reference numeral 1401 denotes a data ID
Data ID error detection code adding means, 1402 is a data error detection code adding means, 1403 is a scrambling means, 1
Reference numeral 404 denotes a storage unit, and 1405 denotes a parity generation unit.

[0005] An error correction encoding procedure for input data in the error correction encoding apparatus of FIG. 14 will be described.

First, a data ID and a data ID error detection code are added to the data input by the data ID / data ID error detection code adding means in sector units. Further, the data error detection code adding means adds a data error detection code. Subsequently, the scrambling means adds a scrambling pattern uniquely determined by the data ID and stores it in the storage means.

The data stored in the storage means is error-correction-coded every 16 sectors which is a unit of error correction coding of DVD. The error correction code of DVD is a product code of Reed-Solomon code, and has 208 inner codewords and 182 codewords.
It is a linear code composed of two outer codewords. Therefore,
The error correction coding is performed by generating the parity of these inner / outer codewords by the parity generator and storing it in the memory.

The data for which the error correction coding has been completed is output as coded data and recorded on a recording medium.

[0009]

However, there may be cases where recording cannot be performed due to local defects or the like in the recording medium.
If the recording fails, it will be recorded at another location in the recording medium.However, in a system that requires real-time properties such as moving image recording, the decrease in recording rate should be minimized. It is advantageous to adopt a method of recording in a subsequent recording area in order to suppress it. However, when the recording area is shifted to the subsequent area, it is necessary to change the data ID to the succeeding area, and the scramble pattern changes with the change of the data ID. In the apparatus, the processing is started again from the addition of the data ID / data ID error detection code. For this reason, it takes time to perform error correction encoding and generate encoded data, and as a result, the recording rate is reduced. In particular, in a product code such as a DVD having a large unit of error correction coding, the time possessed by the error correction coding becomes large,
The reduction in the recording rate due to the re-execution of the error correction coding becomes remarkable.

[0010] The present invention has been made in view of this point,
When the recording area is shifted to the subsequent area, the data I
It is an object of the present invention to provide a method of error correction coding that does not require re-execution of error correction coding even when D changes.

[0011]

In order to solve the above-mentioned problems, the present invention provides a method in which a data error detecting code is added by a data error detecting code adding means and a data ID is generated by a pattern generating means. This is an error correction encoding apparatus that individually encodes error correction codes of pattern data and adds them to generate encoded data.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION
The data and the pattern data depending on the data ID to be added to the data are individually error-correction-coded sequentially and the error-correction-coded data are individually added to generate coded data. For this reason, even when the data ID is changed to a subsequent one, the error correction coding is performed by adding the error correction coding of the data and the error correction coding of the pattern data corresponding to the subsequent data ID. The encoded data can be generated without redoing the above.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 shows a configuration of an error correction coding apparatus according to Embodiment 1 of the present invention. In FIG. 1 storage means, 103 is a first parity generation means, 104 is a pattern generation means, 105 is a second storage means, 106 is a second parity generation means, and 107 is an addition means.

Hereinafter, the operation of the error correction encoding apparatus of FIG. 1 will be described, and then an example of configuring the error correction encoding apparatus in the DVD format will be described. First, a data error detection code is added to the data input by the data error detection code adding means 101. The data error detection code is added to detect an error included in the data after error correction decoding during data reproduction, and is used to determine whether the error correction decoding is normal. The data to which the data error detection code has been added is stored in the first storage means 102. Parity is added to the data stored in the first storage unit 102 by the first parity generation unit 103 and error correction coding is performed.

Further, pattern data uniquely determined by the input data ID is generated by the pattern generation means 104 and stored in the second storage means 105. Parity is added to the pattern data stored in the second storage unit 105 by the second parity generation unit 106 and error correction coding is performed.

Subsequently, the data stored in the first storage means 102 and the data stored in the first storage means 102 are subjected to error correction coding and error correction coding, and the data stored in the second storage means 105 are added by the addition means 107. Generate encrypted data.

FIG. 2 shows an example of the operation of generating coded data in the error correction coding apparatus according to the present embodiment. In the operation example of FIG. 2, data d1, d2,.
2, and so on. Here, data IDs corresponding to L1, L2,... On the recording medium are i1, i2,.
, And pattern data uniquely determined for the data IDs i1, i2,. The data d1, d2,... Added with a data error detection code and subjected to error correction coding are D1, D2,..., And the pattern data p1, p2,.
P2, ...

First, when data d1 is recorded in L1 on the recording medium, as described above, data error detection code adding means 101, first storage means 102, and first parity generation means 103 detect data error in data d1. A code is added to generate an error correction code D1, and the first storage means 10
2 is stored. Further, the pattern generation means 104, the second storage means 105, and the second parity generation means 106 generate P1 in which pattern data uniquely determined for the data IDi1 is error-corrected and stored in the second storage means 105. The generation of D1 and P1 is completed before the recording on L1 on the recording medium is started. Thereafter, the adder 107 adds D1 and P1 to generate encoded data, and records the encoded data in L1 on the recording medium.

Similarly, in order to record data d2 and d3, encoded data is generated by generating and adding D2 and D3 and P2 and P3, and recording the encoded data in L2 and L3 on the recording medium. Here, it is assumed that recording failed in recording on L3 due to a defect in the recording medium. In this case, the data d3
Is shifted to L4 on the recording medium, and is recorded.
This is performed by recording the encoded data generated by adding D3 and P4 in L4 on the recording medium. The generation of D3 and P4 required at this time is completed before the recording to L4 starts irrespective of the success or failure of the recording, and the generation of the encoded data is not delayed due to the failure of the recording.

.. And P5, P6,.
5, L6, ....

Next, an example of the configuration of an error correction encoding apparatus in the DVD format according to the present embodiment will be described.

The error correction code of the DVD is a prime field GF (2)
Is the product code of the Reed-Solomon code on the extended field in which the root α of the primitive polynomial (Equation 1) is added, and is composed of 208 inner codes and 182 outer codes.

[0024]

(Equation 1)

The unit of the error correction code of the DVD is 16 sectors, and FIG. 3 shows the structure. Each sector includes a data ID, a data ID error detection code, a reserve, user data, and a data error detection code.
Parities of the inner code and the outer code are added in sector units.

FIG. 4 shows a data error detecting code adding means 101.
This is an example of the configuration. The data error detection code of the DVD is a polynomial a by regarding a data ID, a data ID error detection code, a reserve, and a bit sequence of user data as coefficients of a polynomial.
(X) is obtained by extracting each coefficient of the polynomial obtained by (Equation 2).

[0027]

(Equation 2)

In FIG. 4, 401 to 432 are 1-bit storage elements, 441 to 443 are adders, 451 is a switch, and 461 is an output selection unit. The operation of the data error detection code adding means in FIG. 4 will be described. The data error detection code adding means generates a data error detection code on the assumption that the data ID and the data ID error detection code are 0. Therefore, the reserve and user data are input as input data in a bit sequence. First, the storage elements 401 to 432 are cleared to 0, and the switch 451 is turned on. The output selection unit 461 is set to select and output input data. Then, reserve and user data are sequentially input in bit units. When the reservation and the input of the user data are completed, the switch 451 is turned off, the output selection unit 461 is set to select and output the output of the storage element 432, and the values of the storage elements 431 to 401 are sequentially output. , A data error detection code is added. The data to which the data error detection code is added is stored in the first storage means 102. At this time, the data ID area and the data ID error detection code area in FIG.

FIG. 5 shows an example of the configuration of the first parity generation means 103. In FIG. 5, reference numeral 501 denotes a first parity generation unit, 502 denotes a second parity generation unit, and 503 denotes an output switching unit. The error correction code of the DVD is a product code, and the parity generation method differs between the inner code and the outer code. Therefore, the first parity generation unit 501 that generates the parity of the inner code and the second parity generation unit 502 that generates the parity of the outer code
Switch to use. FIG. 6 shows the first parity generation unit 50.
FIG. 7 shows an example of the configuration of the second parity generation unit 502. In FIG. 6, 601 to 610 are 8-bit storage elements, 621 to 630 are coefficient multipliers,
650 is an 8-bit adder. 7, reference numerals 701 to 716 denote 8-bit storage elements, and 721 to 716.
36 is a coefficient multiplier, and 741 to 756 are adders.

In the configuration example of FIG. 6, the operation of (Equation 3) is performed on a polynomial B (X) using each byte of input codeword data as a coefficient, and each coefficient of the polynomial of the operation result is extracted. Generates the parity of the inner code.

[0031]

(Equation 3)

Similarly, in the configuration example of FIG. 7, the operation of (Equation 4) is performed on the polynomial C (X) using each byte of the input codeword data as a coefficient, and each coefficient of the polynomial of the operation result is calculated. The parity of the outer code is generated by extracting.

[0033]

(Equation 4)

The operation of error correction coding using the parity generation means of FIG. 5 will be described. First, in order to generate the parity of the inner code, the first output is used as the output of the output switching unit 503.
The output of the parity generation unit 501 is selected. Next, with respect to the data of 16 sectors to which the data error detection code stored in the first storage means 102 is added, the data from the first row to the 192nd row in FIG. Enter in the means. The input data at this time is 172 bytes per line. The parity generated by the parity generation unit in FIG. 5 is stored in the inner code parity area of the same row as the input data in the first storage unit 102.

Subsequently, the output of the second parity generation section 502 is selected as the output of the output switching section 503 in order to generate the parity of the outer code. Next, the data from the first column to the 182nd column in FIG. 3 of the first recording unit 102 is input to the parity generation unit in FIG. 5 for each column. The input data at this time is 192 bytes per column. Also, 1
In the 73rd to 182nd columns, the parity of the already generated inner code is input. The parity generated by the parity generation unit in FIG. 5 is stored in the outer code parity area in the same column as the input data in the first storage unit 102.

FIG. 8 shows an example of the configuration of the pattern generating means 104. 8, reference numeral 801 denotes a data ID holding unit;
2 is a counter section, 803 is a data ID error detection code addition section, 804 is a data error detection code generation section, 805 is a seed generation section, 806 is a shift register, 807 is an adder,
Reference numeral 808 denotes an output switching unit. In the configuration example of FIG. 8, the data ID, the data ID error detection code, the user data, and the data error detection code in FIG. 3 are generated and output in sector units. Hereinafter, the operation will be described.

The input data ID is held in the data ID holding unit 801 and then held in the counter unit 802. In the counter unit 802, 1 is added for each sector.
This value becomes the data ID of the sector. Data ID error detection code adding section 803 adds a data ID error detection code to the output of counter section 802. The DVD data ID error detection code is obtained by extracting each coefficient of the polynomial obtained by (Equation 5) when the data ID is regarded as a polynomial D (X).

[0038]

(Equation 5)

FIG. 9 shows a data ID error detection code adding section 80.
3 is a configuration example. In FIG. 9, 901 and 902 are 8
Bit storage elements, 911 and 912 are coefficient multipliers, 92
1 and 922 are adders, and 931 is an output selector. FIG.
In the configuration example, first, the values of the storage elements 901 and 902 are set to 0, and the output selection unit 931 is set so that the input data ID is output. Next, a data ID is input in byte units. Thereafter, the values of the storage elements 901 and 902 at the time when the input of the data ID is completed are output as the data ID error detection code via the output selection unit 931.

The data ID to which the data ID error detection code has been added by the data ID error detection code addition section 803 is input to the data error detection code generation section 804 to generate a data error detection code. The data error detection code generated here is a data error detection code calculated when the reserve and user data in FIG. 3 are set to 0, and the data ID and the bit sequence of the data ID error detection code are represented by a polynomial e.
When it is considered as (x), each coefficient of the polynomial obtained by (Equation 6) is extracted.

[0041]

(Equation 6)

FIG. 10 shows a data error detection code generator 804.
This is an example of the configuration. In FIG. 10, 1001 to 1032
Is a 1-bit storage element, and 1041 to 1053 are adders. In the configuration example of FIG. 10, first, 1001 to 1032
After setting the value of the storage element to 0, the data ID and the data I
D error detection codes are sequentially input in bit units. Data I
1 when input of D and data ID error detection code is completed
The values of the storage elements 001 to 1032 are output as data ID error detection codes.

The scramble pattern of the DVD is generated by the portion composed of the shift register 806 and the adder 807 in FIG. The initial value of the shift register when generating the scramble pattern is defined as shown in Table 1 by bits 4 to 7 of the fourth byte of the data ID. However, the set value number in the table is the fourth of the data ID.
This is the value of bit 4 to bit 7 of the byte.

[0044]

[Table 1]

The seed generator 805 includes a counter 802
, An initial value to be set in the shift register 806 is generated. The generated initial value is set in the shift register 806, and the lower 8 bits of the shift register 806 are output. Thereafter, the operation of shifting the shift register 806 left eight times and then outputting the lower 8 bits of the shift register 806 is repeated for a total of 2048 bytes.

Output switching section 808 outputs data according to the sector structure in FIG. That is, the output of the data ID error detection code adding unit 803 is selected as the data ID and the data ID error detection code, 0 is selected as the reserve, the output of the shift register 806 is selected as the user data, and the data is detected as the data error detection code. The output of the error detection code generation unit 804 is selected and output as pattern data. The generated pattern data is stored in the second storage unit 105.

The pattern data stored in the second storage means 105 is subjected to error correction coding using the second parity generation means 106. The configuration example of FIG. 5 can be used as the second parity generation unit 106 similarly to the first parity generation unit 103. The procedure of error correction encoding of the pattern data stored in the second storage means 105 is as follows.
2 can be performed using the second parity generation means 106 in the same manner as the error correction coding procedure for the data stored in the second parity generation section.

By outputting the encoded data while adding the error-correction-encoded data of the first storage means 102 and the error-correction-encoded pattern data of the second storage means 105 by the addition means 107, the DVD format is obtained. Can be configured.

(Embodiment 2) FIG. 11 shows the configuration of an error correction coding apparatus according to Embodiment 2 of the present invention. In FIG. 1 storage means, 1103 is a first parity generation means, 1104 is a first pattern generation means, 1
105 is a second parity generation unit, 1106 is a second storage unit, 1107 is a second pattern generation unit, and 1108 is an addition unit.

After the operation of the error correction coding apparatus of FIG. 11 is described below, an example when configuring the error correction coding apparatus in the DVD format will be described. First, a data error detection code is added to the data input by the data error detection code adding means 1101. The data to which the data error detection code is added is stored in the first storage unit 1102. Parity is added to the data stored in the first storage unit 1102 by the first parity generation unit 1103 and error correction coding is performed.

The pattern data uniquely determined by the input data ID is stored in the first pattern generation unit 1104.
And the parity for the pattern data is generated by the second parity
It is stored in the storage unit 1106. At this time, if a product code is used as the error correction code, the second storage unit 11
06 stored in the second parity generation means 110
5 to generate a parity at a portion where the inner code parity and the outer code parity intersect.
06.

Further, the pattern data uniquely determined by the input data ID is stored in the second pattern generating means 110.
7.

Subsequently, the adding means 1108 outputs the second
The parity for the pattern data stored in the storage unit 1106 is combined with the pattern data generated by the second pattern generation unit 1107 to form an error correction code, and the error correction encoded data stored in the first storage unit 1102 To generate encoded data.

Next, an example of the configuration of the error correction coding apparatus in the DVD format according to the present embodiment will be described.

The data error detection code adding means 1101 can be realized with the configuration example of FIG. 4 as in the first embodiment, and the first parity generation means 1103 can also be realized with the configuration example of FIG. 6 as in the first embodiment. . Also, the procedure for error correction encoding the input data and storing it in the first storage means 1102 is the same as in the first embodiment.

FIG. 12 shows an example of the configuration of the first pattern generating means 1104 in the present embodiment. In FIG.
01 is a data ID holding unit, 1202 is a counter unit, 12
03 is a data ID error detection code addition unit, 1204 is a data error detection code generation unit, 1205 is a seed generation unit, 12
06 is a shift register, 1207 is an adder, 1208 is a 15-bit storage element, 1209 is an adder, and 1210 is an output switch.

In the configuration example of FIG. 12, the data of the area excluding the inner code parity and the outer code parity in FIG. 3 can be generated in both the horizontal direction and the vertical direction. First, generation of data in the horizontal direction is performed by a data ID holding unit 1201, a counter unit 1202, a data ID error detection code addition unit 1203, and a data error detection code generation unit 1203.
4, the seed generating unit 1205, the shift register 1206, the adder 1207, and the output switching unit 1210 are operated in the same manner as the configuration example of the pattern generating unit in the first embodiment shown in FIG. Next, a case where vertical data is generated will be described. As for the method of generating the data ID, the data ID error detection code, and the data error detection code, the data unit corresponding to the output data is generated by the counter unit 1202 as in the case of generating the horizontal data.
A data ID error detection code adding unit 1203 adds a data ID error detection code to the data ID,
A data error detection code generation unit 1204 generates a data error detection code. To generate a scramble pattern in the vertical direction, first, bit 4 of the fourth byte of the data ID is used.
The seed generation unit 1205 generates the setting values shown in (Table 2) according to bits 7.

[0058]

[Table 2]

The set values in (Table 2) are
In this case, the value of the shift register 1206 at the time of shifting leftward 96 times by 06 becomes the set value in (Table 1). The set value generated by the seed generation unit 1205 is set in the shift register 1206. Shift register 12
Reference numeral 06 shifts left eight times every time the generation of the scramble pattern of one column is completed. After setting the value of the shift register 1206, the storage element 1208 outputs the lower 8 bits. After that, the value of the storage element 1208 is added to the addition unit 120.
9 and outputs the output of the adder 1209 again to the storage element 12.
08 and outputs the lower 8 bits. However, the input bits i14 to i0 of the adder 1209 and the output bit o14
The relationship of ~ o0 is as shown in (Table 3).

[0060]

[Table 3]

The data is input to the adder 1209 and the storage element 1
The operation of updating the value of 208 and outputting the lower 8 bits is further repeated 10 times to output a total of 12 bytes of data. After outputting 12 bytes of data, the operation of setting the value of the shift register 1206 to the storage element 1208 is repeated 15 times, thereby outputting a total of 192 bytes of data. This 192 bytes of data becomes a scramble pattern for one column. When the output of the scramble pattern for one column is completed, the shift register 12
06 is shifted left eight times to generate a scramble pattern for the next column. This is repeated to generate a scramble pattern for a total of 172 columns.

In the output switching unit 1210, the data ID
By selecting and outputting the outputs of the error detection code adding unit 1203, the data error detection code generation unit 1204, and the storage element 1208 according to the sector structure of FIG. 3, vertical pattern data is output.

The pattern data generated by the first pattern generating means 1104 is
5 to generate a parity for the pattern data. The second parity generation unit 1105 can be realized by the configuration example of FIG. 5 similarly to the first parity generation unit 1103. The generated parity is stored in the second storage unit 1106. Further, the inner code parity for the 192 code words stored in the second storage unit 1106 is stored in the second parity generation unit 11 for each column.
05, and generates a parity at a portion where the inner code parity and the outer code parity intersect, and stores it in the second storage unit 1106.

The second pattern generating means 1107 can be realized by the configuration example of FIG. 8 similarly to the pattern generating means 104 of the first embodiment.

Finally, the adding means 1108 outputs the second
The pattern data output from the pattern generation unit 1107 and the parity of the pattern data stored in the second storage unit 1106 are combined to form an error correction code for the pattern data, and the error stored in the first storage unit 1102 is formed. The encoded data is generated by adding the corrected encoded data.

As described above, the DV according to the present embodiment
An error correction encoding device in the D format can be configured.

(Embodiment 3) FIG. 13 shows the configuration of an error correction encoding apparatus according to Embodiment 3 of the present invention. In FIG. Means, 1303 is a first parity generating means, 1304 is a first pattern generating means, 130
5 is a second parity generation unit, 1306 is a second pattern generation unit, and 1307 is an addition unit.

In this embodiment, the first storage means 1102 and the second storage means 1106 in the second embodiment are the same memory, that is, a single storage means 1302. In the second embodiment, the data stored in the second storage unit 1106 is only the parity for the pattern data, and is very small compared to the data amount stored in the first storage unit 1102. Therefore, even if a single storage unit is divided and used, the bandwidth required for the storage unit does not change so much, and the configuration of the present embodiment is possible.

The operation in the present embodiment is performed by
By dividing the two areas and making them correspond to the first storage means 1102 and the second storage means 1106 in the second embodiment,
This is the same as in the second embodiment.

[0070]

As described above, according to the present invention, in a system for adding pattern data uniquely determined by a data ID corresponding to a recording position and then performing error correction coding, the data ID is shifted to a succeeding one. However, encoded data can be generated without redoing error correction encoding. For this reason, in a system that requires real-time properties such as recording of a moving image, even when recording is shifted to a subsequent location due to failure in recording on a recording medium,
Encoded data can be output without interruption,
There is an effect that a decrease in the recording transfer rate due to a recording failure can be suppressed low.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing an operation example according to the first embodiment of the present invention;

FIG. 3 is a diagram showing a configuration of a DVD format error correction code.

FIG. 4 is a diagram showing a configuration example of a data error detection code adding unit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example of a first parity generation unit according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration example of a first parity generation unit according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration example of a second parity generation unit according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a configuration example of a pattern generation unit according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a configuration example of a data ID error detection code adding unit according to the first embodiment of the present invention.

FIG. 10 is a diagram showing a configuration example of a data error detection code generation unit according to the first embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 12 is a diagram showing a configuration example of a first pattern generation unit according to the second embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a third embodiment of the present invention.

FIG. 14 is a diagram showing an example of the configuration of a conventional error correction encoding device.

[Explanation of symbols]

Reference Signs List 101 Data error detection code adding means 102 First storage means 103 First parity generation means 104 Pattern generation means 105 Second storage means 106 Second parity generation means 107 Addition means 401 to 432 Storage elements 441 to 443 Adders 451 Switch 461 Output Selection unit 501 First parity generation unit 502 Second parity generation unit 503 Output switching unit 601 to 610 8-bit storage element 621 to 630 Coefficient multiplier 641 to 650 8-bit adder 701 to 716 8-bit storage element 721 to 736 Coefficient multiplication Units 741 to 756 8-bit adder 801 Data ID holding unit 802 Counter unit 803 Data ID error detection code addition unit 804 Data error detection code generation unit 805 Seed generation unit 806 Shift register 807 Adder 808 Output switching unit 90 , 902 8-bit storage element 911, 912 Coefficient multiplier 921, 922 8-bit adder 931 Output selector 1001-1032 Storage element 1041-1053 Adder 1101 Data error detection code adding means 1102 First storage means 1103 First parity generation Means 1104 First pattern generation means 1105 Second parity generation means 1106 Second storage means 1107 Second pattern generation means 1108 Addition means 1201 Data ID holding section 1202 Counter section 1203 Data ID error detection code addition section 1204 Data error detection code generation section 1205 seed generation unit 1206 shift register 1207 adder 1208 15-bit storage element 1209 addition unit 1210 output switching unit 1301 data error detection code adding unit 1302 storage unit 1303 first Parity generating means 1304 first pattern generating means 1305 second parity generating means 1306 second pattern generating means 1307 adding means 1401 data ID / data ID error detecting code adding means 1402 data error detecting code adding means 1403 scrambling means 1404 storage means 1405 parity Generation means

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Makoto Usui 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F-term (reference) 5J065 AA01 AB01 AC03 AD01 AD11 AD13 AG01 AH02 AH06 AH19 5K041 AA08 CC01 CC04 FF36 GG02 GG11 HH12 JJ28

Claims (3)

[Claims] A first storage unit for storing data including a data area, a data error detection code area, and a parity area; and generating data with a data error detection code to which data is input and to which a data error detection code is added. A data error detection code adding unit to be stored in a data area and a data error detection code area of the first storage unit; and a first parity generated from the data of the first storage unit, and a parity area of the first storage unit. A first parity generation unit for storing data composed of a pattern data area and a parity area; and a pattern data area generated by inputting a data ID. Generating a second parity from the data in the second storage means, and generating a second parity from the data in the second storage means. Error correction, comprising: a second parity generation means for storing data in the storage area; and an addition means for adding the data in the first storage means and the data in the second storage means to generate encoded data. Encoding device. 2. A first storage means for storing data comprising a data area, a data error detection code area, and a parity area, and generating data with a data error detection code to which data is input and to which a data error detection code is added. A data error detection code adding unit to be stored in a data area and a data error detection code area of the first storage unit; and a first parity generated from the data of the first storage unit, and a parity area of the first storage unit. A first parity generating means for storing data constituted by a parity area; a first pattern generating means for generating first pattern data by inputting a data ID; Second parity generating means for generating a second parity from data in the second storage means and storing the second parity in a parity area of the second storage means; A second pattern generation unit that generates second pattern data by using the data ID as an input; and generates encoded data by adding the data of the first storage unit, the data of the second storage unit, and the second pattern data. An error correction coding device comprising an adding means for performing the correction. 3. The error correction encoding device according to claim 2, wherein said first storage means and said second storage means are configured as the same memory.