JP2001189059A - Recording/reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the occurrence of retry in a disk recording/reproducing device. SOLUTION: A post processor 114 generates syndrome by using a parity bit in a modulation code bit line, and performs error detection/correction to output the syndrome to a vanishing position calculation circuit 121. The vanishing position calculation circuit 121 estimates an error byte position and the number of error byte pieces from the syndrome, and specifies decode operation of an RS decoder 122 to either one among error correction, vanishing correction and a corrective operation stop, according to large/small of the number of estimated error pieces. The RS decoder 122 doesn't decode an RS code language in a present sector when the corrective operation stop is specified, to output the regenerative data as it is. As the result, the retry due to a decode bad isn't performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing apparatus, and more particularly, to a method for controlling a digital reproduction signal processing circuit of a magnetic disk drive.

[0002]

2. Description of the Related Art Conventionally, this kind of reproduced signal processing circuit has been used for the purpose of lowering a bit error rate (BER) of a reproduced bit string in a magnetic disk, an optical disk or the like. The reproduction signal of the magnetic disk is
First, in the reproduction signal processing circuit, a signal having a continuous signal level at a continuous time is converted into a signal having a discrete time binary {0, 1}. In this circuit, the Partial Response Maximum
Likelihood (PRML) signal processing is generally performed. PRML lowers the BER compared to signal determination by conventional signal peak detection. After the reproduced signal passes through the PRML circuit, it is input to the error correction code decoder. The BER of the decoder output sequence of the error correction code is lower than the BER of the same input sequence, and the BER approaches zero. Thus, reproduced bit data having no bit error is output from the magnetic disk device.

In recent years, a reproduction signal processing method based on PRML signal processing and adding various processing thereto has been proposed. For example, the method described in U.S. Pat.
This is a method in which a post-processing circuit called a post processor is added to RML, and has the following two features.

(1) A parity bit is added to a part of a code word of a modulation code, and a reproduction side calculates a syndrome using the bit, thereby detecting occurrence of an error bit.

(2) Only when the occurrence of an error bit is detected by the syndrome calculation, the post processor uses the difference signal between the input and output signals of the Viterbi detector to
Identify the error pattern and error location that occurred.

[0006] The method described in the above document is based on the PR
BER can be reduced compared to ML. This prior art scheme is referred to below as parity post-processing.
(Parity-Post Process: P-PP) method.

The P-PP method will be described with reference to FIGS. First, a channel until data is recorded on a magnetic disk will be described with reference to FIG. FIG. 1 is a block diagram showing a recording channel of a magnetic disk, and data Data to be recorded in the device is a CRC (Cyclic Redundancy Check) calculation circuit 101.
Calculates the CRC remainder byte and appends the remainder byte to the data. Next, the data is Reed-Solomon (Reed-So
lomon) encoder: Encoded in the RS encoder 102.
Similar to the CRC encoding, the RS encoding is performed by obtaining a remainder byte obtained by dividing data by a generator polynomial of the RS code, and adding the remainder to data before encoding. Thereafter, the data after the RS encoding is rearranged in the interleaver 103 in byte units. On the reproducing side, the reverse operation of the rearrangement is performed, and when a bit error on a burst occurs in the magnetic recording / reproducing process, the error is converted into a random error, so that the BER is reduced. The output of interleaver 103 is input to randomizer 104, where a pseudo-random sequence is added and the weights of bits 0 and 1 of the data are averaged. The randomizer output is input to modulator 105. In modulator 105, modulation encoding is performed on the recording data, the CRC remainder byte, and the RS remainder byte.
As the modulation code, 8/9 modulation, 16/17 modulation, or the like is used. The modulation coded sequence is output to precoder 106, where I
-Conversion of NRZI (Interleaved-Non Return to Zero Inversion) is performed. The precoder output sequence is input to the parity calculation circuit 107, where one-bit parity is calculated for each bit length determined here, and added to the bit string. For example, when one parity bit is added to four 16/17 modulation codes, that is, 68 bits, the code length of the modulation code is 69 bits. The parity calculated by the parity calculation circuit is transmitted to the post processor 11 in the reproduction channel.
In step 4, it is used to determine the presence or absence of an error bit in the recording / reproducing process. After the parity is calculated and added, the data is converted to the level of the recording current Iw according to the bits 0 and 1, and is recorded on the magnetic recording medium by the recording head in the magnetic recording / reproducing process.

Next, a conventional technique of a channel for reproducing data from a recording medium of a magnetic disk will be described with reference to FIG. In FIG. 9, the read head output signal R is first set to AGC (Automatic G
ain Controller) 110, PR4 (Partial Response Class 4) signal of appropriate signal level via PR4 equalizer 111,
That is, the signal is amplified to a signal that takes three values at the signal identification time.
Equalized. Next, the signal is converted to an EPR4 signal (Ex) by a 1 + D converter 112 (D represents a delay operation for a required time of one bit transmission).
The EPP4 signal is subjected to Viterbi detection by the EPR4 Viterbi detector 113 to become a signal VDOUT of bits 0 and 1 by tender detection. VDOUT matches the pattern of the recording current Iw in FIG. 1 if there is no noise or the like in the recording / reproducing process. VDOUT is input to post processor 114. In addition, the post processor 114 receives the PR4 signal PR4 Signal via the delay element 123, and also receives the signal Bit Count regarding the bit position in the sector generated by the bit counter 124 from the PR4 Signal before passing through the delay element 123. Is done.

The operation of the post processor 114 will be described with reference to FIG. Note that, in FIG. 3, arrows drawn with Syndrome upward from the top of the post-processor 114 are not used in the conventional technology, and therefore are not described in the following column of the conventional technology. The arrows are ignored.

[0010] Figure 3 shows the structure of a post-processor 114, the post-processor as shown in the figure syndrome calculating circuit 135, error correction circuit 136,1-D ² calculation circuit a is converter 137, an adder 138, 1 + D converter 139, error detection circuit
It consists of 140. Viterbi detector output signal VDOUT is subjected to 1-D ² converted by the converter 137. 1-D represents the signal conversion in the differentiation operation, that is, the reproduction process of the longitudinally recorded signal. 1 + D represents a transfer function of the PR4 equalizer.
That is, the output signal of the converter 137 is equal to the Viterbi detector 113 for EPR4.
Is a PR4 equalizer output signal reproduced from the output bit string. On the other hand, PR4 Signa
l is also entered. The adder 138 calculates a difference signal PR4 Error between the output signal of the converter 137 and PR4Signal. If there is no error or other error in the magnetic recording / reproducing process, PR
4 Error becomes zero. However, in practice, there are various causes of errors in the recording / reproducing process, and the PR4 Error becomes large especially when the Viterbi detector 113 outputs a bit string different from the recording bits (incorrect). 1 + D converter 139 is PR4 Er
ror is converted to an error sequence EPR4 Error after EPR4 equalization, and EPR4
Error is input to the error detection circuit 140.

In FIG. 3, the error detection circuit 140
Among the error bit patterns output from the EPR4 Viterbi detector 113, a plurality of frequently occurring patterns are set, and the function of calculating the autocorrelation coefficient of the frequently occurring error bit patterns is provided. When the error bit pattern appears in EPR4 Error, the autocorrelation coefficient output value reaches a peak at the position where the error bit pattern occurs. Position: Error
Bit T and information on which error bit pattern corresponds to which autocorrelation coefficient showed a peak: Error T
ype is output to the error correction circuit 136 once every time the code length of the modulation code is transmitted. The signal Bit Count input to the error detection circuit 140 is used to identify a codeword break of the modulation code.

In FIG. 3, VDOUT is a syndrome calculation circuit 135.
, Where the syndrome Syndrome is calculated based on the parity once for the code length. For example, if the code length is 69
In the case of bits, the syndrome is obtained by the following calculation.

[0013]

(Equation 1)

In the equation (0), b (i), i = 1, 2,..., 69 is the value of each bit in the modulation codeword and is 0 or 1. If the syndrome is non-zero, an odd number of errors has been detected. In fact, most of the error bit patterns output from the EPR4 Viterbi detector are odd. Therefore, the occurrence of a bit error in the output sequence of the EPR4 Viterbi detector 113 can be detected by this syndrome calculation. Sy explained so far
The ndrome, VDOUT, ErrorType, and Error Bit Location are input to the error correction circuit 136. The error correction circuit 136 is a Syndro
Bit position in VDOUT Error Bit only if me is non-zero
In Location, add the bit pattern specified by Error Type to VDOUT on Mod2 (mod2 represents the remainder when the numerical value is divided by 2). As a result, the bit error in VDOUT is corrected, and the corrected sequence Corrected is output.

Returning to FIG. 9, the signal Corrected, in which the error has been corrected by the post processor 114, has its parity bit removed by a parity removing circuit 115, and 1 + D
^{After the two} conversions are performed, the demodulator 117, the inverse randomizer 118,
The data is returned to the data array before recording via the deinterleaver 119. Thereafter, a CRC remainder bit is obtained by a CRC remainder calculator 301. If this is not zero, the RS decoder 302 performs decoding (error correction) of the RS code.

[0016]

A first problem of the prior art is that, in an RS code word (data and RS surplus bytes) constituting a certain sector, as many error bytes as possible exceed the correction capability even by one byte occur. Then, a retry (reproducing a recording signal of the same sector twice or more) occurs. At the time of retry, the data in the sector that cannot be decoded is reproduced again and error correction is attempted, but when the retry is performed, the number of lost sectors decreases instead of the time until the disk reproduction signal is output from the device. , At least one disk revolution. This signal delay becomes a problem particularly when the magnetic disk device is used as a recording medium for data that requires a real-time reproduction operation such as audio / video data. That is, if the processing algorithm for the audio / video data is configured in consideration of the retry, the control regarding the time delay in the audio / video processing algorithm increases, and the algorithm becomes more complicated. Also, if retries occur frequently, the reproduction of audio / image becomes discontinuous, which causes a deterioration in sound quality / image quality.

The second problem is that the post processor 1 shown in FIG.
In 14, the error detection circuit 140 does not always specify the bit error position correctly.

The reason is that the error detection circuit 140 specifies the error position Error Bit Location based on the correlation coefficient. The error detection circuit 140 calculates the autocorrelation coefficient of the difference between the signal EPR4 Error and the specific bit pattern, and monitors the magnitude of the calculation result.However, since the signal EPR4 Error can take various values depending on recording and reproduction conditions, Specifying an error position using a correlation coefficient is more difficult than specifying an algebraic error position.
The probability of erroneously specifying the error position increases. If the error location is incorrectly specified, the P-PP increases the number of bit errors, so that a small specific error leads to a large BER degradation.

The present invention has been made to solve the above problems, and has the following objects.

An object of the present invention is to prevent a decoding operation from being performed on an error correction code when the occurrence of an erasure error exceeding the erasure correction capability of an error correction code is estimated during a reproduction operation of a magnetic disk, thereby enabling a retry operation. It is to suppress the occurrence.

Another object of the present invention is to prevent the error correction code from performing a decoding operation when an erasure error exceeding the erasure correction capability of the error correction code occurs during a reproducing operation of the magnetic disk, thereby causing a retry. It is to suppress.

Another object of the present invention is to reduce the BER degradation after error correction code decoding due to the increase in the number of error bits even if the error bit position is erroneously specified and the number of error bits is increased in the parity coding post-processing method. Is to prevent.

[0023]

In order to solve the above-mentioned problems, the present invention is directed to a modulator for converting a data bit into a recording modulation bit string including a parity bit, and a demodulator for performing an inverse conversion thereof. Means for calculating a value (syndrome) for detecting the occurrence of a bit error at the time of recording / reproducing on the data reproducing side using the generated parity bit, and error estimation for estimating the number of error bytes and the error byte position from the syndrome. Means, an error-correcting code encoder and decoder, and an error-detecting code encoder and detector. When an error occurrence is identified by the error-detecting code detector, the error-correcting code Is changed according to the number of errors and the error position estimated by the error estimating means.

According to a second aspect of the present invention, when the code word of the error correction code includes the estimated error byte, the presence or absence of an error bit in the error byte position is specified for each error correction code word. It is characterized by having specific means. According to a third aspect of the present invention, the presence of an error bit in the error correction codeword is confirmed by the specifying means, and the estimated number of error bytes is larger than the error correction codeword's correction capability or a value exceeding the error correction codeword by a predetermined value. In this case, a first output means for outputting the estimated error byte position to a decoder of the error correction code for each codeword is provided. The invention according to claim 4 is characterized in that when the identification means confirms the presence of an error bit in an error correction codeword and the estimated number of error bytes exceeds the erasure correction capability of the error correction codeword, the error correction It is characterized by having second output means for outputting to the code decoder that decoding is impossible for each codeword. In the invention according to claim 5, the error detection code is a code using a CRC (Cyclic Redundancy Check) remainder byte, and the error correction code is a code using a Reed-Solomon code. It is characterized by.

As described above, the recording / reproducing apparatus of the present invention
The recording channel has means for generating a parity bit for the modulation code, and the reproduction channel has means for calculating a syndrome from the parity bit.

The present invention also relates to a post processor (see FIG. 2).
It has a function of estimating an error byte position in a sector from the syndrome generated by 114).

Further, the present invention has means for estimating the number of error bytes in a sector from the generated syndrome.

Further, according to the present invention, when the estimated error byte is included in the RS code word, the error bit in the error byte position is corrected by the P-PP error correction circuit (136 in FIG. 3). In order to judge whether or not the error bit is present, a means for identifying the presence or absence of an error bit (means for calculating a remainder byte of the CRC) is represented by R
It has for every S code word. For example, if one sector is encoded by three RS code words, three CRC remainder byte calculation means are provided.

Further, according to the present invention, the above means performs estimation of an error byte position, estimation of the number of error bytes, identification of the presence or absence of an error in an RS code word input to an RS decoder, and calculation of the RS remainder by CRC remainder calculation. Only when the presence of error bits in the code word is confirmed and the estimated number of error bytes is larger than the correction capability of the RS code word or a value slightly more than that, the RS code decoder estimates the error byte. There is means for outputting an error byte position for each codeword.

Further, according to the present invention, the above means performs estimation of an error byte position, estimation of the number of error bytes, identification of the presence or absence of an error in an RS code word input to an RS decoder, and calculation of the RS remainder by CRC remainder calculation. Only when the presence of error bits in the code word is specified and the estimated number of error bytes exceeds the erasure correction capability of the RS code word, it is determined for each code word that the RS code cannot be decoded by the decoder. Output means.

Next, the operation of the present invention will be described with reference to FIG. FIG. 8 shows an encoding format of the RS code on the recording channel side of one sector of the magnetic disk, and one square indicates one byte (8 bits). In one sector, 512 bytes of data, a CRC remainder byte, and an RS code remainder byte are recorded. In FIG. 8, the data bytes are divided into three equal parts in three rows in the horizontal direction from the upper left end in the figure, and data1, data2,…, dat
It is written as a512. The CRC remainder bytes are CRC1 (1), C
RC1 (2), etc., 2 bytes in each line, total 6 bytes, RS code remainder bytes are ECC1 (1), ECC1 (2),…, ECC1 (8) etc., 8 bytes in each line, total 24 bytes I have.

In FIG. 8, one line indicates one codeword of the RS code. That is, recording data bytes data1, data2,…, da
RS encoding is performed on ta171, and RS remainder byte ECC1
(1), ECC1 (2), ..., ECC1 (8) are generated. The above 1
CRC of 16th-order generator polynomial for 71 data bytes
The remainder bytes CRC1 (1) and CRC1 (2) are generated. Similarly, ECC2 (1), ECC2 (2),…, ECC2 (8) and CRC2 (2), CR for the recording data bytes data172, data173, ..., data342
C2 (2) is generated and data343, data344,…, data512
ECC3 (1), ECC3 (2),…, ECC3 (8) and CRC3
(1), CRC3 (2) are generated.

Each byte in FIG. 8 is recorded on the disk in units of columns after the CRC bytes and ECC bytes are generated in units of rows. In other words, sectors on the disk include data1, data172, data343, data2, data173,
data344,…, data342, CRC3 (1), CRC1 (1), CRC2
(1),…, CRC2 (2), ECC3 (1), ECC1 (1), ECC2 (1),
…, Each byte is recorded in the order of ECC2 (8). The reason that RS and CRC are encoded on a line basis in FIG. 8 and then recorded on the disk so that the bytes in the direction of FIG. 8 are continuous is to convert a burst error into a random error by performing deinterleaving on the reproducing side. It is. If a burst error occurs during the magnetic recording / reproducing process, the burst error
(Column direction 8). When this error is viewed on a row basis in FIG. 8, if the burst error in the column direction is not long, it is a random error.

Since the RS code shown in the example of FIG. 8 has eight ECC remainder bytes, its correction capability can be set to four. That is, this RS code has the ability to correct up to four error bytes generated in one row of FIG. Suppose 4 in a line
When an error byte exceeding the byte occurs, the error in the row is not corrected, and the sector including the code word is a target sector for retry. The erasure correction capability of this RS is 8
It is. That is, if error positions of up to 8 bytes per row in FIG. 8 are given to the RS decoder before decoding, the RS decoder can complete decoding and no retry occurs. In order to avoid retry occurrence, which is the object of the present invention, when the number of error bytes per line may exceed 4 in FIG. 8, even if the number of error bytes does not actually exceed 4, error detection If a byte position having a high probability is sent to the RS decoder as an erasure position and erasure correction is performed on the RS code based on the erasure position, retry can be avoided.

In order to know the position of a byte having a high probability of error in the RS decoder input byte sequence before RS decoding, the Parity-Post Process method (PP
(P method) is used. The syndrome is calculated for each modulation codeword in the syndrome calculation circuit 135 of FIG. If the syndrome is non-zero, the bit sequence after EPR4 equalization and Viterbi detection of the playback signal
It is found that an odd number of bit errors occur in the (modulation codeword sequence) (the number of errors in the dominant error bit pattern after EPR4ML detection is an odd number). Even if the bit error occurs, most of the error bits are corrected by the error correction circuit 136 in FIG. However, as pointed out as a second problem in the section of “Problems to be Solved by the Invention”, some error bits remain uncorrected by the error correction circuit 136 even if the syndrome becomes non-zero. Output from the post processor 114. That is, when the syndrome of a certain modulation code becomes non-zero,
Data bytes after the modulation codeword has been demodulated (by demodulator 117) are relatively likely to be incorrect. Therefore, it is considered that the data byte having a high error probability is designated as an erasure position and the RS decoder performs erasure correction.

Returning to FIG. 8, the modulation encoding of the data bytes is performed in the order of recording in the sector. Suppose now that modulation coding is performed in units of three data bytes. That is, data1, data172, and data343 are encoded into the first modulation codeword, and data2, data173, and data344 are encoded into the second modulation codeword (one row in FIG. 8 is assigned to one modulation codeword). This modulation and coding method is performed up to the rightmost column in FIG. In the present invention, if the syndrome of the second modulation code becomes non-zero, for all three RS code words,
Designate the second byte of those to be lost.

Further, for the input byte sequence of the RS code word,
If the CRC check is performed before RS decoding, the erasure error position can be specified in more detail. This is because the CRC remainder calculation is performed in the row direction in FIG. 8 (similar to the decoding of the RS code). As a result of the syndrome calculation, even if a certain column is designated as a lost byte, if the remainder of the CRC divider becomes all zero, no bit error occurs in the modulation codeword regarded as the lost byte (see FIG. The error bit has been corrected by the error correction circuit 136). For example, if the lost byte is considered as the second three bytes in the sector (data2, data173, data344),
If only data2 contains an error, the CRC inspection results in the second and third rows are all zero. In this case, erasure correction may be performed only when decoding the RS code word in the first row. For this purpose, it is necessary to independently calculate the CRC remainder bytes for the recording data of each row before recording.

As for the parity of the modulation codeword, as shown in FIG. 8, in the case of a format in which one sector is composed of three RS codewords, one parity is added to each three bytes after modulation and encoding. Thus, it is possible to specify lost bytes in units of columns (units of bytes when viewed in the row direction).

Finally, the number of lost bytes and the control of the RS decoder will be described. The RS code correction capability is t [bytes], and the erasure correction capability is 2t [bytes]. As a result of the syndrome calculation in the P-PP, even if the number of lost bytes exceeds t, most of those errors have been corrected by the error correction circuit 136 in FIG. The number of bytes is likely to be smaller than t. Therefore, when the number of lost bytes greatly exceeds t, the RS decoder is first sent the lost byte position to perform the erasure correction. Even if the number of lost bytes exceeds 2t, the number of error bytes in the RS decoder input byte sequence is likely to be 2t or less (however, it is highly likely that the correction capability t is exceeded). However, since the erasure position cannot be narrowed down to 2t or less, erasure correction of RS is impossible. In this case, there are two possible solutions. First, the retry of the sector is repeated until data that can be corrected is reproduced from the sector. Second, for an RS code word that cannot be decoded, the recording data byte is output as it is or is replaced with some data from the RS decoder, and no retry is performed. The second method can be said to be a particularly effective method for a magnetic disk device for recording audio / image data. The reason is that, even if a part of the audio / image data is lost, only a slight disturbance of the sound quality / image quality is required. On the other hand, if the first method is selected, when the byte error rate is deteriorated, retries are frequently repeated, so that sound quality and image quality are frequently interrupted with time, and the usability of the device is rapidly deteriorated.

[0040]

1 to 9 show an embodiment of the present invention.
The description will be made with reference to FIG.

(1) Recording channel

FIG. 1 shows a recording channel of a magnetic disk. Data Data to be recorded in the device is stored in a CRC (Cyclic Redunda).
The CRC remainder byte is calculated in the ncy check) calculation circuit 101, and the remainder byte is added to the data. The data is then encoded in a Reed-Solomon (RS) encoder 102. RS encoding is similar to CRC encoding in that data is
This is performed by obtaining the remainder byte divided by the S-code generation polynomial and adding the remainder to the data before encoding. these
CRC remainder calculation and RS coding are performed in units of one sector (512 bytes). The data so far is confirmed using FIG.
The CRC calculation circuit 101 and the RS encoder 102 in FIG. 1 independently perform CRCk (i), ECCk
(j), i = 1, 2, j = 1, 2,…, 8, k = 1, 2,
Calculate 3.

Next, the data after the RS encoding is rearranged in units of bytes in interleaver 103, and data1,
data172, data343, data4, data173, data344,
... are rearranged in this order. The output of interleaver 103 is input to randomizer 104, where a pseudo-random sequence is added and the weights of bits 0 and 1 of the data are averaged. The randomizer output is input to modulator 105. In modulator 105, modulation encoding is performed on the recording data, the CRC remainder byte, and the RS remainder byte. As the modulation code, for the reason described in the above description of the operation of the present invention, encoding is performed such that parity is generated in the same 3-byte unit as the interleave size. In this embodiment, the modulator 105 in FIG. 1 converts each column (3 bytes) in FIG.
Convert to 8/9 modulation sequence. The output bit sequence of the modulator 105 is output to the precoder 106, where the I-NRZI (Interleaved-Non
Return to Zero Inversion) is applied to the parity calculation circuit 107. In the circuit 107, the parity bit is calculated and added by one bit for every 27 bits according to the calculation shown in the equation (1), so that it is converted into a sequence of modulation code words having a code length of 28 bits.

[0044]

(Equation 2)

In Expression (1), b (i), i = 1, 2,..., 27
Represents the value (0 or 1) of each bit after 8/9 modulation encoding.
The insertion of the parity bit b (28) slightly disturbs the run length restriction of the bit '0' in the 8/9 modulation coded bit string, but has a negligible effect on the BER from the appearance frequency of the parity bit. The bit string to which the parity is added is converted into the level of the recording current Iw according to bits 0 and 1, and is recorded on the magnetic recording medium by the recording head in the magnetic recording / reproducing process.

(2) Reproduction channel

Next, an outline of a channel for reproducing data from a recording medium of a magnetic disk in the embodiment of the present invention will be described with reference to FIG. Figure 2 shows the AGC110, PR4 equalizer 11
1, 1 + D converter 112, EPR4 Viterbi detector 113, post processor 114, parity remover 115, postcoder 116, demodulator 117, inverse randomizer 118, inverse interleaver 119,
It comprises an erasure position calculation circuit 121, an RS decoder 122, a delay element 123, and a bit counter 124. 2, the components corresponding to those shown in FIG. 9 are denoted by the same reference numerals.

In FIG. 2, the reproduction head output signal R is first supplied to the AGC 11
0, PR4 of appropriate signal level via PR4 equalizer 111
The signal is amplified and equalized to a (Partial Response Class 4) signal, that is, a signal that takes three values at the signal identification time. Next, the signal is converted into an EPR4 signal (Extended PR4 signal,
The EPP4 signal is Viterbi-detected by the EPR4 Viterbi detector 113, and becomes the signal VDOUT of bits 0 and 1. VDOUT matches the pattern of the recording current Iw in FIG. 2 if there is no noise or the like in the recording / reproducing process. VDOUT is post processor 1
Entered into 14. In addition, PR4
The signal PR4 Signal is input via the delay element 123, and the signal Bit Count regarding the bit position in the sector generated by the bit counter 124 from PR4 Signal is also input. The bit counter 124 in FIG.
The function to detect the sync word from the output signal of 11 and the recording data sequence started after the sync word
It has a function of counting as 1, 2,..., And outputs the counted value as a signal Bit Count to the post-processor 114 or the disappearance position calculation circuit 121.

The operation of the post processor 114 will be described with reference to FIG. Figure 3 shows the structure of a post-processor 114, the post-processor as shown in the figure syndrome calculating circuit 135, error correction circuit 136,1-D ² a calculation circuit which converter 137, subtractor 138,1 + D converter 139, error detection circuit
It consists of 140. Viterbi detector output signal VDOUT is subjected to 1-D ² converted by the converter 137. 1-D represents the signal conversion in the differentiation operation, that is, the reproduction process of the longitudinally recorded signal. 1 + D represents a transfer function of the PR4 equalizer.
That is, the output signal of the converter 137 is a PR4 equalizer output signal reproduced from the EPR4 Viterbi detector output bit string. On the other hand, the PR4 signal is also input to the post processor 114. The adder 138 outputs the output signal of the converter 137 and
The difference signal PR4 Error from the PR4 Signal is calculated. If there is no error or other error in the magnetic recording / reproducing process, PR4
Error becomes zero. However, in practice, there are various causes of errors in the recording / reproducing process, and the PR4 Error becomes large especially when the Viterbi detector outputs a bit string different (wrong) from the recording bits. 1 + D converter 139 sets PR4 Error to E
The error sequence after PR4 equalization is converted to EPR4 Error, and the EPR4 Error
Is input to the error detection circuit 140.

Configuration of error detection circuit 140

The error detection circuit 140 will be described with reference to FIG. The error detection circuit 140 has an error filter as shown in FIG.
151, 152, multiplier 153, absolute value calculation circuits 154, 155, maximum value calculation circuits 156, 157, latches 158, 162, 164, comparator 15
9, 160, gates 161, 163, 165, 166, a comparator 167, an adder 169, and a remainder calculator 168. EP in the figure
R4 Error is input to the two error filters 151 and 152 in parallel. The substance of these error filters 151 and 152 is an FIR filter, and the tap coefficient sequence is an EPR4 Viterbi detector 11.
It is assumed that the dominant error bit pattern output by 3 is converted to an EPR4 signal. Specifically, the dominant error pattern is expressed as 1 + D + D ² and 1 using a one-bit delay operator D in the time domain of the recording current level (the output bit string of the Viterbi detector for EPR4). You. Converting these to EPR4 signals yields (1-D) (1 + D) ² , and (1-D) (1 + D) ² (1 +
D + D ² ). When the signal EPR4 Error is input to the FIR filter having the two transfer functions, if the EPR4 Error is close to any one of the series, the error filter output corresponding to the close series is either positive or negative at the error occurrence position. The peak is shown. The filter outputs E1 and E2 are input to the maximum value calculation circuit 156 via the absolute value calculation circuits 154 and 155, respectively. The maximum value calculation circuit 156 has a function of outputting a larger value among the two input values. The output signal of the maximum value calculation circuit 156 is input to the maximum value calculation circuit 157 and the comparator 159. The comparator 159 has two input terminals IN and CMP, and has a function of outputting 1 if the input value from IN is equal to or greater than CMP and outputting 0 otherwise. The latch 158 has a function of holding the previously input value until a new value is input or a clear signal is input to the terminal CL, and 0 is stored when the clear signal is input to the terminal CL. You. The maximum value of the output signals of the maximum value calculation circuit 156 is stored in the latch 158 by the circuits 157 and 159 and the latch 158, and the output signal L of the maximum value calculation circuit 159 is such that max (E1, E2) is the maximum value. It becomes 1 each time it is updated. max (*, *) represents the maximum value in parentheses.

On the other hand, E1 and E2 are also input to the comparator 160,
The output signal Type of the comparator 160 is 0 if E1 ≧ E2, and 1 otherwise. L and Type are gates 161, 163 and comparator 167
Is input to The gates 161 and 163 are connected when the signal of the input terminal G is 1
It has a function of outputting a signal from the terminal IN only when. The gate 161 outputs to the latch 162 the Type (0 or 1) at the bit position L where max (E1, E2) is maximum.
To gate 163, L and the position in the current modulation codeword Locat
ion (one of 1, 2,…, 28) is input. The position in the current codeword is created by remainder calculator 168 and adder 169. The remainder calculator 168 has a function of outputting a remainder obtained by dividing x by y with respect to input signals x and y from the terminals IN and MOD, respectively. Bit Count is the bit number in the sector, which is obtained by taking the remainder according to the modulation code length N = 28.
The bit position in the modulation codeword by adding
Convert to

Each of the latches 164 and 162 has a bit position Loca at which max (E1, E2) is the maximum in the modulation code word of length 28.
tin and the Type at that position are retained. For the Location and Type held in each latch, the Bit Count is 2
8, 56,..., Ie, when it is equal to a multiple of the modulation code length, the error correction circuit passes through gates 166 and 165, respectively (136 in FIG. 3).
Output to The comparison between the Bit Count and the modulation code length is realized using a comparator 167 (which outputs 1 when the two input values are equal). As described above, at the first bit position of a certain modulation codeword, max (E
Error Bit Location where the bit position where (1, E2) is the maximum
And its bit Type (0 or 1) is obtained. Also,
The output of the comparator 167 is latch 1 at each break of the modulation codeword.
Clear 58 to zero.

Referring back to FIG. 3, VDOUT is a syndrome calculation circuit.
135, where the syndrome is calculated based on the parity once for the code length. For example, when the code length is 28 bits, a syndrome is obtained by the following calculation.

[0055]

(Equation 3)

If the syndrome is non-zero, it is detected that an odd number of errors have occurred. In fact, most of the error bit patterns output from the EPR4 Viterbi detector 113 are
As described above, the number is odd. Therefore, the occurrence of a bit error in the output sequence of the EPR4 Viterbi detector can be detected by this syndrome calculation. Syndrome, VD explained so far
OUT, Error Type and Error Bit Location are error correction circuits 1
Entered into 36. The error correction circuit 136 detects the bit position in the VDOUT only when the Syndrome is non-zero.
In VDOU, the bit pattern specified by Error Type
Add to T on Mod2. As a result, the bit error in VDOUT is corrected, and the corrected sequence Corrected is output.

Description of error correction circuit 136

The error correction circuit 136 will be described with reference to FIG. The circuit includes a delay element 171, a selection circuit 172, a switch 173,
Pattern table 174, selection circuit 175, shift register 176
Consists of VDOUT is input to the shift register 176 in FIG. 5 after being delayed by the delay element 171 by the signal delay in the converter 139 and the error detection circuit 140 in FIG.

The Error Bit Location is input to the selection circuit 172. The selection circuit 172 has a function of outputting the input value to the terminal IN1 from the terminal OUT if the input value to the terminal CTL is 1, and outputting the input value to the terminal IN2 from the terminal OUT otherwise. If Syndrome = 1, that is, if an odd number of errors occur in the code word, the circuit 172 switches the Error Bit Location to the switch 173.
Otherwise, the value Dummy is output to the switch 173. The pattern table holds in advance error patterns (0 1 0) and (1 1 1) which are dominant in the channel, and one of these is input to the switch 173 by the selection circuit 175. The selection circuit 175 is controlled by the error type.If the error type is 0 (0 1 0), otherwise (1 1 1) is the switch 1 as the signal Correct Pattern of FIG.
Entered in 73.

The switch 173 converts the three parallel signals Correct Pattern according to the value of the Error Bit Location into one bit unit of the shift register 176 by using three signal lines continuous in position among the 30 signal lines. Output to the buffers FF1 to FF30. In FIG. 5, the signal values output from the signal lines are indicated as s (0), s (1),..., S (29). When Error Bit Location = x, three signal values s (i-
1), s (i), and s (i + 1) are set to the value of the Correct Pattern, and the other signal values are set to 0. These are simultaneously and independently transmitted to the switch 173 (i = 0, 1, 2,
…, 29). The switch 173 is input to the switch 173.
When Error Bit Location is Dummy, s (i) = 0,
i = 0, 1, ..., 29. For example, Syn
drome = 1, ErrorBit Location = 2, Error Type = 0
S (1) = 0, s (2) = 1, s (3) = 1, s (i) = 0, i
= 4, 5,…, 29 are transferred from switch 173 to shift register 17
Output to 6.

The shift register 176 has a function of storing and shifting a bit string having a length of 30 bits. Shift register 17
6 also stores a certain modulation codeword (b (1), b (2),..., B (28) as the transmission order of each bit value of the codeword) in the position shown in FIG. From the right in Fig. 5

(Equation 4) Buffer FF1 to FF3
It has the function of updating the contents of 0. In Expression (3), the addition indicates addition on mod2. With this feature, Syndrome
Is non-zero, that is, when a bit error occurs in the code word, the code word can be corrected by the bit pattern stored in the pattern table 174.

Returning to FIG. 2, the signal Corrected by the post-processor 114 whose error has been corrected has its parity bit removed by a parity remover 115, and 1 + D ²
After the conversion, the data is returned to an array of data before recording (in the order of data1, fata2,... Shown in FIG. 8) via a demodulator 117, an inverse randomizer 118, and an inverse interleaver 119, and the byte sequence C
odeword (1), Codeword (2), Codeword (3). Codew
ord (1) is the byte string in the first row of FIG. 8, that is, data1, dat
a2,…, data171, CRC1 (1), CRC2 (2), ECC1 (1),
…, ECC1 (8). Similarly, Codeword (2) and Codeword (3) are byte strings on the second and third rows in FIG. Figure 2
Then, Codeword (1) to Codeword (3) are input to the erasure position calculation circuit 121 in parallel.

In FIG. 2, Codewo is provided to the erasure position calculation circuit 121.
Bit Count and Syndrome are input in addition to rd (1) to Codeword (3). Erasure Byte Location, Erasure (1) to Erasure Erasure Byte Location
(3), Uncorrect (1) to Uncorrect (3) are generated and the RS decoder 122
It has the function of outputting to Figure 8 shows the Erasure Byte Location
Indicates the position of the lost byte in the sector. Erasure (1)-Er
In asure (3), when decoding each RS code word (each row in FIG. 8), only the signal of the number corresponding to the RS code word for performing erasure correction becomes “1”. For example, if the number of lost bytes in Codeword (1) exceeds the default value for performing erasure correction, Erasure (1)
= 1, otherwise 0. Uncorrect (1)-Unc
orrect (3) is a function that does not perform decoding when decoding each RS codeword.
Only the signal corresponding to the S code number becomes 1.

Description of the erasure position calculation circuit 121

The configuration of the erasure position calculation circuit 121 will be described with reference to FIG.
The operation will be described in detail. Figure 6 shows the remainder calculator 168, delay elements
181, 182, comparator 183, adder 184, latches 185, 190, gates 186, 188, shift register 187, adder 189, comparator
191 and 192, AND circuits 193 to 199, and division circuits (remainder calculators) div1 to div3 for CRC1 to CRC3. Also, the erasure position calculation circuit 121 is supplied with an intra-sector bit position signal Bit Cou.
nt, Syndro indicating the presence / absence of a bit error in one modulation code
me, codeword string Codeword (1) to Cod output from deinterleaver
eword (3) has been entered.

The Bit Count is delayed by the delay element 182 by a time equal to the delay time from the parity remover 115 to the deinterleaver 119 in FIG. 2, and then input to the terminal IN of the remainder calculator 168. The remainder calculator 168 has a function of obtaining a remainder obtained by dividing an input signal from the terminal IN by an input signal from the terminal MOD, and the remainder calculation circuit 168 outputs a remainder obtained by dividing Bit Count by N to the comparator 183. The modulation code length 28 is set in N. The comparator 183 has a function of outputting 1 when the two input values are equal, and outputting 0 otherwise. That is, the output signal of the comparator 183 becomes 1 only at the time when the last bit time of the modulation code word is delayed by the delay time of the delay element 182. The output signal of comparator 183 is output to adder 184 and gate 188.

An adder 184 adds two inputs, and a latch 185 is initialized to 1 each time a sector is started, and holds a previously input value until a new value is input. Having. By the adder 184 and the latch 185, the output signal ByteNumber becomes the number 1,2,... Of transmitted modulation codewords in the sector. Byte Number is a figure
Also matches the byte number in each row of 8. The transmission time of one modulation codeword is one column in FIG. 8 (24 before modulation or after demodulation).
This is because it corresponds to the transmission time of (bit).

The Syndrome is input to the gate 188 after being delayed by the delay element 181 by a time equal to the delay time from the parity remover 115 to the deinterleaver 119 in FIG. Gate 188 delays the last bit time of each modulation codeword by the delay time of delay
Outputs 1 only when yndrome = 1. The output of gate 188 is accumulated by adder 189 and latch 190, and
Error Byte Number is the total number of modulation codewords for which = 1. The gate 188 output signal is also output to gate 186. The output signal of the gate 186 is the byte position where Syndrome = 1. The byte position is a 2t-stage shift register 18.
7 and are output to the RS decoder 122 as the erasure location at the time when the reproduction of the sector ends.

The Error Byte Number is compared with Erasure Value and Uncorrect Value by comparators 191 and 192.
The comparators 191 and 192 have a function of outputting 1 when in ≧ cmp is established between the terminal IN input signal in and the input signal cmp from the terminal CMP, and outputting 0 otherwise. In the present embodiment, since the correction capability of the RS code is 4 bytes, Erasu
For reValue, specify a value of about 4 to 6, which is the same as or slightly larger than the correction ability. Also, the erasure correction ability 8 is specified in the Uncorrect Value. Comparators 191 and 192 and AND circuit 193
Erasure Enable, Uncorrect Enable
Are determined as shown in Table 1 of FIG. The two signals are input to AND circuits 194 to 199.

On the other hand, Codeword (1) to Codeword (3) are divided by CRC generating polynomials in division circuits div1 to div3, respectively, and the sum of the remainders Det (1) to Det (3) is calculated. Det (1) to Det (3) indicate the presence or absence of an error bit in the recording data of each row in FIG. 8, and are 1 if an error bit has occurred and 0 otherwise. Det (1) to Det (3) are AND circuits 194 in FIG.
To 199. The AND circuits 194 to 199 determine the following. If Erasure Enable = 1, Det (i)
= 1 only for the RS codeword number i
(i) = 1, and for other i, Erasure (i) = 0 (i = 1, 2, 3). Or Uncorrect Enable = 1
Then, Uncorrect (i) = 1 only for the RS codeword number i for which Det (i) = 1, and Unco
rrect (i) = 0 (i = 1, 2, 3).

The configuration and operation of the division circuit dvi1 will be described with reference to FIG. div1 is composed of adders 201, 201,..., one-bit delay elements 202, 202,. In this case, as shown in FIG.
vi1 is a single adder 201 to which the bit string of Codeword (1) is input, followed by five one-bit delay elements 202, followed by one adder 201 and seven one-bit delay elements 202
By forming one loop circuit with one adder 201 and four one-bit delay elements 202 following the adder 201, and forming a loop circuit with each of the adders 201, 201, 201, the mathematical expression ( The value G (x) shown in 4) is sequentially calculated. The delay element 202 has a function of shifting rightward by one bit each time a bit string of Codeword (1) is input one bit at a time, and a function of outputting the value in the element to the adder 203. Codeword (1) of 181 bytes (1448 bits)
Data1, data2, ..., data511, CRC1 (1), CRC1 in Fig. 8
At the point when 1384 bits up to (2) have been input to the leftmost delay element 202 in FIG. 7, the output signals of all the delay elements 202 in FIG. 7 are added by the adder 203, and the addition result is Det (1) Is output as If no bit error occurs in the 1384 bits, the addition result becomes zero. The division circuits div2 and div3 are the same as div1. However, for div3, the addition result at the time when CRC3 (2) in FIG. 8 is input to the leftmost delay element in FIG. 7 is output as det (3).
That is, div3 is a bit string whose remainder is div1,
It differs from div1 and div2 only in that it is 8 bits shorter than div2.

[0072]

(Equation 5)

Returning to FIG. 2, the Erasure Byte is sent to the RS decoder 122.
Location, Erasure (1) ~ Erasure (3), Uncorrect (1) ~
Uncorrect (3) is input each time the reproduction of each sector ends. Codeword (1) to Codeword (3) are also input to the RS decoder 122. The RS decoder 122 is configured by a conventional technique, and has a function of performing error correction of up to 4 bytes and erasure correction of up to 8 bytes in each RS codeword. However, the RS decoder is Erasure Byte Location (2t), Erasure (1) to Er
A decoding method for three codes per sector is determined according to asure (3) and Uncorrect (1) to Uncorrect (3). That is, Erasure
For i where (i) = 1, Erasu of RS codeword Codeword (i)
The lost byte position indicated by re Byte Location is lost and corrected,
The recording data after erasure correction is output as decoding result Data. For i where Uncorrect (i) = 1, the RS codeword Cod
Instead of starting the decoding of eword (i), the recording data part of Codeword (i) is output as RS decoding result Data as it is. At this time, the RS decoder outputs some identification signal Status as shown in FIG. 2 to indicate that there are more error bytes than the correction capability. The identification signal can be used in an image / audio data processing algorithm, particularly when the apparatus of the present invention is used for recording image / audio data. That is, if it is known in advance that an error byte is included, the image / audio data processing algorithm can perform processing to reduce the disturbance of the image / audio data.

[0074]

The first effect is to suppress the occurrence of retries during the reproducing operation of the apparatus. The second effect is that, in the parity encoding post-processing method, even if an error bit position is erroneously specified and the number of error bits is expanded, BER degradation after error correction code decoding due to the error bit number expansion can be prevented. is there.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a recording channel according to the related art and the present invention.

FIG. 2 is a diagram showing a reproduction channel of the present invention.

FIG. 3 illustrates a prior art post processor.

FIG. 4 is a diagram showing an error detection circuit used in a conventional post processor.

FIG. 5 is a diagram showing a conventional error correction circuit.

FIG. 6 is a diagram showing an erasure position calculation circuit according to the present invention.

FIG. 7 is a diagram illustrating a CRC division circuit.

FIG. 8 is an explanatory diagram of an encoding format.

FIG. 9 is a diagram showing a conventional reproduction channel using a post processor.

FIG. 10 shows Erasur obtained by the erasure position calculation circuit 121 in FIG.
5 is a chart showing a list of values of e Enable and Uncorrect Enable.

[Explanation of symbols]

101 CRC calculation circuit 102 RS encoder 103 Interleaver 104 Randomizer 105 Modulator 106 Precoder 107 Parity calculation circuit 108 Magnetic recording / reproducing process 110 AGC 111 PR4 equalizer 112 1 + D converter (1 + D) 113 EPR4 Viterbi detection 114 Postprocessor 115 Parity remover 116 Postcoder 117 Demodulator 118 Inverse randomizer 119 Inverse interleaver 121 Erasure position calculation circuit 122 RS decoder 123 Delay element 124 Bit counter 135 Syndrome calculation circuit 136 Error correction circuit 137 Converter (1- D ² ) 139 Converter (1 + D) 138 Adder 140 Error detection circuit 151, 152 Error filter 153 Multiplier 154, 155 Absolute value calculation circuit (ABS) 156, 157 Maximum value calculation circuit (MAX) 158, 162, 164 Latch 159 Comparator 161, 163, 165, 166 Gate 167 Comparator (Equal) 168 Remainder 169 Adder 171 Delay element (Delay) 172 Selection circuit 173 Switching device 174 Pattern table 175 Selection circuit 176 shift register 181, 182 delay element (Delay) 183 comparator 184 adder 185 latch 186 gate 187 shift register 188 gate 189 adder 191, 192 comparator 193 AND circuit 194 to 199 AND circuit div1 to div3 remainder calculator (division Circuit) Adder on 201 mod2 202 1-bit delay element 203 Adder

Claims (5)

[Claims] 1. A modulator for converting a data bit into a modulation bit sequence for recording including a parity bit, a demodulator for performing an inverse conversion of the data bit, and a recording / reproduction side on a data reproduction side using the generated parity bit. Value that detects the occurrence of a bit error in
Means for calculating (syndrome); error estimating means for estimating the number of error bytes and error byte positions from the syndrome; encoders and decoders for error correction codes; encoders and error detectors for error detection codes When the occurrence of an error is specified by the error detection code detector, the decoding operation of the error correction code decoder is changed according to the number of errors and the error position estimated by the error estimating means. Characteristic recording / reproducing device. 2. When the estimated error byte is included in the code word of the error correction code, the code word of the error correction code includes identification means for identifying the presence or absence of an error bit in the error byte position for each error correction code word. 2. The recording / reproducing apparatus according to claim 1, wherein: 3. When the presence of an error bit in an error correction code word is confirmed by the specifying means, and the estimated number of error bytes is larger than the correction capability of the error correction code word or a value exceeding a predetermined value. 3. The recording / reproducing apparatus according to claim 2, further comprising first output means for outputting the estimated error byte position to a decoder of the error correction code for each codeword. 4. When the presence of an error bit in an error correction codeword is confirmed by the specifying means, and the estimated number of error bytes exceeds the erasure correction capability of the error correction codeword,
4. The recording / reproducing apparatus according to claim 2, further comprising a second output unit that outputs to the decoder of the error correction code that decoding is impossible for each codeword. 5. The method according to claim 1, wherein the error detection code is a CRC (Cyclic Redun
The code according to any one of claims 1 to 4, wherein the code is a code using a residual byte, and the error correction code is a code using a Reed-Solomon code. Recording and playback device.