JPH11275042A - Pulse pattern monitoring circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pulse pattern monitoring circuit in which the increase in a circuit scale is suppressed, even if the number of signal lines is increased in monitoring a device based on a path pattern. SOLUTION: A path pattern is inserted in an idle time slot in an input data signal based on a path pattern insertion instruction signal 33 to monitor a memory 32 that outputs N output data signals 31l -31n in response to N input data signals 30l -30n . The path pattern consists of a path pattern pair, with predetermined two input data signals among the N input data signals as a pair where one path pattern is the inversion of the other path pattern. A path pattern detection section 37 extracts an output path pattern, corresponding to each input path pattern pair, based on a path pattern detection instruction signal 35 from the memory 32 which receives an input data signal to which the path pattern pair is inserted, and exclusive OR is operated to the path pattern pairs respectively to collate each path pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a path pattern monitoring circuit, and more particularly to a path pattern monitoring circuit in which a path pattern is inserted.

[0002]

2. Description of the Related Art Conventionally, in a transmission device such as a network switching device, a path pattern is used to monitor a failure in the device. For example, this path pattern is inserted into a transmission path to be monitored by inserting a specific pattern as a path pattern at a predetermined position in an input data signal composed of frames. Then, the pattern output via the transmission path to be monitored is compared with a preset path pattern, and when they do not match, an alarm signal is output to perform failure monitoring.

FIG. 6 shows an outline of the configuration of such a conventionally proposed path pattern monitoring circuit. This path pattern monitoring circuit includes an address generation circuit 11 for designating a time slot in an input data signal 10 having a frame configuration, and delaying the input signal data 10 after the data of the time slot specified by the address generation circuit 11. A data delay circuit 12 for generating a free time slot, a path pattern insertion circuit 13 for inserting a predetermined path pattern into the free time slot generated by the data delay circuit 12, and a device monitoring target based on the path pattern inserted by the path pattern insertion circuit 13. And a monitoring target unit 14 to be monitored. Further, the monitored unit 14
A path pattern separating circuit 15 for separating a path pattern from a pattern output from the output pattern, and an output data signal 16 by packing empty time slots generated by the data delay circuit 12 before input from the output pattern from which the path pattern is separated by the path pattern separating circuit 15. Adjustment circuit 1 for reproducing data
7, a path pattern check circuit 19 that compares the path pattern separated by the path pattern separation circuit 15 with a preset path pattern and outputs a monitoring output signal 18
And

In such a path pattern monitoring circuit, an empty time slot is generated in the time slot designated by the address generation circuit 11 and a predetermined path pattern is inserted as described above. The input data signal into which the path pattern is inserted is monitored by the monitored unit 14 to be monitored by the apparatus.
To enter. The path pattern portion is extracted from the time slot specified by the address generation circuit 11 added when the path pattern is inserted into the output pattern output from the monitored unit 14. The extracted path pattern is compared with a preset path pattern in a path pattern check circuit 19 to generate a monitoring output signal 18. On the other hand, the output pattern from which the path pattern has been extracted generates the output data signal 16 so as to fill the empty time slots generated by the data delay circuit 12 and reproduce the original frame configuration.

FIG. 7 is a timing chart showing an outline of the operation of the conventional path pattern monitoring circuit shown in FIG.
Here, it is assumed that the time slot “4” is specified in advance by the address generation circuit 11. In other words, in each frame at time t ₂ ~t ₈ of the input data signal 10 "ABCDEFG" is inputted (Fig. 7
(A)) During that time, the time slot "4" is designated by the address generation circuit 11 (FIG. 7 (b), 2 in FIG. 7).
0). The data delay circuit 12 generates a vacant time slot 21 by delaying data after time t ₄ corresponding to time slot “4” in each frame configuration of the input data signal 10. Further, at the same time, the time slot “4” specified by the address generation circuit 11 is added to the time slot 22 corresponding to the time t ₁ ((c) in FIG. 7). A path pattern “P” 23 predetermined by the path pattern insertion circuit 13 is inserted into the empty time slot generated by the data delay circuit 12 ((d) in FIG. 7) and input to the monitored unit 14. You.

In the output pattern output from the monitored unit 14, the path pattern portion is extracted and separated based on the designated time slot "4" added by the data delay circuit 12 in the path pattern separation circuit 15. Then, the separated path pattern is compared with a preset comparison pass pattern in a path pattern check circuit 19, and the comparison result is output as a monitor output signal 18 (FIG. 7E, FIG. 7). 24). on the other hand,
An output data signal 16 is generated from the output pattern from which the path pattern has been extracted by filling the empty time slot generated by the data delay circuit 12 in the data adjustment circuit 17 (FIG. 7 (f)).

As a technique relating to a path pattern monitoring circuit for monitoring a device by generating an empty time slot and inserting a path pattern into the time slot as described above, for example, Japanese Patent Application Laid-Open No. 6-77924, entitled "Monitoring Method in Device" It has been disclosed.

Further, Japanese Patent Application Laid-Open No. 5-284134 discloses a "line monitoring circuit" which relates to a path pattern monitoring circuit capable of realizing online monitoring by setting path patterns in all time slots in a frame. Techniques are disclosed.

[0009]

The technique of the pass pattern monitoring circuit disclosed in such a conventional "method of monitoring in a device" disclosed in JP-A-6-77924 or "line device circuit" disclosed in JP-A-5-284134. In the example, the path pattern extracted from the output pattern from the monitored target unit 14 to be monitored is compared with a preset path pattern. That is, the extracted path pattern is compared with a preset expected value of the path pattern.
However, in recent devices, there is a tendency that the bus width of a multi-bit structure increases due to a demand for improvement in signal processing capability and processing capability. However, when the number of input signal lines and output signal lines such as memory circuits and selector circuits increases, the device monitoring circuit using the above-described path patterns needs to perform the expected value comparison of the path patterns by the number of signal lines. This has led to an increase in the memory capacity for storing the expected value, a complicated configuration of the path pattern detection unit, and an increase in the circuit scale.

An object of the present invention is to provide a path pattern monitoring circuit which suppresses an increase in the circuit scale even when the number of signal lines increases in device monitoring using a path pattern.

[0011]

According to the first aspect of the present invention, there is provided a monitoring target circuit which outputs the same number of output data signals in response to a plurality of input data signals.
(B) For each of a plurality of input data signals input to the circuit to be monitored, these input data signals are paired as a pair, and each pair has an inverted bit pattern, one of which is the other, as an input pattern. A pattern insertion unit to be inserted, (c) a pattern detection unit for detecting an output pattern output from the monitoring target circuit in response to the input pattern inserted by the pattern insertion unit, and (d) detection by the pattern detection unit. The path pattern monitoring circuit includes monitoring means for monitoring the monitoring target circuit based on the specified output pattern.

That is, according to the first aspect of the present invention, a plurality of input data signals are output to the monitoring target circuit in response to the plurality of input data signals. One pair of signals is paired, and each pair receives an input data signal inserted with one inverted pattern of the other as an input pattern. The monitoring target circuit is monitored based on the output pattern output from the monitoring target circuit.

According to a second aspect of the present invention, in the path pattern monitoring circuit according to the first aspect, the pattern inserting means includes two input data signals for each of the plurality of input data signals input to the monitored circuit. As a pair of pairs, a bit pattern in which one is the complement of the other is inserted into each pair as an input pattern.

That is, according to the second aspect of the present invention, the pattern to be inserted into the input data signal input to the circuit to be monitored is
These input data signals are paired in pairs for each input data signal, and in each pair, a pattern in which one is the complement of the other is inserted as an input pattern.

According to a third aspect of the present invention, in the path pattern monitoring circuit according to the first or second aspect, an input pattern is inserted into an empty time slot.

That is, according to the third aspect of the present invention, a pattern for monitoring a circuit to be monitored is inserted into an empty time slot.

According to a fourth aspect of the present invention, (a) a memory circuit for outputting the same number of output data signals in response to a plurality of input data signals, and (b) a plurality of input data signals to the memory circuit (C) inserting each of these input data signals into a pair of two pairs of input data signals, and inserting each of the pairs of input data signals into an empty time slot as an input pattern with the other inverted bit pattern; A pattern extraction unit for extracting an output pattern output from the memory circuit in accordance with the input pattern inserted by the pattern insertion unit; and (d) a pattern extraction unit corresponding to the input pattern inserted by the pattern insertion unit. (E) computing means for computing the exclusive OR of each bit of the output pattern extracted by the extracting means for all pairs;
An abnormality detecting means for detecting an abnormality in the memory circuit when at least one of the operation results of each pair calculated by the arithmetic means is "0" is provided in the path pattern monitoring circuit.

That is, according to the present invention, two input data signals are input to a memory circuit which outputs the same number of output data signals in response to a plurality of input data signals. As one set of this pair, one of the pairs inserts the inverted bit pattern of the other as an input pattern into an empty time slot. The exclusive OR of the bits of the output pattern output from the memory circuit corresponding to the input pattern is calculated for all pairs, and at least one of the calculation results of each pair is “0”. At this time, an abnormality of the memory circuit is detected.

According to the fifth aspect of the present invention, (a) a selector circuit for outputting the same number of output data signals in response to a plurality of input data signals, and (b) a plurality of input data signals inputted to the selector circuit (C) inserting each input data signal into a vacant time slot as an input pattern, wherein each of the input data signals is a pair of two input data signals; A pattern extraction unit for extracting an output pattern output from the selector circuit in accordance with the input pattern inserted by the pattern insertion unit; and (d) a pattern extraction unit corresponding to the pair of the input pattern inserted by the pattern insertion unit. Calculating means for calculating the sum of each bit of the output pattern extracted by the extracting means for all pairs, and (e) calculating by the calculating means At least one of the operation results of respective pairs but is provided in Pasupatan monitoring circuit and an abnormality detecting means for detecting an abnormality of the memory circuit when "1".

That is, according to the fifth aspect of the present invention, two input data signals are input to a selector circuit which outputs the same number of output data signals in response to a plurality of input data signals. As one set of pairs, a bit pattern in which one of the pairs is the complement of the other is inserted into an empty time slot as an input pattern. Then, the addition operation of the bits of the output pattern output from the selector circuit corresponding to this input pattern is performed for all pairs, and when at least one of the operation results of each pair is “1”, the selector It detects the abnormality of the circuit.

According to a sixth aspect of the present invention, in the path pattern monitoring circuit of the first to fifth aspects, when the number of input data signals is odd, the number of dummy data lines is added to make the number even.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

First Embodiment

FIG. 1 shows an outline of the configuration of a path pattern monitoring circuit according to a first embodiment of the present invention.
The Pasupatan monitoring circuit, the input data signal synchronized with the same clock 30 _1, 30 _2, ..., output data signal 31 ₁ in response to the 30 _N, 31 _2, ..., a memory 32 for outputting a 31 _N , a Pasupatan insertion portion 34 for inserting the Pasupatan based Pasupatan insert instruction signal 33 to each of the input data signal 30 ₁ to 30 _N, detects Pasupatan from the output data signal 31 ₁ to 31 _N on the basis of the Pasupatan detection indication signal 35 And a pass pattern detection unit 37 that outputs a detection result signal 36.

This path pattern monitoring circuit is a memory 32 for outputting an N-frame output data signal to an output destination in a fixed manner to an N-frame input data signal inputted in synchronization with the same clock. Can be monitored. Pass pattern insertion instruction signal 33
, Together with the idle time slots in the input data signal of a frame structure from the input data signal 30 ₁ to 30 _N, respectively, by idle time slots detector is detected, not shown, a timing signal specifying the position of the idle time slots are generated It is supposed to be. Therefore,
Pasupatan insertion portion 34 can be inserted Pasupatan the idle time slots of the input data signal 30 ₁ to 30 _N on the basis of the Pasupatan insertion instruction signal 33. In the detection of the empty time slot described above, since the input data signal and the output data signal have a predetermined frame configuration, the empty time slot can be easily detected by detecting a predetermined position of the framed signal. Can be determined.

By the way, the path pattern inserted by the path pattern insertion section 34 is such that arbitrary two of N input data signals are determined in advance as one set of pairs, and one of the path patterns is used for inversion of the other path pattern. The inserted pass pattern pair is inserted. For example, when assumed to be predetermined input data signal 30 ₁ and the input data signal 30 _N-2 as a signal-to-above, the input data signal 30 _N against Pasupatan "0" of the input data signal 30 ₁ "1" is inserted into the path pattern of _-2 . When the number N of signals is an odd number, the same pass pattern can be inserted by adding one dummy signal line and using only the pass pattern portion as an even number.

In this manner, a pair of two pass pattern pairs is inserted into each signal pair, and based on the pass pattern detection instruction signal 35 from the output data signals 31 _{1 to} 31 _N output from the memory 32 input. The path pattern detection unit 37 extracts an output path pattern output from the memory 32 corresponding to each path pattern pair inserted by the path pattern insertion unit 34. Since the output path pattern output from the memory 32 is included in the empty time slot specified by the path pattern insertion instruction signal 33, the path pattern detection instruction signal 35 is actually delayed from the path pattern insertion instruction signal 33 by the delay of the memory 32. The signal is input to the path pattern detection unit 37 at a timing delayed by the time.

The output path pattern detected by the path pattern detection section 37 is an exclusive OR (Exclusive OR) of bits of a signal pair determined in advance when the path pattern is inserted.
R: Hereinafter, abbreviated as EXOR. ), And by taking the product of the results of each operation, it can be determined whether or not a mismatch has occurred in the signal pair transmitted through the memory 32.

FIG. 2 shows an outline of the configuration of such a path pattern detecting section. The path pattern detection unit 37 detects the detected path patterns 38 ₁ , 38 ₂ ,.
, 39 _M, and the pass patterns 39 ₁ , 39 ₂ ,..., 39 _M are input, and the pass patterns 38 _X , 39 _X (X = 1,
,..., M) are path pattern pairs. When the number of signals N is equal to 2M, this path pattern detection unit can be applied to the path pattern monitoring circuit shown in FIG. Pasupatan detector 37 such Pasupatan pair is input, computing an EXOR circuit 40 ₁ for calculating an exclusive OR of Pasupatan pair 38 _1, 39 _1, the exclusive OR of Pasupatan pairs 38 _2, 39 ₂ EXOR
A circuit 40 _2, ..., an EXOR circuit 40 _M for calculating the exclusive OR of Pasupatan pairs 38 _M, 39 _M, these E
AND circuit 41 for calculating a product of the XOR circuit 40 ₁ to 40 _M
And

In such a path pattern detecting section 37, since the exclusive OR of each pair of path patterns before being input to the memory 32 is "1", the pair of path patterns detected after output from the memory 32 is determined. When the exclusive OR of at least one of all pairs is “0”, it is possible to detect that the output result of the memory 32 is abnormal.

For example, if one set of pass patterns is "0110"
If the exclusive OR is calculated in bit units, the outputs of all four EXORs become "1", and the product of these becomes "1" to confirm the normal operation of the memory 32. Can be. On the other hand, when the detected path patterns are “0110” and “1000”, “1” is output in the third EXOR, but the fourth EXO is output.
Since “0” is output in R, the product of these is “0”, and an abnormal operation of the memory 32 can be detected.
As described above, the path pattern matching can be performed by calculating the exclusive OR for every pair of the output path patterns.

FIG. 3 is a timing chart for explaining the operation of the above-described path pattern monitoring circuit. Input data signal 30 ₁ to 30 _N, the frame pulse (Frame Pulse: FP) transmits signals for each predetermined time slot by 42 is framed (in FIGS. 3 (a)
And (b)). From the input data signal 30 ₁ to 30 _N thus framed, idle time slots 43 is detected by detecting a predetermined position of the frame signal by idle time slots detecting section not shown (in FIG. 3 (c)), A pass pattern insertion instruction signal 33 is generated (44 in FIG. 3). An output data signal is obtained by inserting the above-described pair of path patterns into the empty time slot designated by the path pattern insertion instruction signal 33 and inputting the pair to the memory 32 ((d) in FIG. 3). The output path pattern 45 of the empty time slot included in the output data signal is obtained from the path pattern insertion instruction signal 33 by the memory 3.
An output path pattern is detected based on the path pattern detection instruction signal 35 delayed by a time 46 corresponding to two passes (47 in FIG. 3). The output path pattern detected in this way is compared with the path pattern in the path pattern detection circuit 37 shown in FIG. 2 to monitor the memory 32.

As described above, in the path pattern monitoring circuit in the first embodiment, N input data signals 30 ₁
To monitor the memory 32 the output data signal 31 ₁ to 31 _N of the N outputs fixedly according to to 30 _N, the Pasupatan the idle time slots in the input data signal based on Pasupatan insert instruction signal 33 Insert it.
The path pattern to be inserted is such that any two of the N input data signals are determined in advance as one set of pairs, and a path pattern pair in which one path pattern is the inverse of the other path pattern is inserted. From the output data signal output from the memory 32 to which the input data signal into which such a path pattern has been inserted is input, each path pattern pair inserted by the path pattern insertion unit 34 by the path pattern detection unit 37 based on the path pattern detection instruction signal 35. , An output path pattern output from the memory 32 is extracted. Then, path pattern matching can be performed by calculating exclusive OR of each path pattern pair extracted by the path pattern detection unit 37. Thus, there is an effect that the path pattern detection unit can be simplified by eliminating the need for a large-capacity memory circuit and an expected value comparison circuit for comparing expected path pattern values.

Second Embodiment

FIG. 4 shows an outline of the configuration of a path pattern monitoring circuit according to a second embodiment of the present invention.
The Pasupatan monitoring circuit, the input data signal 50 ₁ in synchronization with the same clock, 50 _2, ..., output data signal 51 ₁ in response to the 50 _N, 51 _2, ..., a selector 52 for outputting a 51 _N , the input data signal 50 _1-50 and Pasupatan insertion portion 54 for inserting the Pasupatan based Pasupatan insert instruction signal 53 to each of the _N, the output based on the data path pattern detection indication signal 55 at the output data signal 51 ₁
And a Pasupatan detector 57 for outputting a detection result signal 56 to detect Pasupatan from to 51 _N.

This path pattern monitoring circuit receives the input N
It is possible to monitor a selector 52 that outputs N output data signals to a route that is selected and controlled in advance for the input data signals. Pasupatan insert instruction signal 53, along with the idle time slots in the input data signal of a frame structure is detected from the input data signal 50 ₁ to 50 _N, respectively, by idle time slots detecting unit (not shown), specifying the position of the idle time slots Is generated. Therefore, Pasupatan insertion portion 54 based on the Pasupatan insertion instruction signal 53 can be inserted Pasupatan the idle time slots of the input data signal 50 ₁ to 50 _N.

By the way, the path pattern inserted by the path pattern inserting section 54 is such that any two of N input data signals are determined in advance as one set of pairs, and one of the path patterns is complemented by the complement of the other. The inserted pass pattern pair is inserted. When the number N of signals is an odd number, the same pass pattern can be inserted by adding one dummy signal line and using only the pass pattern portion as an even number.

In this manner, a pair of two pass pattern pairs is inserted into each signal pair, and the output data signals 51 _{1 to} 51 _N output from the selector 52 are inputted based on the pass pattern detection instruction signal 55. The path pattern detection unit 57 extracts an output path pattern output from the selector 52 corresponding to each path pattern pair inserted by the path pattern insertion unit 34. Since the output path pattern output from the selector 52 is included in the vacant time slot specified by the path pattern insertion instruction signal 53, the path pattern detection instruction signal 55 is actually delayed from the path pattern insertion instruction signal 53 by a delay corresponding to the passage through the selector 52. The signal is input to the path pattern detection unit 57 at the timing delayed by the time. The output path pattern detected by the path pattern detection unit 57 is obtained by adding bits of a predetermined signal pair at the time of inserting the path pattern, and further performing pattern matching based on whether or not the addition result of all pairs is “0”. Will be

FIG. 5 shows an outline of the configuration of such a path pattern detecting section. This path pattern detection unit 57 detects the detected path patterns 58 ₁ , 58 ₂ ,.
And 58 _M, Pasupatan 59 _1, 59 _2,..., And the 59 _M is input, Pasupatan _{58 X, 59 X (X =} 1,
,..., M) are path pattern pairs. When the number of signals N is equal to 2M, this path pattern detection unit can be applied to the path pattern monitoring circuit shown in FIG. The path pattern detecting unit 57 to which such a pair of path patterns is input is used for each of the pair of path patterns 58 ₁ , 5.
9 includes an arithmetic circuit 60 that performs addition on ₁ and a NOR circuit 61 that performs a NOR operation on an addition result of each path pattern pair.

In such a path pattern detector 57, since the addition result of each pair of path patterns before being input to the selector 52 is "0", the path pattern pairs detected after output from the selector 52 are all pairs. When the addition result of at least one of the pairs is “1”, it can be detected that the output result of the selector 52 is abnormal.

As described above, in the path pattern monitoring circuit according to the second embodiment, the N output data signals 31 _{1 to} 31 _N are generated according to the _N input data signals 30 ₁ to 30 _N by predetermined selection control. In order to monitor the selector 52 to be output, a path pattern is inserted into an empty time slot in the input data signal based on the path pattern insertion instruction signal 53. As the path pattern to be inserted, arbitrary two of the N input data signals are determined in advance as one set of pairs, and one path pattern is inserted as a complement of the other path pattern. From the output data signal output from the selector 52 to which the input data signal into which such a path pattern is inserted is input, based on a path pattern detection instruction signal 55, a path pattern detection unit 57
Thus, the output path pattern output from the selector 52 is extracted corresponding to each path pattern pair inserted by the path pattern insertion unit 54. Then, the path pattern detection unit 5
By performing an addition operation on each of the path pattern pairs extracted in step 7, the path pattern matching can be performed. Thus, there is an effect that the path pattern detection unit can be simplified by eliminating the need for a large-capacity memory circuit and an expected value comparison circuit for comparing expected path pattern values.

[0043]

As described above, according to the first aspect of the present invention, a pair of a plurality of input data signals is used as a pair of a pair of pass data patterns, one of which is an inverted bit pattern of the other. By monitoring based on the output path pattern from the monitoring target circuit for
Since it is not necessary to refer to the input path pattern, the path pattern matching circuit can be simplified. Furthermore, since it is not necessary to perform pass pattern matching for each data signal, not only can the circuit scale be significantly reduced, but also the increase in circuit scale can be suppressed even if the number of signal lines increases.

According to the second aspect of the present invention, a pair of input data signals is monitored as a path pattern based on an output path pattern from a monitored circuit for a path pattern pair in which one is the complement of the other. By doing so, it is not necessary to refer to the input path pattern, and the circuit for matching the path pattern can be simplified.

Further, according to the third aspect of the present invention, since the path pattern pair is inserted using the vacant time slot, monitoring can be efficiently performed even when the monitored circuit is in operation. .

According to the fourth aspect of the present invention, one of the paired path patterns for the memory circuit inserts an inverted bit pattern of the other, so that an exclusive OR circuit is provided for the output path pattern pair. With this simple circuit configuration, the monitoring of the memory circuit can be performed. In addition, since a large-capacity memory circuit and an expected value comparing circuit for comparing the expected value of the conventional pass pattern are not required, and it is not necessary to perform the pass pattern matching for each data signal, the circuit scale can be significantly reduced. In addition to this, even if the number of signal lines increases, an increase in circuit scale can be suppressed.

According to the fifth aspect of the present invention, since a bit pattern, one of which is the complement of the other, is inserted as a pair of path patterns for the selector circuit, a simple addition circuit such as an adder circuit is provided for the pair of output path patterns. Monitoring of the selector circuit can be performed with a circuit configuration. This eliminates the need for conventional large-capacity memory circuits and expected value comparison circuits for comparing expected pass pattern values, and eliminates the need to perform pass pattern matching on each data signal.
The circuit scale can be greatly reduced, and the increase in the circuit scale can be suppressed even when the number of signal lines increases.

Further, according to the present invention, when the number of input data signals is an odd number, the number of input data signals is treated as an even number by adding a dummy signal line. A path pattern monitoring circuit that can be realized at low cost can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating an outline of a configuration of a path pattern monitoring circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating an outline of a configuration of a pattern detection circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart for explaining an operation in the first embodiment of the present invention.

FIG. 4 is a configuration diagram illustrating an outline of a configuration of a path pattern monitoring circuit according to a second embodiment of the present invention;

FIG. 5 is a configuration diagram illustrating an outline of a configuration of a pattern detection circuit according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram showing an outline of a configuration of a conventionally proposed path pattern monitoring circuit.

FIG. 7 is a timing chart for explaining an operation of a conventional path pattern monitoring circuit.

[Explanation of symbols]

30 ₁ to 30 _N , 50 ₁ to 50 _N input data signals 31 _{1 to} 31 _N , 51 _{1 to} 51 _N output data signals 32 memories 33, 44, 53 pass pattern insertion instruction signals 34, 54 pass pattern insertion units 35, 47, 55 Pass pattern detection instruction signal 36, 56 Detection result output signal 37, 57 Pass pattern detection section 38 _{1 to} 38 _M , 39 _{1 to} 39 _M , 58 _{1 to} 58 _M , 59 ₁ to
59 _M path pattern 40 ₁ to 40 _M EXOR circuit 41 AND circuit 42 Frame pulse 43 Empty time slot 45 Output path pattern 46 Delay time 52 Selector 60 Arithmetic circuit 61 NOR circuit

Claims (6)

[Claims] 1. A monitored circuit that outputs the same number of output data signals in response to a plurality of input data signals, and a plurality of input data signals input to the monitored circuit. Pattern insertion means for inserting a signal as an input pattern, one of each being a pair of signals as one pair, and the monitoring means corresponding to the input pattern inserted by the pattern insertion means. A path pattern comprising: pattern detection means for detecting an output pattern output from a target circuit; and monitoring means for monitoring the monitoring target circuit based on a predetermined output pattern detected by the pattern detection means. Monitoring circuit. 2. The pattern insertion means, for each of a plurality of input data signals inputted to the circuit to be monitored, sets these input data signals as a pair of two, one of each pair being the complement of the other. 2. The path pattern monitoring circuit according to claim 1, wherein a bit pattern to be inserted is inserted as an input pattern. 3. The path pattern monitoring circuit according to claim 1, wherein said path pattern insertion means inserts an input pattern into an empty time slot. 4. A memory circuit for outputting the same number of output data signals in response to a plurality of input data signals, and applying the input data signals to the plurality of input data signals input to the memory circuit. Pattern insertion means for inserting the inverted bit pattern of each pair as an input pattern into a vacant time slot as a pair of two, and corresponding to the input pattern inserted by the pattern insertion means. A pattern extraction unit for extracting an output pattern output from the memory circuit; and an exclusive logic of mutual bits of an output pattern extracted by the pattern extraction unit corresponding to a pair of input patterns inserted by the pattern insertion unit. Calculating means for calculating the sum of all pairs, at least one of the calculation results of each pair calculated by the calculating means Pasupatan monitoring circuit but which is characterized by comprising an abnormality detector for detecting an abnormality of the memory circuit when "0". 5. A selector circuit for outputting the same number of output data signals in response to a plurality of input data signals, and a plurality of input data signals input to the selector circuit. A pattern insertion unit for inserting a bit pattern, one of which is the complement of the other, as an input pattern into an empty time slot as a pair of two pairs, and corresponding to the input pattern inserted by the pattern insertion unit; A pattern extraction unit for extracting an output pattern output from the selector circuit; and a sum of bits of the output pattern extracted by the pattern extraction unit corresponding to a pair of the input pattern inserted by the pattern insertion unit. And at least one of the calculation results of each pair calculated by the calculation means is Pasupatan monitoring circuit, characterized by comprising abnormality detecting means for detecting an abnormality of the memory circuit when a 1 ". 6. The path pattern monitoring circuit according to claim 1, wherein when the number of input data signals is odd, an even number is added by adding a dummy signal line.