JPH088996A - Fault detector - Google Patents

Abstract

PURPOSE:To confirm normality of a monitoring function in real time. CONSTITUTION:When a transmission line fault between processing blocks to be connected by 1 to 1 is detected, the output part of a processing block 1 is provided with a data addition part 10B for fault detection and data for fault detection showing 'normality' and 'abnormality' is alternately added to output data with a periodicity. The input part of the processing block is provided with a fault detection part 10 C and data for fault detection is alternately detected from input data with the same periodicity as that on the front step. A fault detection signal 104 showing 'no error' at the time of a detection and 'error' at the time of a detection impossible is made to be outputted, a fault detection signal 104 is monitored in a fault line concentration part 10E, 'no error' and 'error' are alternately discriminated with the periodicity, and the normality of the data addition part 10B for fault detection, the fault detection part 10C, the fault line concentration part 10 E and a transmission line 101 at the time of 'no error' and 'error' can be always monitored 7 in real time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault monitoring device used in a data processing device such as an electronic computer or an electronic exchange to monitor a fault occurrence in a data transmission line.

[0002]

2. Description of the Related Art As is well known, a data processing device such as an electronic computer or an electronic exchange is provided with a fault monitoring device for monitoring the occurrence of a fault in a data transmission path.

As an example of this fault monitoring device, a fault detecting section and a fault detecting data adding section are provided in each processing block, and the fault detecting data adding section of the preceding block adds the fault detecting data to the output data. By determining whether the failure detection data is normal / abnormal in the subsequent block, it is detected whether or not a failure has occurred in the data transmission path, the failure detection signals obtained by the failure detection unit of each block are collected by the failure concentrator, and the CPU ( There is a system of notifying a higher-level device such as a central control device).

In this type of fault monitoring device, the fault detecting unit, the fault detecting data adding unit, the fault concentrating unit, and the fault detecting data adding unit for confirming the normality of the transmission line of the fault detecting signal are added from the host unit. An inspection command is given to the section arbitrarily or periodically, and data for allowing the failure detection section to detect a failure is intentionally added. That is, the normality is confirmed by checking whether or not a fault occurs artificially in response to a test command from the host device and a fault occurrence notice is sent from the fault concentrator.

However, in the conventional fault monitoring device as described above, a test command is given from the host device to the fault detection data addition section to add data indicating a pseudo abnormality as if a fault had occurred. In this way, the normality of the monitoring function is confirmed by the fault detection unit on the upper device side detecting the fault and determining whether or not the fault concentration unit returns the fault occurrence notification. However, software processing on the host device side is required, and the normality of the monitoring function cannot be confirmed in real time.

[0006]

As described above, the fault monitoring device used in the conventional data processing device requires software processing on the host device side to confirm the normality of the monitoring function. Moreover, there is a problem that the normality cannot be confirmed in real time.

Therefore, the present invention has been made to solve the above-mentioned problems, and does not require software processing on the host device side.
It is an object of the present invention to provide a fault monitoring device capable of confirming the normality of the monitoring function in real time.

[0008]

In order to solve the above-mentioned problems, a first invention is a failure detecting apparatus for detecting a failure in a transmission path between processing blocks connected in a one-to-one correspondence in a data processing apparatus. The fault detection data adding section that alternately adds fault detection data indicating "normal" and "abnormal" to the data to the processing block of the above, and the "normal", " Fault detection data representing "abnormal" is detected alternately with periodicity,
A fault detection unit that outputs a fault detection signal that indicates “no error” when detected and a fault detection signal when detection is not possible, and monitors the fault detection signal output from this fault detection unit for “no error” and “error present” And a fault concentrating portion for discriminating alternately with the periodicity.

A second aspect of the present invention is a data processing apparatus according to the first aspect.
In a failure detection device that detects a transmission path failure between processing blocks connected by a plurality of pairs, a plurality of ones, and a plurality of pairs, failure detection data indicating "normal" or "abnormal" in data to a subsequent processing block. And the identification data attached to the data from the processing block in the preceding stage, and the identification data attached to the data from the preceding processing block are detected. The fault detection data corresponding to the above is detected, and a fault detection unit that outputs a fault detection signal indicating “no error” at the time of detection and “error present” at the time of undetectable together with the identification data, and is output from this fault detection unit. And a fault concentrating section that monitors "fault detection signal" based on the identification data to determine "no error" and "error".

[0010]

In the fault detecting apparatus according to the first aspect of the present invention, when detecting a transmission line fault between processing blocks connected one-to-one,
A fault detection data addition unit is provided in the output unit of the processing block, and fault detection data indicating "normal" and "abnormal" is alternately added to the data to the subsequent processing block with periodicity. The failure detection section is provided in the input section of the
Fault detection data indicating "abnormal" is alternately detected with the same periodicity as the preceding stage side, and a fault detection signal indicating "no error" when detected and "error present" when undetectable is output. By monitoring the failure detection signal output from the failure detection section and alternately determining "no error" and "error" with a periodicity, the error detection data addition section when there is no error and when there is an error The normality of the fault detector, fault concentrator, and transmission line can be constantly monitored in real time.

The fault detecting apparatus of the second invention is one-to-many,
When detecting a transmission path failure between processing blocks connected in multiple-to-one or multiple-to-multiple connection, a failure detection data addition unit is provided at the output unit of the processing block, and the data to the subsequent processing block is "normal". , And "abnormal" fault detection data are added in an arbitrary order, identification data indicating the contents of the added data is added, and a fault detection unit is provided in the input unit of the processing block to provide the preceding processing block. The identification data added to the data from the above is detected, the fault detection data corresponding to this identification data is detected, and the fault detection signal indicating "no error" when detected and "error present" when undetectable Outputs together with the identification data, and monitors the failure detection signal output from the failure detection section in the failure concentration section based on the identification data to determine "no error" and "error" The Rukoto were to be constantly monitor the health of the fault detection data adding unit and the fault detector and fault current line portion when there is an error and when no error transmission line in real time.

[0012]

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, a first embodiment will be described with reference to FIGS.

FIG. 1 shows an embodiment of the fault monitoring apparatus according to the present invention in which the processing blocks of a data processing apparatus are connected in a one-to-one relationship.

In FIG. 1, processing blocks 1 and 2 are CPs.
The input data is appropriately processed according to a command from the higher-level device 3 such as U, and is connected in series to the data transmission path. It is assumed that the data transmission path transmits the processing data of each processing block as well as the data synchronization signal which becomes active in the first byte of the data and the clock signal of the bit period, and the processing blocks in the preceding and succeeding stages are not particularly shown. It is assumed that it is configured in the same manner as 1 and 2.

Each of the processing blocks 1 and 2 has a failure detecting section 10A, 10C at the input section and a failure detecting data adding section 10B, 10D at the output section. Control unit 10F
Is an initialization command from the host device 3 (for example, when the power is turned on,
(Regenerated when processing is restored), the reset signal 105 is sent to the failure detection units 10A and 10C and the failure detection data addition units 10B and 10D of the processing blocks 1 and 2, respectively.
Has the function of sending. The fault concentrating unit 10E has a function of collectively reporting the fault detection signals 103 and 104 from the fault detecting units 10A and 10C of the processing blocks 1 and 2 to the upper level device 3.

The fault detecting data adding sections 10B, 10
D is for adding fault detection data that changes periodically to the processed data and deriving it to the data transmission lines 101 and 102, and the additional data is determined in advance according to the reset signal 105 from the control unit 10F. It is designed to be initialized to the specified value.

Each of the fault detecting units 10A and 10C detects data from the fault detection data added to the input data from the data transmission lines 100 and 101.
The fault detection signal 01 is detected. When the fault is detected, the fault detection signals 103 and 104 are sent to the fault concentrator 10E, and the detection process is initialized according to the reset signal 105 from the controller 10F.

FIG. 2 shows the fault detecting data adding section 10B.
2 shows a specific configuration of. Since the configuration of the fault detection data addition unit 10D of the other processing block 2 is exactly the same as that of 10B, the description thereof is omitted here.

In FIG. 2, input data (processed data in the processing block 1 and herein assumed to be 8-bit parallel data) 200 is a first delay circuit 20A, a parity normal operation unit 20B, a parity pseudo normal operation unit. 20C, the data synchronization signal 201, the reset signal 213 (105 in FIG. 1) and the clock signal 202 are supplied to the control unit 20E, and the clock signal 20
2 is supplied to the second register unit 20H as a latch signal, and the data synchronization signal 201 is supplied to the second delay circuit 20I.

The control unit 20E is composed of a register, a counter, etc., and based on the data synchronizing signal 201, the reset signal 213 and the clock signal 202, the reset signal 212 for the parity normal operation unit 20B and the parity pseudo normal operation unit 20C, the second. Latch signal 204 for the first register unit 20D, the first and second selector units 20
The selection control signals 206 and 207 for F and 20G are generated.

The first delay circuit 20A receives the input data 200
Is delayed for a predetermined period, the LSB data in the delayed output 203 is supplied to the second selector section 20G, and the higher 7-bit data is supplied to the second register section 20H.

The normal parity operation unit 20B uses the normal parity as an odd parity and resets the input data 20 after reset.
For 0, the parity is calculated for each data (unit in which the data synchronization signal 201 becomes active). The parity pseudo-normal operation unit 20C calculates the parity for each data of the reset input data 200 with the abnormal parity as an even parity. The respective parity calculation results are sent to the first register section 20D and latched in response to the latch signal 204.

The two parity data latched here are sent to the first selector section 20F, and the selection control signal 20 is sent.
It is selectively derived according to 6. The selection data 205
Is supplied to the second selector section 20G, and the selection control signal 2
In accordance with 07, it is selectively derived from the LSB data of the output 203 of the delay circuit 20A. The selection data 208 is the second
Of the clock signal 20 supplied to the register unit 20H of the delay circuit 20A and the 7-bit data of the output 203 of the delay circuit 20A.
Latched according to 2.

The 8-bit parallel data 210 latched here is the data synchronizing signal 211 and the clock signal 2 whose timing is adjusted by the second delay circuit 20I.
02 is output to the subsequent processing block 2 through the transmission path 101.

Fault detection data adding section 1 having the above configuration
The operation of 0B will be described with reference to FIGS. 3 and 4.

FIG. 3 shows a data format of the input data 200, and P indicates a parity bit.
In this format, one frame of 10 bytes is used, and 8-bit parallel data of each byte is displayed in hexadecimal "01,
02, 03, 04, 05, 06, 07, 08, 09, 1
0 ". Parity is added to the first 4 bytes, and the parity calculation is performed on the shaded portion including the parity bit P. FIG. 4 shows the fault detection data addition unit 10B of FIG. 3 shows the signal timing waveforms of the respective parts of FIG.

That is, when the clock signal 202 and the reset signal 213 are input, the registers and counters of the control section 20E are reset. Subsequently, when the data synchronization signal 201 which becomes active at the first byte of the frame of the input data 200 is input to the control unit 20E, the control unit 20E causes the data synchronization signal 201
On the basis of the
B, reset signal 212 to the parity pseudo-normal operation unit 20C
To calculate the parity for each frame.

The parity arithmetic units 20B and 20C are reset by the reset signal 212 one clock before the beginning of the input data 200 (the position where the data synchronization signal 201 is active), and when the data 200 is input, the data 200 is input. The parity P is calculated from the beginning, and the calculation result is latched in the first register unit 20D at the rising edge of the latch signal 204 from the control unit 20E. FIG.
In the time chart of, the hexadecimal display is “01, 02, 0
Latches when 04 is calculated from 3, 04, ....

The respective parity calculation results are both input to the first selector section 20F and are alternately derived for each frame according to the selection control signal 206 from the control section 20E. In this embodiment, the selection control signal 206 is "0".
When it is, the operation result on the normal parity operation unit 20B side is selected, and when it is "1", the operation result on the parity pseudo-normal operation unit 20C side is selected.

In the time chart of FIG. 4, the same data (“01, 02, 03, 04, 05, 0 in hexadecimal display”
6, 07, 08, 09, 10 ″) is input three times. Since the normal parity and the abnormal parity are alternately selected, the parity data 205 selected by the selector 20F is set for each frame. "0" and "1" are alternated.

The parity calculation result 205 is the delay circuit 20A.
Of the output 203 is input to the second selector unit 20G together with the LSB data to which the parity is added, and is selectively derived according to the selection control signal 207. That is, the second selector unit 20G selects the 205 side when adding a parity bit, and selects the 203 side at other times.

The output 208 of the second selector section 20G is 1 of the LSB of the 8-bit parallel including the parity bit.
Bits are input to the second register unit 20H. The output 2 of the delay circuit 20A is supplied to the second register section 20H.
Data of the upper 7 bits which do not include the parity bit of 03 is input, both input data are latched at the rising edge of the clock signal 202, and as parallel data 210 of 8 bits, the processing block of the next stage via the transmission path 101. 2 is output.

Here, in the time chart of FIG. 4, since the same data 200 is input in the unit of the data synchronization signal 201, normal parity and abnormal parity are alternately given in the first selector section 20F. . As a result, the logical value of the output 208 of the second selector section 20G is inverted at the selection timing of the selection control signal 207. Therefore, the second
In the output data 210 of the register unit 20H, the value of the byte to which the parity is added is " 04 " and " 05 " in hexadecimal display (the underline indicates that the shaded portion in the figure is present) (normal parity is Since it is odd parity, "04" is normal.

Further, the data synchronization signal 211 is the delay circuit 2
The output data 210 is phase-matched with 0I and is output to the processing block 2 of the next stage via the transmission path 101 together with the clock signal 202.

FIG. 5 shows a specific configuration of the fault detecting section 10C. Since the configuration of the fault detection unit 10A of the other processing block 1 is exactly the same as that of 10C,
The description is omitted here.

In FIG. 5, reference numeral 50A is a parity calculation unit for inputting the data 500 (210 in FIG. 2) sent from the failure detection data addition unit 10B through the transmission line 101 and calculating the parity thereof. The result 504 is sent to the register 50C.

Reference numeral 50B is a clock 5 sent from the fault detection data adding section 10B through the transmission line 101.
01 (202 in FIG. 2), the data synchronization signal 211, and the reset signal 503 (105 in FIG. 1, 213 in FIG. 2) sent from the control unit 10F.
A control unit for controlling A and the register 50C, which supplies a parity reset signal 505 to the parity calculation unit 50A and an error synchronization signal 506 to the register 50C.

The register 50C controls the parity error signal 504 obtained by the parity operation unit 50A to the control unit 5.
The synchronization is performed by the error synchronization signal 506 from 0B, and the error signal 507 subjected to the synchronization processing here is sent to the fault concentrator 10E together with the error synchronization signal 506.

The operation of the fault detecting section 10C having the above configuration will be described with reference to the time chart of FIG.

First, data 50 is sent to the parity operation unit 50A.
0 is input and the clock 50 is input to the control unit 50B.
1, the data synchronization signal 502, and the reset signal 503 are input, the control unit 50B displays each data (“01, 02, 03, 04 , 05, 0 in hexadecimal display”).
6,07,08,09,10 "and" 01,02,03,
04, 05 , 06, 07 , 08, 09, 10 "), the parity reset signal 505 is sent to the parity operation unit 50A to reset the parity operation one clock before the data synchronization signal 502. Thereby, the parity is data. Will be calculated from the beginning.

Input data 500 in the parity operation unit 50A
The result 504 of the parity calculation of the error synchronization signal 5
It is latched in the register 50C at the rising edge of 06, and its latch output (parity error signal) 507 is output together with the error synchronization signal 506.

Here, since the data format of the input data 500 is as shown in FIG. 3, the input data 500 shown in the time chart of FIG. 6 is displayed in hexadecimal as "01, 02, 03, 04 , 05,". 06,07,08,
09, 10 "and" 01, 02, 03, 04, 05 , 0
6,07,08,09,10 "and" 01,02,03,
04 , 05, 06, 07, 08, 09, 10 "are input to the register 50C. Since the odd number parity is the correct answer, the error signal 507 has a parity addition byte of" 05 ".
At the time of, it becomes "H" level. The error signal 507 thus generated is sent to the fault concentrator 10E as an abnormality detection signal (104 in FIG. 1) together with the error synchronization signal 506.

FIG. 7 shows a specific structure of the obstacle concentrator 10E.

In FIG. 7A, reference numeral 70A is an alternate waveform abnormality detecting section, and 70B is a failure holding circuit, which are provided corresponding to the failure detecting sections 10A and 10C of each block, respectively. Incidentally, here, only the configuration corresponding to 10C is shown, and the configurations for the other components are the same, and therefore will be omitted.

The alternate waveform abnormality detecting section 70A is constructed, for example, as shown in FIG. 7B, and stores the error signal 700 (corresponding to 507 in FIG. 5) sent from the failure detecting section 10C in a register (D type). It is input to the flip-flop) 70C and latched at the rising timing of the error synchronization signal 701 (506 in FIG. 5) sent at the same time. And
The latch output is further input to the register (D-type flip-flop) 70D and latched at the rising timing of the error synchronization signal 701. Furthermore, both registers 70
EX-NOR gate 70F takes the exclusive OR of the latched outputs of C and 70D, and outputs the inverted result. The logic output 704 is sent to the fault holding circuit 70B.

The fault holding circuit 70B has a function of detecting and holding an error occurrence from the output 704 of the alternating waveform abnormality detecting section 70A. The error detection signal 705 held here is sent to the higher-level device 3.

The operation of the obstacle concentrator 10E having the above structure will be described with reference to the time chart of FIG.

First, in the alternate waveform abnormality detecting section 70A, when the error signal 700 and the error synchronizing signal 701 are inputted from the failure detecting section 10C, the error signal 700 is shifted by one stage and shifted by two stages. Take the EX-NOR to find the error location.

That is, the error signal 700 is normal and is "L" level, and abnormal is "H" level. When the abnormality detection process is operating normally, it is alternately inverted to "L" level and "H" level. If an abnormality occurs in the abnormality detection processing itself, as shown in FIG.
The error of will not be input alternately. Therefore, the EX-NOR output 704 remains at the "H" level at the error occurrence location. Therefore, the error holding circuit 70B holds the error of the EX-NOR output 704 at the error occurrence location.
By sending this error hold signal 705 to the host device 3,
The normality of the fault detection device itself can be discriminated on the higher-level device 3 side.

Therefore, according to the fault detecting apparatus having the above-mentioned configuration, in the fault detecting data addition section, fault detecting section, fault concentrating section, and fault detection of the transmission line, the fault detecting bit or data alternates between normal and abnormal. To the fault detection data addition section, transmission line,
When a failure occurs in each part of the failure detection part and the failure concentration part (missing data,
The normality of the functional operation at the time of non-fault (data insertion etc.) and the normal operation can be easily determined in real time by hardware without any intervention from the host device by software and can be constantly monitored and confirmed.

In the above embodiment, the failure detection bits or data are alternately assigned to normal and abnormal, but the present invention can be implemented in the same manner even if the data or data is used once.

Next, a second embodiment will be described with reference to FIGS. 9 to 15. In this embodiment, in FIG. 1, it is assumed that the processing blocks of the data processing device are connected in a one-to-many manner, a plurality-to-one manner or a plurality-to-many manner.

FIG. 9 shows a specific configuration of the fault detection data addition section 10B of the second embodiment. Since the configuration of the fault detection data addition unit 10D of the other processing block 2 is exactly the same as that of 10B, the description thereof is omitted here.

In FIG. 9, input data (processed data in the processing block 1 and herein assumed to be 8-bit parallel data) 900 is supplied to the delay circuit 90A, the parity normal operation unit 90B, and the parity pseudo normal operation unit 90C, respectively. Data synchronization signal 901 and reset signal 913 supplied
(105 in FIG. 1) and the clock signal 902 are supplied to the control unit 90E, the clock signal 902 is supplied to the second register unit 90H as a latch signal, and the data synchronization signal 901 is supplied to the pulse expansion circuit 90I.

The control unit 90E is composed of a register, a counter, etc., and based on the data synchronization signal 901, the reset signal 913 and the clock signal 902, the reset signal 912 for the parity normal operation unit 90B and the parity pseudo normal operation unit 90C, Latch signal 904 for the first register unit 90D, random generation control signal 90 for the first selector unit 90F and pulse expansion circuit 90I
6. Selection control signal 90 for second selector section 90G
7 is generated.

The first delay circuit 90A receives the input data 900
Of the delay output 903 is supplied to the second selector section 90G, and the upper 7-bit data is supplied to the second register section 90H.

The parity normal operation unit 90B sets the normal parity as an odd parity and resets the input data 90 after reset.
For 0, the parity is calculated for each data (unit in which the data synchronization signal 901 becomes active). The parity pseudo-normal operation unit 90C calculates the parity for each data of the reset input data 900 with the abnormal parity as an even parity. The respective parity calculation results are sent to the first register unit 90D and are latched according to the latch signal 904.

The two parity data latched here are sent to the first selector section 90F and randomly selected and derived according to the random generation control signal 906.
The selection data 905 is supplied to the second selector section 90G and is selectively derived from the LSB data of the output 903 of the delay circuit 90A according to the selection control signal 907. The selection data 908 is supplied to the second register unit 90H,
It is latched in accordance with the clock signal 902 together with the upper 7-bit data of the output 903 of the delay circuit 90A.

The 8-bit parallel data 910 latched here is output to the subsequent processing block 2 through the transmission line 101 together with the data synchronization signal 911 which is randomly expanded by the pulse expansion circuit 90I.

A specific configuration of the pulse expansion circuit 10 will be described with reference to FIG.

In FIG. 10, the data synchronization signal 901 is input to the register (D-type flip-flop) 100A, shifted by one clock by the clock signal 909, and the shift output 1003 is input to the register (D-type flip-flop) 100B. , The clock signal 909 again shifts by one clock. Both registers 100
The outputs 1003 and 1004 of A and 100B are EX-ORed by an OR (logical sum) gate 100C.

The EX-OR output 1005 is input to the register (D-type flip-flop) 100D and is shifted by one clock by the clock signal 909, and its output 1006 is sent to the selector 100E together with the output 1004 of the register 100B. The selector 100E has two systems of inputs 100 according to the random generation control signal 906.
4,1005 are randomly selected and output. The signal 911 obtained by randomly pulse-expanding the data synchronization signal 901 in this manner is sent as a data synchronization signal to the failure detection unit of the processing block at the next stage.

The operation of the above configuration will be described below with reference to FIG. FIG. 11 is a timing chart showing the output timing of each part of FIGS. 9 and 10. still,
In FIG. 9, a portion surrounded by a dotted line in the drawing has the same configuration as that in FIG. 2, and therefore its description is omitted here.

First, in the first selector section 90F,
Random generation control signal 90 from control unit 90E
6, the output of the parity normal operation unit 90B and the output of the parity pseudo normal operation unit 90C are randomly selected. The parity operation result 905 obtained by this selection operation is
L to which the parity of the output 903 of the delay circuit 90A is added
It is input to the second selector section 90G together with the SB data, and selectively derived according to the selection control signal 907.
That is, the second selector unit 90G selects the 905 side when adding a parity bit, and selects the 903 side at other times.

The output 908 of the second selector section 90G is 1 of LSB of 8-bit parallel including a parity bit.
The bit is input to the second register unit 90H. The output 9 of the delay circuit 90A is connected to the second register section 90H.
Data of the upper 7 bits not including the parity bit of 03 is input, both input data are latched at the rising edge of the clock signal 902, and as parallel data 910 of 8 bits, the processing block of the next stage via the transmission path 101. 2 is output.

On the other hand, the data synchronization signal 901 is sent to the register 1
The shift output 1003 latched at the rising edge of the clock signal 909 by 00A and the shift output 1004 latched at the rising edge of the clock signal 909 by the register 100B are ORed. At this time, OR output 10
05 is two clock widths of the clock signal 909. OR
In order to match the phase of the output 1005 with the data output 910, after latching at the rising edge of the clock signal 909 by the register 100D, the data synchronization signal 10 of 2 clock width
The data synchronization signal 1004 of 06 and 1 clock width is selected by the random generation control signal 906. At this time, the data side to which the parity pseudo normality is added at random selects the data synchronization signal 1006 having a 2-clock width.

Here, in the time chart of FIG. 11, since the pseudo pseudo normal is added to the output data 910 when the fourth byte of the data is "05" in the hexadecimal display, the output data synchronization signal 911 has a width of 2 clocks. Has become.

FIG. 12 shows a fault detecting section 10C of the second embodiment.
2 shows a specific configuration of. Since the configuration of the fault detection unit 10A of the other processing block 1 is exactly the same as that of 10C, the description thereof is omitted here.

In FIG. 12, 120A is a transmission line 101.
Is a parity operation unit that inputs the data 1200 (910 in FIG. 9) sent from the failure detection data addition unit 10B through the operation unit and calculates the parity.
204 is sent to the register 120C.

Further, 120B is a clock signal 1201 (902 in FIG. 9) and a data synchronization signal 12 sent from the fault detection data adding section 10B through the transmission line 101.
02 (911 in FIG. 9), a control unit that controls the parity operation unit 120A and the register 120C based on the reset signal 1203 (105 in FIG. 1) sent from the control unit 10F.
A parity reset signal 1205 is given to the register 1
An error synchronization signal 1206 is given to 20C. The control unit 120B also outputs the clock signal 1201 as an error synchronization clock signal 1208.

The register 120C is a parity operation unit 120.
The parity error signal 1204 obtained in A is synchronized with the error synchronization signal 1206 from the control unit 120B. The error signal 1207 subjected to the synchronization processing here is the error synchronization signal 1206 and the error synchronization clock signal 12
08 is sent to the obstacle concentrator 10E. The error synchronization clock signal 1208 is used to monitor the pulse width of the error synchronization signal 1206 in the fault concentrator 10E.

The operation of the fault detecting section 10C having the above-described structure is exactly the same as the operation of the fault detecting section 10C of the first embodiment, as shown in the time chart of FIG. Line 1208
The difference is that is output.

FIG. 14 shows the obstacle concentrator 10E of the second embodiment.
2 shows a specific configuration of.

In FIG. 14 (a), 140A is a pulse width monitoring section and 140B is a failure holding circuit, which are provided corresponding to the failure detection sections 10A and 10C of each block, respectively. Incidentally, here, only the configuration corresponding to 10C is shown, and the configurations for other components are the same, and therefore the description thereof will be omitted.

The pulse width monitoring section 140A is constructed, for example, as shown in FIG. 14B, and the error synchronization signal 1401 (12 in FIG. 12) sent from the failure detecting section 10C.
(Corresponding to 06) register (D-type flip-flop) 14
It is input to 0C and latched at the rising timing of the error synchronization clock signal 1406 (1208 in FIG. 12) sent at the same time. Then, the latch output 1407 is further input to the register (D-type flip-flop) 140D and latched at the rising timing of the error synchronization clock signal 1406.

Further, the NAND outputs of the respective latch outputs 1407 and 1408 of the two registers 140C and 140D are taken by the NAND gate 140E and inverted and output. The logic output 1409 is input to the selector 140F together with the error signal 1400 and selectively derived according to the error signal 1400.

On the other hand, the control unit 140H sets the pulse width of the error synchronization signal 1401 to the error synchronization clock signal 1
The pulse width monitoring timing is determined by 406, and the timing signal 1411 is sent to the register 140G. The register 140G latches the selection output 1410 of the selector 140F at the rising timing of the timing signal 1411. The latch output 1404 is sent to the fault holding circuit 140B.

The fault holding circuit 140B has a function of detecting an error occurrence from the output 1404 of the pulse width monitoring unit 140A and holding it. The error detection signal 1405 held here is sent to the higher-level device 3.

The operation of the fault concentrating section 10E having the above configuration will be described with reference to the time chart of FIG.

First, the error synchronization signal 1401 from the abnormality detection unit 10C is latched in the register 140C at the rising edge of the error synchronization clock signal 1406, and further, the error synchronization clock signal 14 in the register 140D.
It is latched at the rising edge of 06.

Here, both latch outputs 1407 and 1408
If NAND is taken, the error synchronization signal 1 of 2 clock width
From 401, it is possible to monitor whether it is pseudo-normal. The selector 140F monitors whether the error signal 1400 has a width of 2 clocks when the error signal 1400 is abnormal at "H" level.

Specifically, the error signal 1400 is "H".
At the time of level, the NOR output 1409 is selected by the selector 140F. At this time, the selector 140F outputs an "L" level of one clock width indicating pseudo normality when the error synchronization signal of two clock width is output, and an error signal 1400 is output when the error synchronization signal of one clock width is an error fault. The "H" level as it is is output. Select output 1 like this
The register 140G to which 410 has been input outputs "H" level at the time of failure and "L" level at the time of no failure or pseudo normal by the clock signal 1411 from the control unit 140H.

Although the method of periodically adding the fault detection data as in the first embodiment is useful in a device which is connected in a one-to-one connection, the fault detection data addition unit and the fault detection unit are connected to each other. In a device (switch, etc.) that changes the data route in, or in a configuration in which data is input from one or more fault detection data addition units to one fault detection unit (multiplex transmission line, etc.), it is added periodically. Then the periodicity collapses. For example, when "normal, abnormal, normal" data is input,
If "abnormal" data is omitted, it becomes "normal, normal" data, and the periodicity is lost.

In such a case, the fault detection data is randomly added as in the second embodiment. According to this method, even in the above configuration, the normality of the functional operation of the fault detection data addition unit, the fault detection unit, the fault concentrator, and the transmission line components at the time of the fault and non-fault is due to the loss or insertion of data. Is not affected by For example, if "normal, normal, abnormal" data is input and the "normal" data is omitted, it becomes "normal, abnormal" data, but "normal" data and "abnormal" data
"Normal" or "abnormal" in the data sync signal as a data distinction
Since the distinction is written, it is not affected by data loss or insertion.

Therefore, according to the configuration of the second embodiment, even in the case of detecting a transmission line fault between the processing blocks connected in a one-to-many manner, a plurality-to-one manner, and a plurality-to-many manner, the software is used to detect the failure from the host device. Fault monitoring can be constantly monitored in real time on the actual operation without intervention.

As an application example, according to the present invention, even in the data bus of the interface between the fault concentrator 10E and the higher-level device 3 in FIG. 1, the fault concentrator, CPU bus,
In order to constantly monitor the normality of the CPU, a fault detection data addition unit and a fault detection unit are provided, and when the CPU reads the fault of the lower device, the normality and abnormality are added to the fault inspection data at each access. By doing so, it is possible to detect failures during normal operation and abnormal operation.

Further, in a configuration for detecting a memory failure at a front stage and a rear stage of a memory such as a FIFO memory in which writing and reading are sequential, when a bit for fault detection is provided together with data to detect the normality of data, ,
By providing the fault detection data adding section, the fault detecting section, and the fault concentrating section, faults can be detected during normal operation and abnormal operation.

Besides, it goes without saying that the present invention is not limited to the above-described embodiments, and can be similarly implemented even if various modifications are made without departing from the gist of the present invention.

[0090]

As described above, according to the present invention, it is possible to provide a fault monitoring apparatus capable of confirming the normality of the monitoring function in real time without the need for software processing on the host apparatus side.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration when a processing block of a data processing device is connected in a one-to-one connection as a first embodiment of a fault monitoring device according to the present invention.

FIG. 2 is a block circuit diagram showing a specific configuration of a fault detection data addition section of the embodiment.

FIG. 3 is a diagram showing a data format of input data of a failure detection data addition unit of the embodiment.

4 is a diagram showing a signal timing waveform of each part of the fault detection data addition part of FIG. 2;

FIG. 5 is a block circuit diagram showing a specific configuration of a failure detection unit of the same embodiment.

6 is a diagram showing a signal timing waveform of each part of the failure detection unit of FIG.

FIG. 7 is a block circuit diagram showing a specific configuration of a fault concentrator of the embodiment.

8 is a diagram showing a signal timing waveform of each part of the obstacle concentrator of FIG.

FIG. 9 is a block circuit diagram showing a specific configuration of a fault detection data adding section according to a second example of the present invention.

10 is a block circuit diagram showing a specific configuration of the pulse expansion circuit of FIG.

11 is a diagram showing signal timing waveforms of respective parts of the fault detection data adding section having the configurations of FIGS. 9 and 10. FIG.

FIG. 12 is a block circuit diagram showing a specific configuration of a failure detection unit of the second embodiment.

FIG. 13 is a diagram showing signal timing waveforms of respective parts of the failure detection unit configured as shown in FIG. 12;

FIG. 14 is a block circuit diagram showing a specific configuration of a fault line concentrator of the second embodiment.

15 is a diagram showing a signal timing waveform of each part of the fault concentrating section having the configuration of FIG. 14;

[Explanation of symbols]

 1, 2 ... Processing block 3 ... Host device 10A, 10C ... Fault detection unit 10B, 10D ... Fault detection data addition unit 10F ... Control unit 10E ... Fault concentrating unit 100, 101, 102 ... Data transmission path 20A, 20I ... Delay Circuit 20B ... Parity normal operation unit 20C ... Parity pseudo-normal operation unit 20D, 20H ... Register unit 20E ... Control unit 20F, 20G ... Selector unit 50A ... Parity operation unit 50B ... Control unit 50C ... Register 70A ... Alternate waveform abnormality detection unit 70B ... Fault holding circuit 70C, 70D ... Register 70F ... EX-NOR gate 90A ... Delay circuit 90B ... Parity normal operation part 90C ... Parity pseudo normal operation part 90D, 90H ... Register part 90E ... Control part 90F, 90G ... Selector part 90I ... Pulse stretching circuit 100A, 00B, 100D ... Register 100C ... OR gate 100E ... Selector 120A ... Parity computing section 120B ... Control section 120C ... Register 140A ... Pulse width monitoring section 140B ... Fault holding circuit 140C, 140D, 140G ... Register 140E ... NAND gate 140F ... Selector 140H … Control section

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06F 15/16 B H04L 12/24 12/26

Claims (4)

[Claims] 1. A fault detection device for detecting a transmission line fault between processing blocks connected one-to-one in a data processing device, wherein a fault detection indicating "normal" or "abnormal" in data to a subsequent processing block is detected. Error detection data addition unit that alternately adds data for periodicity with the periodicity, and the "normal" from the data from the previous processing block,
A fault detection unit that alternately detects fault detection data indicating "abnormal" with a periodicity, and outputs a fault detection signal indicating "no error" at the time of detection, and "error" at the time of non-detection, and a fault detection unit from this fault detection unit. A fault detecting device comprising: a fault concentrator that monitors a fault detection signal that is output and alternately discriminates between "no error" and "presence of error" with periodicity. 2. A failure detecting apparatus for detecting a transmission path failure between processing blocks connected in a one-to-many manner, a plurality-to-one manner, and a plurality-to-many manner in a data processing apparatus, wherein data to a subsequent processing block is "normal". , While adding fault detection data representing "abnormal" in any order,
A fault detection data addition unit that adds identification data indicating the content of the added data, and the identification data that is added to the data from the processing block in the previous stage is detected, and the fault detection data corresponding to this identification data is detected. Then, a failure detection unit that outputs a failure detection signal indicating “no error” at the time of detection and “error present” at the time of undetectable together with the identification data, and a failure detection signal output from this failure detection unit as the identification data. A fault detecting device, comprising: a fault concentrator that monitors on the basis of whether there is an error or whether there is an error. 3. The fault concentrator has a function of notifying a host device of a determination result.
The fault detection device according to any one of the above. 4. The fault detection apparatus according to claim 1, further comprising an initialization unit that initializes the processing of the fault detection data addition unit and the fault detection unit.