JP2002246917A - Parity check system and parity check method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a parity check system which is capable of detecting errors in all the region of transmission data with a one parity comparison operation. SOLUTION: Transmission data, n rows by m columns, are transmitted, in such a manner that vertical parity bits as to the horizontal parity bits of each row are added to at least one of n rows. A vertical parity generating circuit 6 operates vertical parity bits as to each row of the above data, a horizontal parity generating circuit 8 operates horizontal parity bits as to the vertical parity bits outputted from the vertical parity generating circuit 6, and a comparison circuit 10 compares the vertical parity bits added to the above data with the horizontal parity bits outputted from the horizontal parity generating circuit 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity check method and a parity check method, and more particularly, to a transmission side, in which at least one row of horizontal parity bits of n rows.times.m columns of data is provided in at least one row of the data. The present invention relates to a parity check method and a parity check method in an added data transmission system.

[0002]

2. Description of the Related Art A parity check circuit generally requires maintenance of a package in the operation of a transmission apparatus which mainly performs digital processing such as multiplexing, demultiplexing, line termination, data editing, and circuit editing. It has a function to self-monitor hardware faults to a certain extent and notify the outside.

However, errors occurring in data transmission or data processing often occur at the same time. In normal path monitoring, that is, only a vertical parity check method or a horizontal parity check method that can support a path format is used. In such a case, when an error occurs in a plurality of bits at the same time, the detection capability is reduced. As described above, even when an error occurs in a plurality of bits at the same time, it is required to prevent the detection capability from lowering.

In order to respond to such a demand, there has conventionally been a parity check method shown in FIGS. FIG. 5 is a diagram showing a configuration of a conventional vertical parity check system, and FIG. 7 is a diagram showing a configuration of a conventional horizontal parity check system. In FIG. 5, the conventional vertical parity check method includes a shift circuit 100 and a vertical parity generation circuit 110 on the transmission side, and a shift circuit 130 similar to the transmission side and a similar shift circuit 130 on the reception side on the reception side. Vertical parity generation circuit 1
40, and a comparison circuit 150 that receives the outputs of the vertical parity generation circuits 110 and 140 as inputs.

FIG. 6 is a time chart for explaining the operation of the vertical parity check system shown in FIG.
(A) is a time chart for explaining the operation on the transmission side, and (b) is a time chart for explaining the operation on the reception side. 5 and 6, the shift circuit 100
Outputs four transmission data in which data on the same time axis is shifted by giving predetermined delays different from each other to the transmission data (A to L).

The vertical parity generation circuit 110
The data "D, C,
By performing a vertical parity operation on "B, A", a vertical parity bit P1 is generated and output. Similarly, the vertical parity generation circuit 110 outputs a vertical parity bit P2 for “H, G, F, E” and a vertical parity bit P3 for “L, K, J, I”.

On the receiving side, the shift circuit 130 adds shift data to the received data arriving via the data line 120.
A delay is given in the same way as 00, and four transmission data in which data on the same time axis is shifted are output. Then, the vertical parity generation circuit 140
Similarly, the vertical parity bit P1 ′ for “D, C, B, A”, the vertical parity bit P2 ′ for “H, G, F, E” and the vertical parity bit P2 ′ for “L, K, J, I” A parity bit P3 'is generated and output.

In the comparison circuit 150, P1 and P1 'are compared, P2 and P2' are compared, and P3 and P3 'are compared. As a result, when a mismatch is detected (for example, as shown in FIG. 6B, P3 and P3 'are mismatched), it is treated as an error in the received data.

Referring to FIG. 7, the conventional horizontal parity check system has a shift circuit 200, a latch circuit 210, and a horizontal parity generation circuit 220 on the transmission side, and a horizontal parity generation circuit on the reception side. 240 and a multiplex line 250.

FIG. 8 is a time chart for explaining the operation of the horizontal parity check system shown in FIG.
(A) is a time chart for explaining the operation on the transmission side, and (b) is a time chart for explaining the operation on the reception side. 7 and 8, the shift circuit 200
Outputs four transmission data in which data on the same time axis is shifted by giving predetermined delays different from each other to the transmission data (A to L).

The horizontal parity generation circuit 220
A horizontal parity operation is performed on each of the four transmission data input via the latch circuit 210. Specifically, the horizontal parity generation circuit 220 outputs “D, H, L”,
A horizontal parity operation is performed on each of “C, G, K”, “B, F, J” and “A, E, I”, and horizontal parity bits P4, P3, P2, and P1, which are the operation results, correspond to respective data. Append to the end of and output.

On the receiving side, four pieces of received data arriving via the data line 230 are used by the horizontal parity generation circuit 240.
Is input to Then, the horizontal parity generation circuit 240
Are “D, H,
L "," C, G, K "," B, F, J "and" A, E,
The horizontal parity bits P4 ', P3', P2 ', and P1', which are the calculation results, are added to the end of the corresponding data and output.

In the multiplex line 250, P4 and P4 'are compared, P3 and P3' are compared, and P2 and P2 'are compared.
Are compared, and P1 and P1 ′ are compared. As a result, when a mismatch is detected, the received data is treated as having an error.

[0014]

However, in the above-mentioned conventional vertical parity check method, in order to detect that a data error has occurred in transmission data, the comparison circuit 150 compares P1 with P1 ', and compares P1 with P1'. Compare with P2 '
Since it is necessary to sequentially compare each parity bit such as comparing 3 with P3 ', there is a problem that a certain amount of time is required for the parity check. Further, the above-mentioned conventional horizontal parity check method has a similar problem.

In the above-described conventional vertical parity check method and horizontal parity check method, if the parity bit calculated on the transmission side does not match the parity bit calculated on the reception side, the normality of the circuit used is determined. Irrespective of line error (data error during transmission)
There is a problem that is treated as.

As a prior art, Japanese Patent Application Laid-Open No. 62-273
Although there is a semiconductor memory with an error correction circuit using the horizontal / vertical parity check system disclosed in Japanese Patent Application Laid-Open No. 700-700, there is a problem that even with this horizontal / vertical parity check system, it is not possible to detect an abnormality of the parity check circuit used.

A first object of the present invention is to provide a parity check method and a parity check method that can realize error detection for all data areas of transmission data by one parity comparison operation.

A second object of the present invention is to provide a parity check method and a parity check method capable of detecting a failure of a circuit used.

[0019]

According to the parity check method of the present invention, a horizontal parity bit for each row of data of n (n is a positive integer) rows × m (m is a positive integer) column is determined on the transmitting side. A parity check method in a data transmission system in which the vertical parity bits are added to at least one row of the data, and a receiving side performs a first vertical parity operation on each column of the data; Horizontal parity calculating means for performing a first horizontal parity calculation on the result of the first vertical parity calculation; and comparing means for comparing the result of the first horizontal parity calculation with the vertical parity bit. And

Further, in the parity check method, on the transmitting side, each of the n horizontal parity bits is further added to each row of the corresponding data,
The vertical parity calculation means further performs a second vertical parity calculation on the column of the n horizontal parity bits, and the horizontal parity calculation means further performs a second horizontal parity calculation on each row of the data. The comparing means further compares each result of the second horizontal parity operation with the corresponding horizontal parity bit, and further compares the result of the second vertical parity operation with the result of the first horizontal parity operation. 2. The method according to claim 1, wherein
The parity check method described. .

In the parity check method according to the present invention, the vertical parity bit of the horizontal parity bit for each row of data of n (n is a positive integer) row × m (m is a positive integer) column is determined on the transmitting side. A parity check method in a data transmission system added to at least one row of data, the method comprising: performing a first vertical parity operation on each column of the received data at a receiving side; And a comparing step of comparing the result of the first horizontal parity operation with the received vertical parity bit. And

Further, in the parity check method, on the transmitting side, each of the n horizontal parity bits is further added to each row of the corresponding data,
The vertical parity calculation step includes performing a second vertical parity calculation on the received column of the n horizontal parity bits, and the horizontal parity calculation step includes performing a second vertical parity calculation on each row of the received data. Performing said horizontal parity operation, wherein said comparing step includes a step of comparing each result of said second horizontal parity operation with a corresponding received said horizontal parity bit, and said second vertical parity operation And comparing the result of the first horizontal parity operation with the result of the first horizontal parity operation.

The operation of the present invention is as follows. n rows x m
The column data is transmitted with the vertical parity bit for the horizontal parity bit for each row added to at least one of the n rows. The vertical parity calculating means on the receiving side performs a first vertical parity calculation on each column of the data, and the horizontal parity calculating means on the receiving side comprises:
A first horizontal parity operation is performed on the first vertical parity operation result, and the comparing means on the receiving side compares the vertical parity bit added to the data with the first horizontal parity operation result. In the data, each of the horizontal parity bits for each row is further added to the corresponding row. The vertical parity calculation means further performs a second vertical parity calculation on the column of horizontal parity bits added to the data, and the horizontal parity calculation means further performs a second horizontal parity calculation on each row of the data. The means further compares each result of the second horizontal parity operation with a corresponding horizontal parity bit added to the data, and further compares the second vertical parity operation result and the first horizontal parity operation result. Compare.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a parity check system according to a first embodiment of the present invention. In all the drawings shown below, equivalent parts are denoted by the same reference numerals. In FIG. 1, the parity check method according to the present embodiment includes a horizontal parity generation circuit 3 on the transmitting side.
And a vertical parity generation circuit 4, and a data line 5
On the receiving side that receives data arriving via the above, a vertical parity generation circuit 6, a selector 7, a horizontal parity generation circuit 8, and comparison circuits 9 and 10 are provided. 1 is transmission data, and 2 is reception data.

The horizontal parity generation circuit 3 transmits the transmission data 1
, A horizontal parity bit, which is the result of the horizontal parity operation, is added to the end of the transmission data 1 and output, and the horizontal parity bit is output to the vertical parity generation circuit 4. The vertical parity generation circuit 4 performs a vertical parity operation on the horizontal parity bits from the horizontal parity generation circuit 3 and outputs a vertical parity bit as a result of the vertical parity operation.

Thus, the vertical parity bit output from the vertical parity generation circuit 4 is added after the horizontal parity bit added to the end of the transmission data 1. In this way, the transmission data 1 is transmitted with the parity bit of 2 bits added to the end.

The received data 2 arriving at the receiving side via the data line 5 is input to a higher-level device (not shown) and is also input to the vertical parity generation circuit 6 and the selector 7. The vertical parity generation circuit 6 performs a vertical parity operation on the input received data 2 and outputs the operation result to the selector 7.

The selector 7 receives the input data line 5
The selected data 2 and the calculation result from the vertical parity generation circuit 6 are selectively controlled and output to the horizontal parity generation circuit 8 and the comparison circuit 9. The horizontal parity generation circuit 8 performs a horizontal parity operation on the output of the selector 7 and outputs the operation result to the comparison circuits 9 and 10.

The comparison circuit 9 compares the output of the selector 7 with the operation result from the horizontal parity generation circuit 8. Since the received data 2 from the data line 5 is input to the comparison circuit 10, the comparison circuit 10 compares this with the operation result from the horizontal parity generation circuit 8.

FIG. 2 is a diagram showing a more specific configuration of the parity check system shown in FIG. 2 and 1, transmission data 1 is 1-1 to 1-n (n is a positive integer)
, And the column is m (m is a positive integer) column.

The horizontal parity generation circuit 3 performs a horizontal parity operation on the transmission data 1-1 (m bits), outputs a horizontal parity bit as a result of the operation to the vertical parity generation circuit 4, and outputs 1-
1 and a horizontal parity generation circuit 3 that performs the same processing on the transmission data 1-2 (m bits) as the horizontal parity generation circuit 3-1.
-2, and horizontal parity generation circuits 3-3 to 3-n for performing the same processing.

As described above, on the transmitting side, each output of the horizontal parity generation circuits 3-1 to 3-n is connected to the corresponding signal line out of the n signal lines, and It is connected. At the end of each of the transmission data 1-1 to 1-n, a corresponding horizontal parity generation circuit 3-1 to 1-n
3-n output and the vertical parity bit output from the vertical parity generation circuit 4 are added, and received by the reception buffer 12 via the transmission buffer 11 and the data line 5.

On the receiving side, n signal lines from the receiving buffer 12 are connected to the vertical parity generating circuit 6 and the selector 7. One input of the comparison circuit 10 is connected to one of the n signal lines (the reception data 2-
1 is transmitted. In addition, the reception data 2 is reception data of n rows of 2-1 to 2-n, and columns are m + 2 columns.

Next, the operation of the parity check system according to the first embodiment of the present invention will be described with reference to the drawings.
FIG. 3 is a time chart for explaining the operation of the parity check method shown in FIGS. 1 and 2, (a) is a time chart for explaining the operation on the transmission side,
(B) is a time chart for explaining the operation on the receiving side, and (c) is a time chart for explaining the operation of the comparison circuits 9 and 10.

First, the operation on the transmitting side will be described. 3A and 2, transmission data 1-1 is input to a horizontal parity generation circuit 3-1. The horizontal parity generation circuit 3-1 performs a horizontal parity operation on the transmission data 1-1. As a result, the horizontal parity bit A1, which is the result of the horizontal parity operation, is added to the end of the transmission data 1-1.

Similarly, the horizontal parity generation circuit 3-2
A horizontal parity operation is performed on the corresponding transmission data 1-2. As a result, the horizontal parity bit A2, which is the result of the horizontal parity operation, is added to the end of the transmission data 1-2. Similarly, for each of the transmission data 1-3 to 1-n, the corresponding horizontal parity generation circuit 3-3 to 3-3
With −n, each horizontal parity bit A3 to An corresponding to the end is added.

The horizontal parity bits A1 to An output from the horizontal parity generation circuits 3-1 to 3-n are input to the vertical parity generation circuit 4, and the vertical parity generation circuit 4
N horizontal parity bits A1 to A on the same time axis
A vertical parity operation is performed for n, and a vertical parity bit B, which is the result of the operation, is output (“vertical parity generation circuit 4 output” in FIG. 3A). Then, a vertical parity bit B which is an output of the vertical parity generation circuit 4 is added after each of the horizontal parity bits A1 to An added to the end of each transmission data 1-1 to 1-n. That is,
Data shown in “transmission data 1-1 to 1-n” in FIG. 3A is input to the reception buffer 12 via the transmission buffer 11 and the data line 5.

Next, the operation on the receiving side will be described. In FIGS. 3B and 2, received data 2-1 to 2-n received and output by the reception buffer 12 are shown in FIG.
This is data shown in “Received data 2-1 to 2-n” in (b). These received data 2-1 to 2-n are input to the vertical parity generation circuit 6 and the selector 7, respectively. The vertical parity generation circuit 6 performs a vertical parity operation on n bits on the same time axis of each of the first to (m + 1) th columns of the received data 2-1 to 2-n.

That is, a vertical parity bit C1 for n bits in the first column of the received data 2-1 to 2-n;
Similarly, the vertical parity bits C2 to Cm for n bits of each of the second to m-th columns of the reception data 2-1 to 2-n
And a vertical parity bit B ′ for n bits (horizontal parity bits A1 to An) of the (m + 1) th column of the received data 2-1 to 2-n are generated and output (FIG. 3B).
"Output of vertical parity generation circuit 6"). Note that the vertical parity bit B ′ is equivalent to the vertical parity bit B.

The selector 7 selects and controls the received data 2-1 to 2-n and the operation result of the vertical parity generation circuit 6 (“output of the vertical parity generation circuit 6” in FIG. 3B). And output. Here, when the selector 7 selects and outputs the received data 2-1, the received data 2-1 is input to the horizontal parity generation circuit 8 and the comparison circuit 9. At this time, the horizontal parity generation circuit 8 outputs the received data 2-1.
The horizontal parity bit A1 'is generated and output by performing a horizontal parity operation on the data excluding the horizontal parity bit A1 and the vertical parity bit B in the data ("output from the horizontal parity generation circuit 8 in FIG. 3B"). 1 "). Note that the horizontal parity bit A1 'is the horizontal parity bit A
Equivalent to 1.

Similarly, the selector 7 sets the received data 2-2 to 2-2.
2-n is selected and output, the received data 2-2
.About.2-n are input to the horizontal parity generation circuit 8 and the comparison circuit 9, respectively. At this time, the horizontal parity generation circuit 8 performs a horizontal parity operation in the same manner, so that
Generate and output the horizontal parity bits A2 ′ to An ′ (“horizontal parity generation circuit 8 output-2” in FIG. 3B)
"Horizontal parity generation circuit 8 output-n"). Note that each of the horizontal parity bits A2 'to An' is equivalent to the corresponding horizontal parity bits A2 to An.

When the selector 7 selects and outputs the operation result of the vertical parity generation circuit 6, the operation result of the vertical parity generation circuit 6 is input to the horizontal parity generation circuit 8 and the comparison circuit 9, respectively. At this time, the horizontal parity generation circuit 8 performs the horizontal parity operation on the data (vertical parity bits C1 to Cm) excluding the vertical parity bit B ′ in the operation result of the vertical parity generation circuit 6, thereby obtaining the horizontal parity bit B. Is generated and output (FIG. 3
(B) “Horizontal parity generation circuit 8 output−n + 1”).
Note that the horizontal parity bit B ″ is the vertical parity bit B
And B '.

Next, the operation of the comparison circuits 9 and 10 will be described. 3C and 2, the selection signal indicates the timing at which the selector 7 selects the reception data 2-1 to 2-n and the output of the vertical parity generation circuit 6.
The selector 7 selects and outputs the input signal according to the selection signal (“selection signal” and “output of selector 7” in FIG. 3C).
That is, the selector 7 selects and outputs the received data 2-1, the received data 2-2,..., The received data 2-n, and the output of the vertical parity generation circuit 6 in this order.

First, when the selector 7 outputs the reception data 2-1, the reception data 2-1 and the output-1 of the horizontal parity generation circuit 8 shown in FIG. . Then, the comparison circuit 9 compares the horizontal parity bit A1 with the horizontal parity bit A1 ′. Similarly, when the selector 7 sequentially outputs the received data 2-2 to 2-n, the comparison circuit 9 outputs the horizontal parity bits A2 to A2.
An and the corresponding horizontal parity bits A2 ′ to An ′ are sequentially compared.

When the selector 7 outputs the operation result of the vertical parity generation circuit 6, the operation result of the vertical parity generation circuit 6 and the output of the horizontal parity generation circuit 8 shown in FIG. n + 1 is input.
Therefore, the comparison circuit 9 compares the vertical parity bit B ′ with the horizontal parity bit B ″. At this time, the comparison circuit 10 has the output −n + 1 of the horizontal parity generation circuit 8 shown in FIG. Input and received data 2-1
Is also input, the comparison circuit 10 compares the vertical parity bit B with the horizontal parity bit B ″ (“comparison circuit 9” and “comparison circuit 10” in FIG. 3C).

FIG. 4 shows the comparison circuits 9 and 1 shown in FIGS.
FIG. 9 is a diagram for explaining the content of judgment based on a comparison result of 0. In FIG. 4, when an odd number of errors occur in each of the received data 1-1 to 1-n (excluding the vertical parity bit B), the comparison result of the comparison circuit 9 is Ak.
≠ Ak ′ (k is 1 to n) and B ″ ≠ B ′, and the parity check circuit used in this method is normal,
It can be determined that a line error has occurred. In this case, similarly to the conventional horizontal parity method, an error occurrence location can be specified for each row.

When Ak ≠ Ak ′, B ″ ≠ B ′ always holds, so if the comparison result of the comparison circuit 9 is AkＡAk ′ and B ″ = B ′, or
When k = Ak ′ and B ″ ≠ B ′, it can be determined that the parity check circuit used in the present method has a failure.

Further, of the received data 2-1 to 2-n, the entire data area excluding the horizontal parity bit Ak and the vertical parity bit B area (that is, the transmission data 1-1 to 2-n)
In the case where an odd number of errors have occurred in the entire data area 1-n), or in the case where an error has occurred in the vertical parity bit B of the received data 1-1, the comparison result of the comparison circuit 10 is B "≠ B" and it can be determined that a line error has occurred.

At this time, Ak and A are determined in order to determine the normality of the parity check circuit used in this system.
By using the comparison result of k ′ and the comparison result of B ″ and B ′, it is possible to determine whether a line error has occurred or the parity check circuit is abnormal.

Naturally, the comparison circuits 9 and 10
If the comparison result is Ak = Ak ', B "= B' and B" = B, it can be determined that the line and the parity check circuit are normal.

As described above, by comparing the vertical parity bit B generated on the transmission side with the horizontal parity bit B ″ generated on the reception side, parity check in both the vertical direction and the horizontal direction can be performed simultaneously. As a result, only one comparison operation of the vertical parity bit B and the horizontal parity bit B ″ is performed, and the transmission data 1-1 to 1- 1
It is possible to detect whether or not an error has occurred in all of the n data areas.

Further, by comparing the horizontal parity bit Ak 'generated on the transmission side with the horizontal parity bit Ak' generated on the reception side, the parity check in the horizontal direction can be performed at regular intervals. An error occurrence location can be specified for each line. Further, along with the comparison between the horizontal parity bits Ak and Ak ′, the horizontal parity bits B ″
And the vertical parity bit B ′ generated on the receiving side, it is possible to detect the normality of the parity check circuit.

Next, a second embodiment of the present invention will be described. In the parity check method according to the first embodiment of the present invention, a horizontal parity operation is performed on each row of transmission data of n rows × m columns on the transmission side, and the result of this operation is a column of n horizontal parity bits (Ak Column), a vertical parity bit B, which is the result of the calculation, is added to each row of the transmission data and transmitted.

On the other hand, in the parity check method according to the second embodiment of the present invention, the transmitting side performs a vertical parity operation on each column of transmission data of n rows × m columns, and obtains a vertical parity operation result. It is assumed that a horizontal parity operation is performed on a row of parity bits (m bits), and a horizontal parity bit, which is a result of the operation, is added to the end of each row of transmission data and transmitted.

On the receiving side, a horizontal parity operation is performed for each row of the received transmission data of n rows × m columns (hereinafter, referred to as reception data), and a vertical parity bit (n bits) obtained as a result of the operation is subjected to a vertical parity operation. Perform the operation,
The vertical parity bit, which is the result of this operation, is compared with one of the horizontal parity bits added to the end of each row of the received data.

Thus, in the parity check system according to the second embodiment, a comparison operation equivalent to the comparison operation between B "and B in the parity check system according to the first embodiment can be realized. It is possible to detect whether or not an error has occurred in all data areas of the transmission data of n rows × m columns only once.

It should be noted that the present invention is not limited to the above embodiments, but can be appropriately modified within the scope of the technical idea of the present invention.

[0058]

A first effect of the present invention is that error detection for all data areas of transmission data can be realized by one parity comparison operation. The reason is that the vertical parity bit for the horizontal parity bit for each row of the data of n rows × m columns calculated on the transmitting side and the vertical parity bit for each column of the data of n rows × m columns calculated on the receiving side. By comparing the parity bit with a horizontal parity bit (hereinafter, referred to as a first horizontal parity bit),
This is because parity check in both the vertical direction and the horizontal direction can be simultaneously performed.

A second effect of the present invention is that a failure of a circuit to be used can be detected. The reason is that a horizontal parity bit (hereinafter, referred to as a second horizontal parity bit) for each row of n rows × m columns of data calculated on the transmission side and an n rows × m columns of data calculated on the reception side are used. This is because the horizontal parity bits for each row of data are compared with each other, and the vertical parity bits calculated on the receiving side for the second horizontal parity bits are compared with the first horizontal parity bits. . Also,
As a result, it is possible to specify an error occurrence location for each row.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a parity check system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a more specific configuration of the parity check method shown in FIG.

FIG. 3 is a time chart for explaining an operation of the parity check method shown in FIGS. 1 and 2;
3 is a time chart for explaining the operation on the transmission side, FIG. 3B is a time chart for explaining the operation on the reception side, and FIG. 3C is a time chart for explaining the operation of the comparison circuits 9 and 10.

FIG. 4 is a diagram for explaining judgment contents from comparison results of comparison circuits 9 and 10 shown in FIGS. 1 and 2;

FIG. 5 is a diagram showing a configuration of a conventional vertical parity check method.

6 is a time chart for explaining the operation of the vertical parity check method shown in FIG. 5, wherein (a) is a time chart for explaining the operation on the transmission side, and (b) is a time chart for explaining the operation on the reception side. It is a time chart for performing.

FIG. 7 is a diagram showing a configuration of a conventional horizontal parity check method.

8A and 8B are time charts for explaining the operation of the horizontal parity check method shown in FIG. 7, wherein FIG. 8A is a time chart for explaining the operation on the transmission side, and FIG. It is a time chart for performing.

[Explanation of symbols]

 3, 8 horizontal parity generation circuit 4, 6 vertical parity generation circuit 5 data line 7 selector 9, 10 comparison circuit 11 transmission buffer 12 reception buffer

Claims (5)

[Claims] 1. On the transmitting side, n (n is a positive integer) rows × m
(M is a positive integer) a parity check method in a data transmission system in which a vertical parity bit for a horizontal parity bit for each row of column data is added to at least one row of the data; Vertical parity calculation means for performing a first vertical parity calculation on each column of; a horizontal parity calculation means for performing a first horizontal parity calculation on the result of the first vertical parity calculation; A parity check method comprising: comparison means for comparing a result with the vertical parity bit. 2. The transmitting side, wherein each of the n pieces of the horizontal parity bits is further added to each row of the corresponding data, and the vertical parity calculating means includes: Further performing a second vertical parity operation, the horizontal parity operation means further performing a second horizontal parity operation for each row of the data, and the comparing means corresponding to each result of the second horizontal parity operation Further comparing the horizontal parity bit, and further comparing the result of the second vertical parity operation with the first parity bit.
2. The parity check method according to claim 1, wherein the result of the horizontal parity calculation is compared with the result of the parity check. 3. On the transmitting side, n (n is a positive integer) rows × m
(M is a positive integer) A parity check method in a data transmission system in which a vertical parity bit for a horizontal parity bit for each row of data in a column is added to at least one row of the data. A vertical parity calculation step of performing a first vertical parity calculation on each column of the data; a horizontal parity calculation step of performing a first horizontal parity calculation on a result of the first vertical parity calculation; A parity check method comprising: comparing a result of a parity operation with the received vertical parity bit. 4. The transmitting side, wherein each of the n horizontal parity bits is further added to each corresponding row of the data, and the vertical parity calculating step includes the step of: receiving the n horizontal parity bits received. Performing a second vertical parity operation on the columns of the above, the horizontal parity operation step includes performing a second horizontal parity operation on each row of the received data, and the comparing step includes: Comparing each result of the second horizontal parity operation with the corresponding received horizontal parity bit, and comparing the result of the second vertical parity operation with the result of the first horizontal parity operation 4. The parity check method according to claim 3, comprising: 5. On the transmitting side, n (n is a positive integer) rows × m
(M is a positive integer) a parity check method in a data transmission system in which a horizontal parity bit for a vertical parity bit for each column of data is added to at least one row of the data; Horizontal parity calculation means for performing a horizontal parity calculation on each row of data; vertical parity calculation means for performing a vertical parity calculation on the result of the horizontal parity calculation; and comparison means for comparing the result of the vertical parity calculation with the horizontal parity bit And a parity check method.