JPH11274229A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH11274229A JPH11274229A JP7597598A JP7597598A JPH11274229A JP H11274229 A JPH11274229 A JP H11274229A JP 7597598 A JP7597598 A JP 7597598A JP 7597598 A JP7597598 A JP 7597598A JP H11274229 A JPH11274229 A JP H11274229A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor device
- electrode
- semiconductor
- strain detecting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Pressure Sensors (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップを基
板へ実装する際等にかかるストレスを検出することので
きる半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of detecting stress applied when a semiconductor chip is mounted on a substrate.
【０００２】[0002]
【従来の技術】従来、半導体チップを基板へ実装する際
等にかかるストレスの分布を解析、評価する場合、故障
モードの解析やシミュレーションによる解析を行う必要
があった。2. Description of the Related Art Conventionally, when analyzing and evaluating the distribution of stress applied when a semiconductor chip is mounted on a substrate, it has been necessary to analyze a failure mode or analyze by simulation.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上述の
ような解析、評価の方法においては、モデルパターンの
作成が必要になり、この作業に多大の時間を要してしま
うという問題があった。However, in the above-described analysis and evaluation methods, there is a problem that a model pattern needs to be created, and this operation requires a lot of time.
【０００４】本発明は、上記の点に鑑みてなしたもので
あり、その目的とするところは、半導体チップにかかる
ストレスを容易に検出することのできる半導体装置を提
供することにある。[0004] The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device which can easily detect stress applied to a semiconductor chip.
【０００５】[0005]
【課題を解決するための手段】請求項１記載の発明は、
半導体チップを基板上に実装してなる半導体装置であっ
て、半導体チップ内の所定個所に該半導体チップの歪み
を検出するための歪み検出素子を同一方向に複数個形成
し、該歪み検出素子に電気信号を印加するとともに歪み
検出素子からの出力を外部へ取り出すための電極を形成
し、前記基板には、前記電極と接続するための測定用端
子を形成し、該測定用端子と前記電極とを接続するよう
にしたことを特徴とするものである。According to the first aspect of the present invention,
A semiconductor device in which a semiconductor chip is mounted on a substrate, wherein a plurality of strain detecting elements for detecting strain of the semiconductor chip are formed at predetermined locations in the semiconductor chip in the same direction, and An electrode for applying an electric signal and taking out an output from the strain detection element to the outside is formed, and on the substrate, a measurement terminal for connecting to the electrode is formed, and the measurement terminal and the electrode are formed. Are connected.
【０００６】請求項２記載の発明は、請求項１記載の半
導体装置において、前記歪み検出素子を半導体チップ内
の全面に均一に分散配置させるようにしたことを特徴と
するものである。According to a second aspect of the present invention, in the semiconductor device of the first aspect, the strain detecting elements are uniformly distributed over the entire surface of the semiconductor chip.
【０００７】請求項３記載の発明は、請求項１記載の半
導体装置において、前記歪み検出素子を半導体チップ内
に局所的に配置させるようにしたことを特徴とするもの
である。According to a third aspect of the present invention, in the semiconductor device of the first aspect, the strain detecting element is locally arranged in a semiconductor chip.
【０００８】請求項４記載の発明は、請求項１乃至請求
項３のいずれかに記載の半導体装置において、前記歪み
検出素子を半導体チップ内の表面側と裏面側の同一個所
に各々対応させて配置するようにしたことを特徴とする
ものである。According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the strain detecting elements correspond to the same locations on the front side and the back side in the semiconductor chip, respectively. It is characterized by being arranged.
【０００９】請求項５記載の発明は、請求項１乃至請求
項４のいずれかに記載の半導体装置において、前記半導
体チップの結晶構造として、（１１０）構造を用いるよ
うにしたことを特徴とするものである。According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, a (110) structure is used as a crystal structure of the semiconductor chip. Things.
【００１０】請求項６記載の発明は、請求項１乃至請求
項４のいずれかに記載の半導体装置において、前記半導
体チップの結晶構造として、（１００）構造を用いるよ
うにしたことを特徴とするものである。According to a sixth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, a (100) structure is used as a crystal structure of the semiconductor chip. Things.
【００１１】[0011]
【発明の実施の形態】以下、本発明の実施の形態の一例
を図面に基づき説明する。図１は、本発明の実施の形態
の一例に係る半導体チップの模式図である。本実施形態
の半導体チップ１には、所定個所、つまり、歪みを検出
したい個所に歪み検出素子としての複数のピエゾ抵抗素
子３が形成され、各ピエゾ抵抗素子３の両端近傍には接
続用配線４を介して接続される電極２が形成されてい
る。ピエゾ抵抗素子３は、例えば、シリコンウエハにホ
ウ素をドーピングすることにより形成することができ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of a semiconductor chip according to an example of an embodiment of the present invention. In the semiconductor chip 1 of the present embodiment, a plurality of piezoresistive elements 3 as strain detecting elements are formed at predetermined locations, that is, locations where distortion is desired to be detected, and connection wires 4 are provided near both ends of each piezoresistive element 3. The electrode 2 connected through the electrode 2 is formed. The piezoresistive element 3 can be formed, for example, by doping a silicon wafer with boron.
【００１２】ここで、複数のピエゾ抵抗素子３は、全て
同一方向に配置されるとともに、半導体チップ１の全面
にわたって、均一に分散配置されている。Here, the plurality of piezoresistive elements 3 are all arranged in the same direction, and are uniformly distributed over the entire surface of the semiconductor chip 1.
【００１３】本実施形態の半導体チップ１は、図２に示
すように、半導体チップ１の電極２上にバンプ７を形成
しておき、バンプ７の形成面を測定用端子６の形成され
た基板５の測定用端子６に対向させて、フリップチップ
実装し、さらに、アンダーフィル封止樹脂８による樹脂
封止を行い半導体装置が完成されるのである。As shown in FIG. 2, the semiconductor chip 1 of this embodiment has bumps 7 formed on the electrodes 2 of the semiconductor chip 1 and the surface on which the bumps 7 are formed is formed on the substrate on which the measuring terminals 6 are formed. The semiconductor device is completed by flip-chip mounting, facing the measurement terminal 6 of No. 5, and further by resin sealing with the underfill sealing resin 8.
【００１４】本実施形態の半導体装置では、フリップチ
ップ実装工程やアンダーフィル封止工程等において、半
導体チップ１にストレスがかかり半導体チップ１が歪め
ば、ピエゾ抵抗素子３の抵抗値が変化することになり、
外部から測定用端子６を介して電気信号を印加すること
により、ピエゾ抵抗素子３の抵抗値を測定すれば、この
抵抗値の変化により半導体チップ１の歪みを検出するこ
とができるのである。In the semiconductor device of this embodiment, if the semiconductor chip 1 is stressed in the flip chip mounting step or the underfill sealing step and the semiconductor chip 1 is distorted, the resistance of the piezoresistive element 3 changes. Become
If the resistance of the piezoresistive element 3 is measured by applying an electric signal from the outside via the measuring terminal 6, the distortion of the semiconductor chip 1 can be detected by the change in the resistance.
【００１５】従って、半導体チップ１のピエゾ抵抗素子
３の形成された個所にかかっているストレスが容易に検
出できるようになるのである。なお、歪み検出素子とし
て、ピエゾ抵抗素子３の替りに静電容量型素子を使用し
ても良い。Therefore, the stress applied to the portion of the semiconductor chip 1 where the piezoresistive element 3 is formed can be easily detected. It should be noted that a capacitive element may be used instead of the piezoresistive element 3 as the strain detecting element.
【００１６】本実施形態の半導体装置によれば、ピエゾ
抵抗素子３は、半導体チップ１において、全て同一方向
に配置されているので、フリップチップ実装工程やアン
ダーフィル封止工程での半導体チップ１の特定方向の応
力分布が測定できる。また、ピエゾ抵抗素子３は、半導
体チップ１の全面にわたって、均一に分散配置されてい
るので、フリップチップ実装工程やアンダーフィル封止
工程での半導体チップ１全体にわたる応力分布が測定で
きる。従って、半導体チップ１にかかる特定方向のスト
レス分布を容易に検出することができる。According to the semiconductor device of the present embodiment, since the piezoresistive elements 3 are all arranged in the same direction in the semiconductor chip 1, the piezoresistive elements 3 are mounted in the flip chip mounting step or the underfill sealing step. The stress distribution in a specific direction can be measured. Further, since the piezoresistive elements 3 are uniformly distributed over the entire surface of the semiconductor chip 1, the stress distribution over the entire semiconductor chip 1 in the flip chip mounting step or the underfill sealing step can be measured. Therefore, the stress distribution in the specific direction on the semiconductor chip 1 can be easily detected.
【００１７】本実施形態では、ピエゾ抵抗素子３が半導
体チップ１の全面にわたって、均一に分散配置されてい
るが、局所的に配置すれば、局所的且つ詳細なストレス
分布が検出できる。さらには、図３に示すように、ピエ
ゾ抵抗素子３の方向を変えて配置することにより、斜め
の方向でのストレス分布が検出できるのである。つま
り、ピエゾ抵抗素子３の配置の方向により、種々の方向
のストレス分布が検出できるのである。In the present embodiment, the piezoresistive elements 3 are uniformly distributed over the entire surface of the semiconductor chip 1, but if they are locally disposed, a local and detailed stress distribution can be detected. Further, as shown in FIG. 3, by disposing the piezoresistive elements 3 in different directions, it is possible to detect a stress distribution in an oblique direction. That is, the stress distribution in various directions can be detected depending on the direction of the arrangement of the piezoresistive element 3.
【００１８】また、ピエゾ抵抗素子３を、半導体チップ
１内の表面側と裏面側の同一個所に各々対応させて配置
すれば、半導体チップ１の厚み方向のストレス分布が検
出できる。Further, if the piezoresistive elements 3 are arranged at the same positions on the front surface and the rear surface in the semiconductor chip 1 respectively, the stress distribution in the thickness direction of the semiconductor chip 1 can be detected.
【００１９】半導体チップ１の結晶構造として、（１１
０）構造のものを用いれば、ピエゾ抵抗素子３の縦方向
の応力が以下の式により、絶対値として検出することが
できるのである。（横方向の応力に対する検出感度は劣
っている） ΔＲ＝（π／２）σｙ ΔＲ：ピエゾ抵抗素子３の抵抗値の変化量 π：ピエゾ抵抗係数 σｙ：縦方向応力 半導体チップ１の結晶構造として、（１００）構造のも
のを用いれば、ピエゾ抵抗素子３の縦方向の応力が以下
の式により、絶対値として検出することができるのであ
る。The crystal structure of the semiconductor chip 1 is (11
0) With the use of the structure, the longitudinal stress of the piezoresistive element 3 can be detected as an absolute value by the following equation. ΔR = (π / 2) σy ΔR: amount of change in the resistance value of the piezoresistive element 3 π: piezoresistance coefficient σy: longitudinal stress As the crystal structure of the semiconductor chip 1 , (100), the longitudinal stress of the piezoresistive element 3 can be detected as an absolute value by the following equation.
【００２０】ΔＲ＝（π／２）（σｙ−σｘ） ΔＲ：ピエゾ抵抗素子３の抵抗値の変化量 π：ピエゾ抵抗係数 σｙ：縦方向応力 σｘ：横方向応力 また、半導体チップ１の電極２と基板５の測定用端子６
との接続がワイヤボンディングではなくてバンプ７によ
り行われるので、基板５の測定用端子６の形成位置の自
由度が増す。ΔR = (π / 2) (σy−σx) ΔR: amount of change in resistance value of piezoresistive element 3 π: piezoresistive coefficient σy: longitudinal stress σx: lateral stress Further, electrode 2 of semiconductor chip 1 And measuring terminal 6 of substrate 5
Is connected by the bump 7 instead of by wire bonding, so that the degree of freedom in the position of the measurement terminal 6 on the substrate 5 can be increased.
【００２１】なお、ピエゾ抵抗素子３を半導体チップ１
に形成される回路（図示せず）のない部分に形成してお
けば、ストレスを検査した後の半導体装置であっても通
常の使用をすることができる。The piezoresistive element 3 is connected to the semiconductor chip 1
If it is formed in a portion where no circuit (not shown) is formed, even a semiconductor device after stress inspection can be used normally.
【００２２】[0022]
【発明の効果】以上のように、請求項１記載の発明によ
れば、半導体チップを基板上に実装してなる半導体装置
であって、半導体チップ内の所定個所に該半導体チップ
の歪みを検出するための歪み検出素子を同一方向に複数
個形成し、該歪み検出素子に電気信号を印加するととも
に歪み検出素子からの出力を外部へ取り出すための電極
を形成し、前記基板には、前記電極と接続するための測
定用端子を形成し、該測定用端子と前記電極とを接続す
るようにしたので、半導体チップにかかる特定方向のス
トレスを容易に検出することのできる半導体装置が提供
できた。As described above, according to the first aspect of the present invention, there is provided a semiconductor device in which a semiconductor chip is mounted on a substrate, and distortion of the semiconductor chip is detected at a predetermined position in the semiconductor chip. A plurality of strain detecting elements for forming the same in the same direction, forming an electrode for applying an electric signal to the strain detecting element and extracting an output from the strain detecting element to the outside, and forming the electrode on the substrate. Since a measurement terminal for connecting to the semiconductor chip is formed and the measurement terminal is connected to the electrode, a semiconductor device that can easily detect stress in a specific direction applied to the semiconductor chip can be provided. .
【００２３】請求項２記載の発明によれば、請求項１記
載の半導体装置において、前記歪み検出素子を半導体チ
ップ内の全面に均一に分散配置させるようにすれば、半
導体チップ全面にわたってかかる特定方向のストレスの
分布が容易に検出できる。According to the second aspect of the present invention, in the semiconductor device according to the first aspect, if the strain detecting elements are uniformly distributed over the entire surface of the semiconductor chip, the specific direction in the specific direction over the entire surface of the semiconductor chip is improved. Stress distribution can be easily detected.
【００２４】請求項３記載の発明によれば、請求項１記
載の半導体装置において、前記歪み検出素子を半導体チ
ップ内に局所的に配置させるようにすれば、半導体チッ
プの局所的且つ詳細に特定方向のストレスの分布が容易
に検出できる。According to the third aspect of the present invention, in the semiconductor device according to the first aspect, if the strain detecting element is locally arranged in the semiconductor chip, the semiconductor chip can be specified locally and in detail. The distribution of directional stress can be easily detected.
【００２５】請求項４記載の発明によれば、請求項１乃
至請求項３のいずれかに記載の半導体装置において、前
記歪み検出素子を半導体チップ内の表面側と裏面側の同
一個所に各々対応させて配置するようにすれば、半導体
チップの厚み方向のストレス分布が容易に検出できる。According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the strain detecting elements correspond to the same portions on the front side and the back side in the semiconductor chip, respectively. With such arrangement, the stress distribution in the thickness direction of the semiconductor chip can be easily detected.
【００２６】請求項５記載の発明によれば、請求項１乃
至請求項４のいずれかに記載の半導体装置において、前
記半導体チップの結晶構造として、（１１０）構造を用
いるようにすれば、前記歪み検出素子の応力を特定の式
により、絶対値として検出することができる。According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the (110) structure is used as a crystal structure of the semiconductor chip. The stress of the strain detecting element can be detected as an absolute value by a specific equation.
【００２７】請求項６記載の発明によれば、請求項１乃
至請求項４のいずれかに記載の半導体装置において、前
記半導体チップの結晶構造として、（１００）構造を用
いるようにすれば、前記歪み検出素子の応力を特定の式
により、絶対値として検出することができる。According to a sixth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, if the (100) structure is used as the crystal structure of the semiconductor chip, The stress of the strain detecting element can be detected as an absolute value by a specific equation.
【図１】本発明の一実施形態に係る半導体チップの模式
図である。FIG. 1 is a schematic diagram of a semiconductor chip according to an embodiment of the present invention.
【図２】同上の半導体チップを基板にフリップチップ実
装及びアンダーフィル封止を行って構成された半導体装
置の断面方向から見た状態を示す模式図である。FIG. 2 is a schematic diagram showing a state of a semiconductor device configured by flip-chip mounting and underfill sealing the semiconductor chip on a substrate, as viewed from a cross-sectional direction.
【図３】本発明の他の実施形態に係る半導体チップの模
式図である。FIG. 3 is a schematic diagram of a semiconductor chip according to another embodiment of the present invention.
１ 半導体チップ ２ 電極 ３ ピエゾ抵抗素子 ４ 接続用配線 ５ 基板 ６ 測定用端子 ７ バンプ ８ アンダーフィル封止樹脂 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Electrode 3 Piezoresistive element 4 Connection wiring 5 Substrate 6 Measurement terminal 7 Bump 8 Underfill sealing resin
Claims (6)
導体装置であって、半導体チップ内の所定個所に該半導
体チップの歪みを検出するための歪み検出素子を同一方
向に複数個形成し、該歪み検出素子に電気信号を印加す
るとともに歪み検出素子からの出力を外部へ取り出すた
めの電極を形成し、前記基板には、前記電極と接続する
ための測定用端子を形成し、該測定用端子と前記電極と
を接続するようにしたことを特徴とする半導体装置。1. A semiconductor device having a semiconductor chip mounted on a substrate, wherein a plurality of strain detecting elements for detecting strain of the semiconductor chip are formed at predetermined locations in the semiconductor chip in the same direction, An electrode for applying an electric signal to the strain detecting element and extracting an output from the strain detecting element to the outside; forming a measurement terminal for connecting to the electrode on the substrate; A semiconductor device, wherein a terminal is connected to the electrode.
面に均一に分散配置させるようにしたことを特徴とする
請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said strain detecting elements are uniformly distributed over the entire surface of the semiconductor chip.
所的に配置させるようにしたことを特徴とする請求項１
記載の半導体装置。3. The semiconductor device according to claim 1, wherein said strain detecting element is locally arranged in a semiconductor chip.
13. The semiconductor device according to claim 1.
面側と裏面側の同一個所に各々対応させて配置するよう
にしたことを特徴とする請求項１乃至請求項３のいずれ
かに記載の半導体装置。4. The semiconductor device according to claim 1, wherein the strain detecting elements are arranged corresponding to the same locations on the front surface and the rear surface in the semiconductor chip, respectively. Semiconductor device.
（１１０）構造を用いるようにしたことを特徴とする請
求項１乃至請求項４のいずれかに記載の半導体装置。5. The crystal structure of the semiconductor chip,
5. The semiconductor device according to claim 1, wherein a (110) structure is used.
（１００）構造を用いるようにしたことを特徴とする請
求項１乃至請求項４のいずれかに記載の半導体装置。6. The crystal structure of the semiconductor chip,
5. The semiconductor device according to claim 1, wherein a (100) structure is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7597598A JP3873438B2 (en) | 1998-03-24 | 1998-03-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7597598A JP3873438B2 (en) | 1998-03-24 | 1998-03-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11274229A true JPH11274229A (en) | 1999-10-08 |
| JP3873438B2 JP3873438B2 (en) | 2007-01-24 |
Family
ID=13591767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7597598A Expired - Fee Related JP3873438B2 (en) | 1998-03-24 | 1998-03-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3873438B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009065052A (en) * | 2007-09-07 | 2009-03-26 | Ricoh Co Ltd | Semiconductor package group for detecting stress distribution, and method of detecting stress distribution in semiconductor package using the same |
-
1998
- 1998-03-24 JP JP7597598A patent/JP3873438B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009065052A (en) * | 2007-09-07 | 2009-03-26 | Ricoh Co Ltd | Semiconductor package group for detecting stress distribution, and method of detecting stress distribution in semiconductor package using the same |
| JP4512125B2 (en) * | 2007-09-07 | 2010-07-28 | 株式会社リコー | Semiconductor package group for detecting stress distribution and method for detecting stress distribution of semiconductor package using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3873438B2 (en) | 2007-01-24 |
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