JP3873438B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP3873438B2
JP3873438B2 JP7597598A JP7597598A JP3873438B2 JP 3873438 B2 JP3873438 B2 JP 3873438B2 JP 7597598 A JP7597598 A JP 7597598A JP 7597598 A JP7597598 A JP 7597598A JP 3873438 B2 JP3873438 B2 JP 3873438B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
strain
electrode
substrate
strain detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7597598A
Other languages
Japanese (ja)
Other versions
JPH11274229A (en
Inventor
恭史 田中
一功 葛原
智広 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP7597598A priority Critical patent/JP3873438B2/en
Publication of JPH11274229A publication Critical patent/JPH11274229A/en
Application granted granted Critical
Publication of JP3873438B2 publication Critical patent/JP3873438B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Pressure Sensors (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップを基板へ実装する際等にかかるストレスを検出することのできる半導体装置に関するものである。
【０００２】
【従来の技術】
従来、半導体チップを基板へ実装する際等にかかるストレスの分布を解析、評価する場合、故障モードの解析やシミュレーションによる解析を行う必要があった。
【０００３】
【発明が解決しようとする課題】
しかしながら、上述のような解析、評価の方法においては、モデルパターンの作成が必要になり、この作業に多大の時間を要してしまうという問題があった。
【０００４】
本発明は、上記の点に鑑みてなしたものであり、その目的とするところは、半導体チップにかかるストレスを容易に検出することのできる半導体装置を提供することにある。
【０００５】
【課題を解決するための手段】
請求項１記載の発明は、半導体チップを基板上に実装してなる半導体装置であって、半導体チップ内の所定個所に該半導体チップの歪みを検出するための歪み検出素子を同一方向に複数個形成し、該歪み検出素子に電気信号を印加するとともに歪み検出素子からの出力を外部へ取り出すための電極を形成し、前記基板には、前記電極と接続するための測定用端子を形成し、該測定用端子と前記電極とを接続するようにし、歪み検出素子を半導体チップ内の全面に均一に分散配置させるようにしたことを特徴とするものである。
【０００６】
請求項２記載の発明は、半導体チップを基板上に実装してなる半導体装置であって、半導体チップ内の所定個所に該半導体チップの歪みを検出するための歪み検出素子を同一方向に複数個形成し、該歪み検出素子に電気信号を印加するとともに歪み検出素子からの出力を外部へ取り出すための電極を形成し、前記基板には、前記電極と接続するための測定用端子を形成し、該測定用端子と前記電極とを接続するようにし、歪み検出素子を半導体チップ内の表面側と裏面側の同一個所に各々対応させて配置するようにしたことを特徴とするものである。
【０００７】
請求項３記載の発明は、請求項１又は２記載の半導体装置において、前記半導体チップの結晶構造として、（１１０）構造を用い、歪み検出素子がピエゾ抵抗素子であることを特徴とするものである。
【０００８】
請求項４記載の発明は、請求項１又は２記載の半導体装置において、前記半導体チップの結晶構造として、（１００）構造を用い、歪み検出素子がピエゾ抵抗素子であることを特徴とするものである。
【００１１】
【発明の実施の形態】
以下、本発明の実施の形態の一例を図面に基づき説明する。図１は、本発明の実施の形態の一例に係る半導体チップの模式図である。本実施形態の半導体チップ１には、所定個所、つまり、歪みを検出したい個所に歪み検出素子としての複数のピエゾ抵抗素子３が形成され、各ピエゾ抵抗素子３の両端近傍には接続用配線４を介して接続される電極２が形成されている。ピエゾ抵抗素子３は、例えば、シリコンウエハにホウ素をドーピングすることにより形成することができる。
【００１２】
ここで、複数のピエゾ抵抗素子３は、全て同一方向に配置されるとともに、半導体チップ１の全面にわたって、均一に分散配置されている。
【００１３】
本実施形態の半導体チップ１は、図２に示すように、半導体チップ１の電極２上にバンプ７を形成しておき、バンプ７の形成面を測定用端子６の形成された基板５の測定用端子６に対向させて、フリップチップ実装し、さらに、アンダーフィル封止樹脂８による樹脂封止を行い半導体装置が完成されるのである。
【００１４】
本実施形態の半導体装置では、フリップチップ実装工程やアンダーフィル封止工程等において、半導体チップ１にストレスがかかり半導体チップ１が歪めば、ピエゾ抵抗素子３の抵抗値が変化することになり、外部から測定用端子６を介して電気信号を印加することにより、ピエゾ抵抗素子３の抵抗値を測定すれば、この抵抗値の変化により半導体チップ１の歪みを検出することができるのである。
【００１５】
従って、半導体チップ１のピエゾ抵抗素子３の形成された個所にかかっているストレスが容易に検出できるようになるのである。なお、歪み検出素子として、ピエゾ抵抗素子３の替りに静電容量型素子を使用しても良い。
【００１６】
本実施形態の半導体装置によれば、ピエゾ抵抗素子３は、半導体チップ１において、全て同一方向に配置されているので、フリップチップ実装工程やアンダーフィル封止工程での半導体チップ１の特定方向の応力分布が測定できる。また、ピエゾ抵抗素子３は、半導体チップ１の全面にわたって、均一に分散配置されているので、フリップチップ実装工程やアンダーフィル封止工程での半導体チップ１全体にわたる応力分布が測定できる。従って、半導体チップ１にかかる特定方向のストレス分布を容易に検出することができる。
【００１７】
本実施形態では、ピエゾ抵抗素子３が半導体チップ１の全面にわたって、均一に分散配置されているが、局所的に配置すれば、局所的且つ詳細なストレス分布が検出できる。さらには、図３に示すように、ピエゾ抵抗素子３の方向を変えて配置することにより、斜めの方向でのストレス分布が検出できるのである。つまり、ピエゾ抵抗素子３の配置の方向により、種々の方向のストレス分布が検出できるのである。
【００１８】
また、ピエゾ抵抗素子３を、半導体チップ１内の表面側と裏面側の同一個所に各々対応させて配置すれば、半導体チップ１の厚み方向のストレス分布が検出できる。
【００１９】
半導体チップ１の結晶構造として、（１１０）構造のものを用いれば、ピエゾ抵抗素子３の縦方向の応力が以下の式により、絶対値として検出することができるのである。（横方向の応力に対する検出感度は劣っている）
ΔＲ＝（π／２）σｙ
ΔＲ：ピエゾ抵抗素子３の抵抗値の変化量
π：ピエゾ抵抗係数
σｙ：縦方向応力
半導体チップ１の結晶構造として、（１００）構造のものを用いれば、ピエゾ抵抗素子３の縦方向の応力が以下の式により、絶対値として検出することができるのである。
【００２０】
ΔＲ＝（π／２）（σｙ−σｘ）
ΔＲ：ピエゾ抵抗素子３の抵抗値の変化量
π：ピエゾ抵抗係数
σｙ：縦方向応力
σｘ：横方向応力
また、半導体チップ１の電極２と基板５の測定用端子６との接続がワイヤボンディングではなくてバンプ７により行われるので、基板５の測定用端子６の形成位置の自由度が増す。
【００２１】
なお、ピエゾ抵抗素子３を半導体チップ１に形成される回路（図示せず）のない部分に形成しておけば、ストレスを検査した後の半導体装置であっても通常の使用をすることができる。
【００２２】
【発明の効果】
請求項１記載の発明においては、半導体チップを基板上に実装してなる半導体装置であって、半導体チップ内の所定個所に該半導体チップの歪みを検出するための歪み検出素子を同一方向に複数個形成し、該歪み検出素子に電気信号を印加するとともに歪み検出素子からの出力を外部へ取り出すための電極を形成し、前記基板には、前記電極と接続するための測定用端子を形成し、該測定用端子と前記電極とを接続するようにし、歪み検出素子を半導体チップ内の全面に均一に分散配置させるようにしたので、半導体チップ全面にわたってかかる特定方向のストレスの分布が容易に検出できる。
【００２３】
本願請求項２記載の発明においては、半導体チップを基板上に実装してなる半導体装置であって、半導体チップ内の所定個所に該半導体チップの歪みを検出するための歪み検出素子を同一方向に複数個形成し、該歪み検出素子に電気信号を印加するとともに歪み検出素子からの出力を外部へ取り出すための電極を形成し、前記基板には、前記電極と接続するための測定用端子を形成し、該測定用端子と前記電極とを接続するようにし、歪み検出素子を半導体チップ内の表面側と裏面側の同一個所に各々対応させて配置するようにしたので、半導体チップの厚み方向のストレス分布が容易に検出できる。
【００２４】
本願請求項３記載の発明においては、半導体チップの結晶構造として（１１０）構造を用い、歪み検出素子がピエゾ抵抗素子であるので、前記歪み検出素子の応力を特定の式により、絶対値として検出することができる。
【００２５】
本願請求項４記載の発明においては、半導体チップの結晶構造として（１００）構造を用い、歪み検出素子がピエゾ抵抗素子であるので、前記歪み検出素子の応力を特定の式により、絶対値として検出することができる。
【図面の簡単な説明】
【図１】本発明の一実施形態に係る半導体チップの模式図である。
【図２】同上の半導体チップを基板にフリップチップ実装及びアンダーフィル封止を行って構成された半導体装置の断面方向から見た状態を示す模式図である。
【図３】本発明の他の実施形態に係る半導体チップの模式図である。
【符号の説明】
１ 半導体チップ
２ 電極
３ ピエゾ抵抗素子
４ 接続用配線
５ 基板
６ 測定用端子
７ バンプ
８ アンダーフィル封止樹脂[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device capable of detecting stress applied when a semiconductor chip is mounted on a substrate.
[0002]
[Prior art]
Conventionally, when analyzing and evaluating the distribution of stress applied when a semiconductor chip is mounted on a substrate, it has been necessary to perform failure mode analysis or simulation analysis.
[0003]
[Problems to be solved by the invention]
However, in the analysis and evaluation methods as described above, it is necessary to create a model pattern, and there is a problem that this work requires a lot of time.
[0004]
The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of easily detecting a stress applied to a semiconductor chip.
[0005]
[Means for Solving the Problems]
The invention according to claim 1 is a semiconductor device in which a semiconductor chip is mounted on a substrate, and a plurality of strain detecting elements for detecting strain of the semiconductor chip are provided in a predetermined direction in the semiconductor chip in the same direction. Forming an electrode for applying an electrical signal to the strain detection element and taking out an output from the strain detection element to the outside, and forming a measurement terminal for connecting to the electrode on the substrate; The measurement terminals and the electrodes are connected, and the strain detection elements are uniformly distributed over the entire surface of the semiconductor chip .
[0006]
According to a second aspect of the present invention, there is provided a semiconductor device having a semiconductor chip mounted on a substrate, wherein a plurality of strain detecting elements for detecting strain of the semiconductor chip are provided in the same direction at predetermined locations in the semiconductor chip. Forming an electrode for applying an electrical signal to the strain detection element and taking out an output from the strain detection element to the outside, and forming a measurement terminal for connecting to the electrode on the substrate; The measurement terminals and the electrodes are connected to each other, and the strain detection elements are arranged corresponding to the same positions on the front surface side and the back surface side in the semiconductor chip, respectively .
[0007]
According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect , a (110) structure is used as the crystal structure of the semiconductor chip, and the strain detecting element is a piezoresistive element. is there.
[0008]
According to a fourth aspect of the present invention, in the semiconductor device according to the first or second aspect , a (100) structure is used as a crystal structure of the semiconductor chip, and the strain detection element is a piezoresistive element. is there.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram of a semiconductor chip according to an example of an embodiment of the present invention. In the semiconductor chip 1 of the present embodiment, a plurality of piezoresistive elements 3 as strain detecting elements are formed at predetermined locations, that is, where strain is desired to be detected, and connection wirings 4 are provided near both ends of each piezoresistive device 3. The electrode 2 connected via is formed. The piezoresistive element 3 can be formed, for example, by doping a silicon wafer with boron.
[0012]
Here, the plurality of piezoresistive elements 3 are all arranged in the same direction and are uniformly distributed over the entire surface of the semiconductor chip 1.
[0013]
As shown in FIG. 2, the semiconductor chip 1 of the present embodiment has bumps 7 formed on the electrodes 2 of the semiconductor chip 1, and the surface on which the bumps 7 are formed is measured on the substrate 5 on which the measurement terminals 6 are formed. The semiconductor device is completed by flip-chip mounting facing the terminal 6 and further resin sealing with the underfill sealing resin 8.
[0014]
In the semiconductor device of the present embodiment, if the stress is applied to the semiconductor chip 1 and the semiconductor chip 1 is distorted in the flip chip mounting process or the underfill sealing process, the resistance value of the piezoresistive element 3 changes. If a resistance value of the piezoresistive element 3 is measured by applying an electrical signal from the measurement terminal 6 through the measurement terminal 6, the distortion of the semiconductor chip 1 can be detected by the change in the resistance value.
[0015]
Therefore, the stress applied to the portion where the piezoresistive element 3 of the semiconductor chip 1 is formed can be easily detected. Note that a capacitive element may be used instead of the piezoresistive element 3 as the strain detection element.
[0016]
According to the semiconductor device of the present embodiment, since the piezoresistive elements 3 are all arranged in the same direction in the semiconductor chip 1, the piezoresistive elements 3 are arranged in a specific direction of the semiconductor chip 1 in the flip chip mounting process or the underfill sealing process. Stress distribution can be measured. Further, since the piezoresistive elements 3 are uniformly distributed over the entire surface of the semiconductor chip 1, the stress distribution over the entire semiconductor chip 1 in the flip chip mounting process and the underfill sealing process can be measured. Therefore, the stress distribution in a specific direction applied to the semiconductor chip 1 can be easily detected.
[0017]
In this embodiment, the piezoresistive elements 3 are uniformly distributed over the entire surface of the semiconductor chip 1. However, if the piezoresistive elements 3 are arranged locally, a local and detailed stress distribution can be detected. Furthermore, as shown in FIG. 3, by changing the direction of the piezoresistive element 3, the stress distribution in the oblique direction can be detected. That is, the stress distribution in various directions can be detected depending on the direction of arrangement of the piezoresistive elements 3.
[0018]
Further, if the piezoresistive elements 3 are arranged corresponding to the same positions on the front surface side and the back surface side in the semiconductor chip 1, the stress distribution in the thickness direction of the semiconductor chip 1 can be detected.
[0019]
If the crystal structure of the semiconductor chip 1 is (110), the longitudinal stress of the piezoresistive element 3 can be detected as an absolute value by the following equation. (Sensitive sensitivity to lateral stress is inferior)
ΔR = (π / 2) σy
ΔR: change in resistance value of the piezoresistive element 3 π: piezoresistive coefficient σy: longitudinal stress If the crystal structure of the semiconductor chip 1 is a (100) structure, the longitudinal stress of the piezoresistive element 3 is It can be detected as an absolute value by the following equation.
[0020]
ΔR = (π / 2) (σy−σx)
ΔR: amount of change in resistance value of the piezoresistive element π: piezoresistance coefficient σy: longitudinal stress σx: lateral stress In addition, the connection between the electrode 2 of the semiconductor chip 1 and the measurement terminal 6 of the substrate 5 is wire bonding. Since it is performed by the bumps 7, the degree of freedom of the formation position of the measurement terminals 6 on the substrate 5 is increased.
[0021]
If the piezoresistive element 3 is formed in a portion without a circuit (not shown) formed on the semiconductor chip 1, it can be used normally even in a semiconductor device after the stress is inspected. .
[0022]
【The invention's effect】
According to the first aspect of the present invention, there is provided a semiconductor device in which a semiconductor chip is mounted on a substrate, and a plurality of strain detection elements for detecting strain of the semiconductor chip are provided in the same direction at predetermined locations in the semiconductor chip. Forming electrodes, forming an electrode for applying an electrical signal to the strain sensing element and taking out the output from the strain sensing element to the outside, and forming a measurement terminal on the substrate for connection to the electrode. Since the measurement terminals and the electrodes are connected and the strain detection elements are uniformly distributed over the entire surface of the semiconductor chip, the distribution of stress in a specific direction over the entire surface of the semiconductor chip can be easily detected. it can.
[0023]
In the invention according to claim 2 of the present application, there is provided a semiconductor device in which a semiconductor chip is mounted on a substrate, and a strain detecting element for detecting strain of the semiconductor chip is provided in the same direction at a predetermined location in the semiconductor chip. A plurality of electrodes are formed, an electric signal is applied to the strain detection element, an electrode for taking out the output from the strain detection element is formed outside, and a measurement terminal for connecting to the electrode is formed on the substrate. In addition, since the measurement terminals and the electrodes are connected, and the strain detection elements are arranged corresponding to the same positions on the front surface side and the back surface side in the semiconductor chip, The stress distribution can be easily detected.
[0024]
In the invention according to claim 3, since the (110) structure is used as the crystal structure of the semiconductor chip and the strain detecting element is a piezoresistive element, the stress of the strain detecting element is detected as an absolute value by a specific formula. can do.
[0025]
In the invention according to claim 4, since the (100) structure is used as the crystal structure of the semiconductor chip and the strain detecting element is a piezoresistive element, the stress of the strain detecting element is detected as an absolute value by a specific formula. can do.
[Brief description of the drawings]
FIG. 1 is a schematic view of a semiconductor chip according to an embodiment of the present invention.
FIG. 2 is a schematic view showing a state in which a semiconductor device formed by flip-chip mounting and underfill sealing on a substrate is viewed from the cross-sectional direction.
FIG. 3 is a schematic view of a semiconductor chip according to another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Electrode 3 Piezoresistive element 4 Connection wiring 5 Board | substrate 6 Measurement terminal 7 Bump 8 Underfill sealing resin

Claims (4)

半導体チップを基板上に実装してなる半導体装置であって、半導体チップ内の所定個所に該半導体チップの歪みを検出するための歪み検出素子を同一方向に複数個形成し、該歪み検出素子に電気信号を印加するとともに歪み検出素子からの出力を外部へ取り出すための電極を形成し、前記基板には、前記電極と接続するための測定用端子を形成し、該測定用端子と前記電極とを接続するようにし、歪み検出素子を半導体チップ内の全面に均一に分散配置させるようにしたことを特徴とする半導体装置。 A semiconductor device in which a semiconductor chip is mounted on a substrate, wherein a plurality of strain detection elements for detecting strain of the semiconductor chip are formed in the same direction at predetermined locations in the semiconductor chip, and the strain detection element An electrode for applying an electric signal and taking out an output from the strain detection element to the outside is formed, and a measurement terminal for connection to the electrode is formed on the substrate, the measurement terminal and the electrode And a strain detection element is uniformly distributed over the entire surface of the semiconductor chip. 半導体チップを基板上に実装してなる半導体装置であって、半導体チップ内の所定個所に該半導体チップの歪みを検出するための歪み検出素子を同一方向に複数個形成し、該歪み検出素子に電気信号を印加するとともに歪み検出素子からの出力を外部へ取り出すための電極を形成し、前記基板には、前記電極と接続するための測定用端子を形成し、該測定用端子と前記電極とを接続するようにし、歪み検出素子を半導体チップ内の表面側と裏面側の同一個所に各々対応させて配置するようにしたことを特徴とする半導体装置。  A semiconductor device having a semiconductor chip mounted on a substrate, wherein a plurality of strain detecting elements for detecting strain of the semiconductor chip are formed in the same direction at predetermined locations in the semiconductor chip. An electrode for applying an electric signal and taking out an output from the strain detection element to the outside is formed, and a measurement terminal for connection to the electrode is formed on the substrate, the measurement terminal and the electrode And a strain detecting element is arranged corresponding to the same position on the front surface side and the back surface side in the semiconductor chip. 前記半導体チップの結晶構造として（１１０）構造を用い、歪み検出素子がピエゾ抵抗素子であることを特徴とする請求項１又は２記載の半導体装置。  3. The semiconductor device according to claim 1, wherein a (110) structure is used as a crystal structure of the semiconductor chip, and the strain detection element is a piezoresistive element. 前記半導体チップの結晶構造として（１００）構造を用い、歪み検出素子がピエゾ抵抗素子であることを特徴とする請求項１又は２記載の半導体装置。  3. The semiconductor device according to claim 1, wherein a (100) structure is used as a crystal structure of the semiconductor chip, and the strain detection element is a piezoresistive element.
JP7597598A 1998-03-24 1998-03-24 Semiconductor device Expired - Fee Related JP3873438B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7597598A JP3873438B2 (en) 1998-03-24 1998-03-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7597598A JP3873438B2 (en) 1998-03-24 1998-03-24 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH11274229A JPH11274229A (en) 1999-10-08
JP3873438B2 true JP3873438B2 (en) 2007-01-24

Family

ID=13591767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7597598A Expired - Fee Related JP3873438B2 (en) 1998-03-24 1998-03-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3873438B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4512125B2 (en) * 2007-09-07 2010-07-28 株式会社リコー Semiconductor package group for detecting stress distribution and method for detecting stress distribution of semiconductor package using the same

Also Published As

Publication number Publication date
JPH11274229A (en) 1999-10-08

Similar Documents

Publication Publication Date Title
JP4617943B2 (en) Mechanical quantity measuring device
US8502224B2 (en) Measuring apparatus that includes a chip having a through silicon via, a heater, and a stress sensor
CN208847381U (en) Micro-electro-mechanical transducer
JP2011522251A (en) Configuration of current detection circuit and integrated current sensor
CN110160681B (en) Load sensing device, package and system
US7262617B2 (en) Method for testing integrated circuit, and wafer
CN114252679A (en) Current sensor device
JP3281217B2 (en) Semiconductor type acceleration sensor and method for evaluating characteristics of sensor element of the sensor
JP3873438B2 (en) Semiconductor device
JP3837898B2 (en) Semiconductor device
JP3599003B2 (en) Bonding damage measurement method
JPH04279867A (en) Three-dimensional acceleration sensor
JP7474964B2 (en) Inspection method for device manufacturing equipment and device manufacturing equipment
JP3753023B2 (en) Bumped chip for measuring bonding damage
JPH11304614A (en) Semiconductor device
JP3034620B2 (en) 3D acceleration sensor
JPH0523140U (en) Acceleration sensor
JPH11163020A (en) Semiconductor device
TWI305273B (en) A test assembly for testing a ball grid array package device
JP4877465B2 (en) Semiconductor device, semiconductor device inspection method, semiconductor wafer
JP3573113B2 (en) Bonding damage measuring device and measuring method
JP2010071817A (en) Semiconductor sensor built-in package
JP2665075B2 (en) Integrated circuit check pattern and check method thereof
JP3573112B2 (en) Bonding damage measurement board
JPH11211586A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040618

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050322

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060711

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060907

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20061003

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20061016

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091102

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091102

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091102

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101102

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111102

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121102

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121102

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131102

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees