JPH11274162A - Semiconductor substrate and manufacture thereof - Google Patents

Semiconductor substrate and manufacture thereof

Info

Publication number
JPH11274162A
JPH11274162A JP9276298A JP9276298A JPH11274162A JP H11274162 A JPH11274162 A JP H11274162A JP 9276298 A JP9276298 A JP 9276298A JP 9276298 A JP9276298 A JP 9276298A JP H11274162 A JPH11274162 A JP H11274162A
Authority
JP
Japan
Prior art keywords
layer
semiconductor substrate
dislocation
layers
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9276298A
Other languages
Japanese (ja)
Inventor
Shinichi Tomita
真一 冨田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Sumitomo Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Industries Ltd filed Critical Sumitomo Metal Industries Ltd
Priority to JP9276298A priority Critical patent/JPH11274162A/en
Publication of JPH11274162A publication Critical patent/JPH11274162A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To eliminate the fear of the occurrence of particles and to retain the gettering ability up to the final process, by forming machining stress layers on both faces in a grinding process, forming dislocations from the stress layers in later heat treatment, simultaneously polishing both faces and executing a mirror surface polishing process for leaving a dislocation layer only on the back face. SOLUTION: The plane grinding of a surface and a back face is executed for removing unevenness on the slice face of a semiconductor substrate 10 and a non-uniform stress layer, and uniform stress layers 11 and 12 different in depth are formed on the surface and the back face. The substrate is cleaned with a condition that the machining stress layers remain and the stress layers are cleaned. It is heat-treated with a condition that dislocations are generated from the stress layers. Then, the dislocation layers of about 5 μm is formed on the surface side and that of about 10 μm on the back face. Then, double face polishing machine polishes in mirror surface one face for about 10 μm, and the stress layer 11 of the surface, the stress layer 13 and the stress layer 12 on the back face are removed. Thus, the semiconductor substrate 10 which has the stress layer 14 on the back face and which does not have COP (initial crystal particle) on the surface can be manufactured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、安定したゲッタ
リング能を有し、表層にgrown−in欠陥のない高
平坦度化された半導体基板とその製造方法に係り、研削
工程、熱処理、鏡面研磨工程を経ることにより、裏面に
発塵のないゲッタリングの持続性が長いゲッタリング層
を設けて、表層にgrown−in欠陥のない層を形成
し、かつ極めて平坦度の良い半導体基板を製造性よく製
造する半導体基板とその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly planarized semiconductor substrate having stable gettering ability and having no surface grown-in defects, and a method of manufacturing the same. Through the process, a gettering layer having no dust generation and a long persistence of gettering is provided on the back surface, a layer having no grown-in defects is formed on the surface layer, and a semiconductor substrate having extremely good flatness is manufactured. The present invention relates to a well-manufactured semiconductor substrate and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、ゲッタリング能を有した半導体基
板を簡単に製造する方法として、基板裏面に機械的加工
歪み、レーザーによる熱的歪みを設ける方法、基板裏面
にイオンビームを打ち込み歪みを設ける方法、あるいは
表裏面にリンを拡散させる方法、基板表面を酸化雰囲気
でHClを添加して塩酸酸化させる方法などのエクスト
リンシックゲッタリング(EG)法がある。また、半導
体基板内部の酸素析出物によるイントリシックゲッタリ
ング(IG)法等がある。
2. Description of the Related Art Conventionally, as a method for easily manufacturing a semiconductor substrate having a gettering ability, a method of providing mechanical processing distortion or laser thermal distortion on the back surface of a substrate, and a method of implanting an ion beam on the back surface of a substrate to provide distortion. There is an extrinsic gettering (EG) method such as a method of diffusing phosphorus on the front and back surfaces, and a method of adding HCl in an oxidizing atmosphere to oxidize hydrochloric acid on the substrate surface. In addition, there is an intrinsic gettering (IG) method using an oxygen precipitate inside a semiconductor substrate.

【0003】また、特開昭55−8067号には、基板
1表裏面に機械的加工歪み設けるに際し、図3aに示す
ごとく、まず、シリコン単結晶ブロックを円板状にスラ
イスして、両主面に加工歪層2,3を有するシリコンウ
ェーハを得る。この加工歪層2,3はクラック層、モザ
イク層、多結晶層などを含み、機械的変質層であっても
よく、その後グラインディングで両面を所要深さで研削
し、平滑化して両加工歪層2,3を均一厚みに加工す
る。
Japanese Patent Application Laid-Open No. 55-8067 discloses that when a mechanical strain is formed on the front and back surfaces of a substrate 1, a silicon single crystal block is first sliced into a disk shape as shown in FIG. A silicon wafer having processing strain layers 2 and 3 on its surface is obtained. The work strain layers 2 and 3 include a crack layer, a mosaic layer, a polycrystalline layer, etc., and may be a mechanically deteriorated layer. Then, both surfaces are ground to a required depth by grinding and smoothed to obtain both work strains. Process layers 2 and 3 to a uniform thickness.

【0004】次いで、図3bに示すごとく、適当な熱処
理、例えば1000℃、20分間の熱処理によって所要
深さまで転位を発生させて転位層4,5を形成する。さ
らに、図3cに示すごとく、両面をエッチングにより加
工して加工歪層2,3を除去し、転位層4,5を所要厚
みに揃える。
Next, as shown in FIG. 3B, dislocations are generated to a required depth by an appropriate heat treatment, for example, a heat treatment at 1000 ° C. for 20 minutes to form dislocation layers 4 and 5. Further, as shown in FIG. 3C, both surfaces are processed by etching to remove the processed strained layers 2 and 3, and the dislocation layers 4 and 5 are adjusted to a required thickness.

【0005】最後に、図3dに示すごとく、デバイス作
製面の表面のみを鏡面研磨して転位層4を完全に除去
し、裏面側の転位層5を残す。従って、加工歪層が残存
しないので反りが発生せず、裏面の転位層5にてデバイ
ス作製時においてゲッタリングを行わせることができ
る。
[0007] Finally, as shown in FIG. 3 D, only the surface of the device fabrication surface is mirror-polished to completely remove the dislocation layer 4, leaving the rear surface dislocation layer 5. Therefore, no warping occurs because the processed strain layer does not remain, and gettering can be performed in the dislocation layer 5 on the back surface during device fabrication.

【0006】一方、結晶欠陥をほぼ完全に含まない高品
質のエピタキシャル層をシリコンウェーハ表面上に成長
させたいわゆるエピタキシャルシリコン半導体基板のゲ
ッタリング源としては、前記の基板裏面に損傷を施すB
SDタイプ基板を得る方法のほか、エッチングまたは鏡
面研磨後、減圧CVD法等で裏面側表面に多結晶シリコ
ン膜を形成するPBSタイプのものがあり、またボロン
を高濃度にドープした基板を用いたり、さらにシリコン
半導体基板内部の酸素析出物によるIG法がある。
On the other hand, as a gettering source for a so-called epitaxial silicon semiconductor substrate in which a high-quality epitaxial layer substantially free of crystal defects is grown on the surface of a silicon wafer, B, which damages the back surface of the substrate, is used.
In addition to the method of obtaining an SD type substrate, there is a PBS type in which a polycrystalline silicon film is formed on the back side surface by etching under reduced pressure or the like after etching or mirror polishing, or a substrate doped with boron at a high concentration is used. Further, there is an IG method using an oxygen precipitate inside the silicon semiconductor substrate.

【0007】[0007]

【発明が解決しようとする課題】しかし、従来の製造方
法においては、片面に転移層を残すためにエッチング工
程と片面研磨工程を必要とし、工程が複雑になってい
る。また、裏面側表面がエッチング面であるため、裏面
側からパーティクルが発生する問題があり、さらにはデ
バイスの高集積度化に伴う半導体基板の高平坦度化に対
応し難いという問題があった。
However, in the conventional manufacturing method, an etching step and a one-side polishing step are required to leave a transition layer on one side, and the steps are complicated. Further, since the back side surface is an etched surface, there is a problem that particles are generated from the back side, and further, there is a problem that it is difficult to cope with high flatness of a semiconductor substrate accompanying high integration of devices.

【0008】また、COP(Crystal Orig
inated Particle)と呼ばれる深さが
0.1μm程度のピットが表面に存在し、デバイス歩留
りを低下させるという問題がある。これは単結晶育成時
に形成される結晶欠陥(grown−in欠陥)であ
り、この結晶欠陥は空洞で内壁に酸化膜が形成されてい
ることが、数多く報告されている。
[0008] Also, COP (Crystal Orig)
There is a problem that pits having a depth of about 0.1 μm, which are called integrated particles, are present on the surface, which lowers the device yield. This is a crystal defect (grown-in defect) formed during the growth of a single crystal, and it has been reported that the crystal defect is a cavity and an oxide film is formed on the inner wall.

【0009】また、エピタキシャルシリコン半導体基板
においても、BSDタイプ基板はパーティクル発生の心
配があり、BSDタイプもPBSタイプの基板もデバイ
ス熱処理工程を経ることにより、ゲッタリング能の減少
又は消滅する懸念があり、デバイスの最終工程までゲッ
タリング能が期待できない問題があった。また、IG法
では、デバイス作製の初期工程でゲッタリング能が期待
できない問題があった。
[0009] Also, in the epitaxial silicon semiconductor substrate, there is a concern that particles may be generated on the BSD type substrate, and that the gettering ability may be reduced or eliminated by performing the device heat treatment process on both the BSD type substrate and the PBS type substrate. However, there is a problem that gettering ability cannot be expected until the final process of the device. Further, the IG method has a problem that gettering ability cannot be expected in an initial step of device fabrication.

【0010】この発明は、上述のゲッタリング能を有し
た半導体基板の製造に関する問題に鑑み、パーティクル
発生の心配がなく、デバイスの初期から最終工程までゲ
ッタリング能の減少又は消滅がなく、表面にCOPがな
く、デバイス歩留りの向上が期待でき、また、低コスト
で製造できる平坦度の良い半導体基板とその製造方法の
提供を目的としている。
The present invention has been made in view of the above-mentioned problems relating to the manufacture of a semiconductor substrate having gettering ability, and has no fear of generation of particles, no decrease or disappearance of gettering ability from the initial stage to the final step of the device, and An object of the present invention is to provide a semiconductor substrate with good flatness that can be manufactured at low cost without COP, can be expected to improve device yield, and a method for manufacturing the same.

【0011】[0011]

【課題を解決するための手段】発明者は、パーティクル
発生の心配がなく、デバイスの初期から最終工程までゲ
ッタリング能の減少又は消滅がなく、表層にgrown
−in欠陥のない平坦度の良い半導体基板を目的に種々
検討した結果、研削工程で両面に加工歪層を形成、その
後熱処理で歪層より転位を形成し、両面同時研磨を行い
裏面のみに転位層を残す鏡面研磨工程を経ることによ
り、裏面に発塵のないゲッタリングの持続性が長いゲッ
タリング層を設けて、表層にgrown−in欠陥のな
い層を形成し、かつ極めて平坦度の良い半導体基板を、
製造性よく製造できることを知見し、この発明を完成し
た。
Means for Solving the Problems The inventor of the present invention has no concern about generation of particles, has no decrease or disappearance of gettering ability from the initial stage to the final process of the device, and has a grown surface on the surface.
As a result of various investigations for the purpose of semiconductor substrates with good flatness without in-defects, formed a strained layer on both sides in the grinding process, then formed dislocations from the strained layer by heat treatment, and simultaneously polished both sides, dislocations only on the backside Through a mirror polishing step that leaves a layer, a gettering layer with long dust-free gettering durability is provided on the back surface to form a layer without a grown-in defect on the surface layer, and has extremely good flatness. Semiconductor substrate,
The present inventors have found that they can be manufactured with good manufacturability, and have completed the present invention.

【0012】すなわち、この発明は、半導体基板の表裏
面に加工歪層を形成し、その後、加工歪層から転位を発
生させて転位層を形成し、さらに両面同時研磨を行い裏
面のみに転位層を残存させて、表裏面が鏡面で裏面に転
位層を有する基板を得ることを特徴とする半導体基板の
製造方法である。
That is, according to the present invention, a work strain layer is formed on the front and back surfaces of a semiconductor substrate, and then dislocations are generated from the work strain layer to form a dislocation layer. To obtain a substrate having a mirror surface on the front and back surfaces and having a dislocation layer on the back surface.

【0013】また、この発明は、上記構成の製造方法に
おいて、1100℃以上融点以下の温度範囲で熱処理を
行い転位層を形成すること、を特徴とする半導体基板の
製造方法である。
Further, the present invention is a method of manufacturing a semiconductor substrate, characterized in that a heat treatment is performed in a temperature range of 1100 ° C. or higher and a melting point or lower to form a dislocation layer.

【0014】さらに、この発明は、半導体基板の表裏面
に加工歪層を形成し、その後、500℃以上1000℃
以下の温度範囲で熱処理を行い加工歪層から転位を発生
させて転位層を形成し、さらに両面同時研磨を行い裏面
のみに転位層を残存させ、表面にエピタキシャルシリコ
ン層を形成することを特徴とする半導体基板の製造方法
である。
Further, according to the present invention, a processing strain layer is formed on the front and back surfaces of a semiconductor substrate, and thereafter, the temperature is 500 ° C. or more and 1000 ° C.
A heat treatment is performed in the following temperature range to generate dislocations from the strained layer to form a dislocation layer, and further, both sides are simultaneously polished to leave a dislocation layer only on the back surface, and an epitaxial silicon layer is formed on the surface. This is a method of manufacturing a semiconductor substrate.

【0015】また、この発明は、上記構成の各製造方法
において、半導体基板の表裏面に異なる深さで加工歪層
を形成すること、半導体基板の表裏面に作用させる砥粒
径を変えて異なる深さで加工歪層を形成すること、両面
同時研磨で表裏面の研磨速度比を制御し裏面のみに転位
層を残すこと、加工歪層の形成工程と鏡面研磨工程を両
面同時加工で連続的に行うこと、をそれぞれ特徴とする
半導体基板の製造方法である。
Further, according to the present invention, in each of the manufacturing methods having the above-described structures, the processing strain layers are formed at different depths on the front and back surfaces of the semiconductor substrate, and the abrasive grain diameters acting on the front and back surfaces of the semiconductor substrate are changed. Forming a strained layer at a depth, controlling the polishing rate ratio of the front and back surfaces by simultaneous polishing on both sides, leaving a dislocation layer only on the back side, and continuously forming and forming a processed strained layer and mirror-polishing process by simultaneous processing on both sides In each case.

【0016】この発明による製造方法は、両面同時研磨
を行い表裏面が鏡面で裏面に転位層を有する極めて平坦
度の良い半導体基板を得るが、さらにこの半導体基板表
面にエピタキシャルシリコン層を形成して、デバイスの
初期から最終工程まで安定したゲッタリング能を有した
エピタキシャルシリコン半導体基板を容易に製造するこ
とができる。
According to the manufacturing method of the present invention, a semiconductor substrate having an extremely flat surface having a dislocation layer on the back surface with mirror surfaces on the front and back surfaces is obtained by simultaneous polishing on both surfaces, and an epitaxial silicon layer is further formed on the surface of the semiconductor substrate. In addition, an epitaxial silicon semiconductor substrate having a stable gettering ability from the initial stage to the final process of the device can be easily manufactured.

【0017】この発明による半導体基板は、BSDタイ
プやPBSタイプなどに比べて転位層はデバイス熱処理
工程を経ても消滅せず、デバイスの最終工程までゲッタ
リング能を有しておりデバイス歩留りの向上が期待で
き、また、BSDタイプに比べ、パーティクル発生の心
配がない利点がある。
In the semiconductor substrate according to the present invention, the dislocation layer does not disappear even after the device heat treatment step, has a gettering ability until the final step of the device, and improves the device yield, as compared with the BSD type or the PBS type. There is an advantage that it can be expected and there is no worry about generation of particles as compared with the BSD type.

【0018】また、この発明による半導体基板は、IG
法に比較して、デバイス製造工程の初期よりゲッタリン
グ作用があり、デバイス歩留りの向上が期待でき、さら
に、表面にCOPがないため、デバイス歩留りの向上が
期待できる。
Further, the semiconductor substrate according to the present invention has an IG
Compared with the conventional method, gettering action is obtained from an early stage of the device manufacturing process, and an improvement in device yield can be expected. Further, since there is no COP on the surface, an improvement in device yield can be expected.

【0019】[0019]

【発明の実施の形態】この発明による製造方法は、例え
ば平面研削で表裏面にダイヤモンド砥粒径が異なる番手
を用いて表裏面に深さの異なる加工歪層を形成し、熱処
理を施し、転位を形成させ、両面研磨機でデバイス形成
面側の表面の浅い加工歪層及び転位層を除去し、裏面の
深い加工歪層のみを除去して転位層を残すことより、表
裏面が鏡面で裏面側に転位層を有する基板が得られる。
かかる工程にはエッチング工程が不要で、高精度に平面
研削した後に両面研磨を施しているため、極めて平坦度
がすぐれた半導体基板が得られる。
BEST MODE FOR CARRYING OUT THE INVENTION The manufacturing method according to the present invention comprises forming strained layers having different depths on the front and back surfaces by using, for example, surface grinding by using counts having different diamond abrasive grain sizes, performing heat treatment, By removing the shallow work strain layer and dislocation layer on the surface on the device formation side with a double-sided polishing machine and removing only the deep work strain layer on the back surface and leaving the dislocation layer, the front and back surfaces are mirror-finished and the back surface A substrate having a dislocation layer on the side is obtained.
Such a process does not require an etching process, and since both surfaces are polished after highly accurate surface grinding, a semiconductor substrate having extremely excellent flatness can be obtained.

【0020】また、平面研削で表裏面に同じ深さで加工
歪層を形成し、熱処理を施し、転位を形成させた後、両
面研磨機で研磨するが、ここで、表面と裏面の研磨量が
異なるように研磨の条件を変えることができ、この条件
としては上下の定盤の回転数を変えたり、上下の定盤に
張り付けている研磨パッドを変える等によって実現で
き、これによって、表面の歪層及び転位層と裏面の歪層
のみを除去でき、表裏面が鏡面で裏面に転位層を有する
半導体基板を製造できる。
Further, a strained layer is formed at the same depth on the front and back surfaces by surface grinding, heat treatment is performed, and dislocations are formed. Then, polishing is performed by a double-side polishing machine. Can be changed so that the polishing conditions are different.The conditions can be realized by changing the rotation speed of the upper and lower platens, changing the polishing pad attached to the upper and lower platens, etc. Only the strained layer, the dislocation layer, and the strained layer on the back surface can be removed, and a semiconductor substrate having mirror surfaces on the front and back surfaces and having a dislocation layer on the back surface can be manufactured.

【0021】以下に、この発明の半導体基板の製造方法
を図面に基づいてを詳述する。半導体基板の製造方法
は、まず、図1aに示すように、半導体基板10のスラ
イス面の凹凸及び不均一な歪層を除去するために表裏面
の平面研削を行い、半導体基板10の表裏面に異なった
深さの均一な歪層11,12を形成する。
Hereinafter, a method of manufacturing a semiconductor substrate according to the present invention will be described in detail with reference to the drawings. In the method of manufacturing a semiconductor substrate, first, as shown in FIG. 1A, surface grinding is performed on the front and back surfaces of the semiconductor substrate 10 in order to remove unevenness and uneven strain layers on the slice surface of the semiconductor substrate 10. Uniform strain layers 11 and 12 having different depths are formed.

【0022】上記の表裏面の平面研削は、ダイヤモンド
固定砥粒の大きさの異なるものを用いて行うことがで
き、例えば表面側を2000番手で行い、裏面側を50
0番で行う。これによって、表面側には5μm程度、裏
面側には10μm程度の歪層が形成される。このときの
平面研削は、表裏面同時に研削することも、片面ずつ行
うこともできる。
The above-mentioned surface grinding of the front and back surfaces can be performed using diamond fixed abrasive grains having different sizes.
Perform on No. 0. As a result, a strain layer of about 5 μm is formed on the front side and about 10 μm on the back side. At this time, the surface grinding can be performed simultaneously on the front and back surfaces or one surface at a time.

【0023】次に、図1bに示すように、SC1洗浄、
HF洗浄、SC2洗浄、NaOH洗浄、KOH洗浄、超
音波洗浄等を組み合わせて加工歪層が残存するような条
件で洗浄し、歪層を清浄化した後、歪層から転位が発生
するような条件、500℃以上、例えば900℃、30
分間で熱処理を熱処理炉で行う。これにより表面側に5
μm程度、裏面側に10μm程度の転位層が形成され
る。
Next, as shown in FIG.
HF cleaning, SC2 cleaning, NaOH cleaning, KOH cleaning, ultrasonic cleaning, etc. are combined under such conditions that the processed strained layer remains, and after the strained layer is cleaned, dislocations are generated from the strained layer. , 500 ° C. or higher, for example, 900 ° C., 30
Heat treatment in a heat treatment furnace for a minute. As a result, 5
A dislocation layer having a thickness of about 10 μm is formed on the rear surface side.

【0024】熱処理時の雰囲気は酸素、窒素、アルゴ
ン、水素など、またそれらの混同雰囲気で行う。この熱
処理によって同時にドナキラー処理も行われる。CZ法
で引き上げたシリコン単結晶には、単結晶育成時に形成
される結晶欠陥(grown−in欠陥)15、すなわ
ち前述した深さが0.1μm程度で内部が空洞で内壁に
酸化膜が形成されている結晶欠陥、他に酸素析出核16
も存在するが、ここで、1100℃以上、非酸化性雰囲
気下で熱処理を行えば、図1bに示すように、表層の空
洞の内壁酸化膜が溶解し、加工歪層、転位層より格子間
シリコンが供給され、表面に加工歪層、転位層がない場
合に比べて容易に空洞を埋めることができ、結晶欠陥の
ない表層17を得ることができる。また、以上の熱処理
を窒素雰囲気で行えば低コストで熱処理可能となる。
The heat treatment is performed in an atmosphere of oxygen, nitrogen, argon, hydrogen, or the like, or a mixed atmosphere thereof. By this heat treatment, a donakiller treatment is also performed at the same time. In the silicon single crystal pulled by the CZ method, a crystal defect (grown-in defect) 15 formed at the time of growing the single crystal, that is, an oxide film is formed on the inner wall having a depth of about 0.1 μm and a hollow inside. Crystal defects, oxygen precipitate nuclei 16
However, if heat treatment is performed in a non-oxidizing atmosphere at a temperature of 1100 ° C. or more, the inner wall oxide film of the surface cavity is dissolved as shown in FIG. The silicon can be supplied, the cavity can be easily filled as compared with the case where there is no strained layer and no dislocation layer on the surface, and the surface layer 17 without crystal defects can be obtained. If the above heat treatment is performed in a nitrogen atmosphere, heat treatment can be performed at low cost.

【0025】なお、熱処理時に歪層に残存している金属
汚染の半導体内部への拡散が考えられるが、歪層または
転移層にゲッタリングされて、後にデバイス形成面にな
る層には、金属は残存しないため問題とならない。ゲッ
タリングには冷却過程が重要であるため、適切な冷却を
施す。
It is conceivable that metal contamination remaining in the strained layer during the heat treatment may diffuse into the inside of the semiconductor. However, a metal which is gettered by the strained layer or the transition layer and becomes a device forming surface later has no metal. There is no problem because it does not remain. Since the cooling process is important for gettering, appropriate cooling is performed.

【0026】また、熱処理時に投入、取り出し等で表面
に酸化膜が形成された場合には、HF溶液で酸化膜を除
去し、その後の研磨がスムーズに行えるようにする。
If an oxide film is formed on the surface during the heat treatment, such as by being charged or removed, the oxide film is removed with an HF solution so that subsequent polishing can be performed smoothly.

【0027】次に、図1cに示すように、両面研磨機で
片面をそれぞれ10μm程度研磨することで、表面の歪
層11及び転位層13を除去でき、裏面の歪層12を除
去することができる。これによって、裏面にのみ転位層
14を有し、表面にCOPのない半導体基板1が製造で
きる。ここでは、高精度平面研削後、両面研磨機を使用
しているため、平坦度も優れている。また、必要応じて
片面毎に研磨してもよい。
Next, as shown in FIG. 1C, one side is polished by about 10 μm with a double-side polishing machine, whereby the strained layer 11 and the dislocation layer 13 on the front side can be removed, and the strained layer 12 on the back side can be removed. it can. Thereby, the semiconductor substrate 1 having the dislocation layer 14 only on the back surface and having no COP on the front surface can be manufactured. Here, since a double-side polishing machine is used after high-precision surface grinding, the flatness is also excellent. Moreover, you may grind | polish every single surface as needed.

【0028】さらに、面取り工程などを上記の両面研磨
工程前又は熱処理工程前に行うことも可能である。ま
た、上記の両面研磨工程の前後の適当な工程時に端面の
鏡面研磨工程を加えることができる。またさらに、両面
研磨工程の後、裏面側にCVD酸化膜を形成しても、よ
り平坦度を向上させるために局所プラズマエッチング加
工を実施してもよい。
Further, a chamfering step or the like can be performed before the above-mentioned double-side polishing step or before the heat treatment step. In addition, a mirror polishing process of the end face can be added at an appropriate step before and after the double-side polishing step. Further, after the double-side polishing step, even if a CVD oxide film is formed on the back surface side, local plasma etching may be performed to further improve the flatness.

【0029】図2に示す半導体基板の製造方法は、ま
ず、図2aに示すように、ボロンを高濃度に含有する半
導体基板20のスライス面の凹凸及び不均一な歪層を除
去するために表裏面の平面研削を行い、半導体基板20
の表裏面に同じ深さの均一な歪層21,22を形成す
る。この表裏面の平面研削は同じダイヤモンド固定砥粒
を用いて行い、例えば表裏面ともに500番手で行うこ
とによって、表面、裏面側には10μm程度の歪層2
1,22が形成される。この平面研削は表裏面同時にあ
るいは個別に行うことができる。
In the method of manufacturing a semiconductor substrate shown in FIG. 2, first, as shown in FIG. 2A, a table is formed to remove unevenness and uneven strain layers on a slice surface of a semiconductor substrate 20 containing high concentration of boron. The back surface is ground and the semiconductor substrate 20 is ground.
The uniform strain layers 21 and 22 having the same depth are formed on the front and back surfaces of the substrate. The surface grinding of the front and back surfaces is performed using the same diamond fixed abrasive grains. For example, by performing the front and back surfaces at 500 count, the strained layer 2 of about 10 μm is formed on the front and back surfaces.
1 and 22 are formed. This surface grinding can be performed simultaneously on the front and back surfaces or individually.

【0030】次に、図2bに示すように、SC1洗浄、
HF洗浄、SC2洗浄、NaOH洗浄、KOH洗浄、超
音波洗浄等を組み合わせて加工歪層が残存するような条
件で洗浄して歪層21,22を清浄化した後、低温で熱
処理、例えば800℃で4時間行うことにより、表裏面
に10μm程度の転位層23,24並びに内部の酸素析
出核26が成長して、図示の成長した酸素析出核27と
なる。
Next, as shown in FIG.
After cleaning the strained layers 21 and 22 by combining HF cleaning, SC2 cleaning, NaOH cleaning, KOH cleaning, ultrasonic cleaning, etc. under conditions such that the processed strained layer remains, heat treatment at a low temperature, for example, 800 ° C. 4 hours, the dislocation layers 23 and 24 of about 10 μm and the inside of the oxygen precipitate nuclei 26 grow on the front and back surfaces to become the grown oxygen precipitate nuclei 27 shown in the figure.

【0031】ここで1000℃以下の低温で短時間熱処
理を行うと、より低温側では酸素析出核サイズが殆ど変
化しないが、より高温側では図2のb1に示すように、
酸素析出核が縮小する。しかし、この熱処理では結晶欠
陥(grown−in欠陥)25を低減することができ
ない。なお、熱処理にはランプアニール装置を使用して
もよい。
When the heat treatment is performed at a low temperature of 1000 ° C. or less for a short time, the size of the oxygen precipitation nuclei hardly changes at the lower temperature side, but at the higher temperature side, as shown in FIG.
Oxygen precipitation nuclei shrink. However, this heat treatment cannot reduce the crystal defects (grown-in defects) 25. Note that a lamp annealing device may be used for the heat treatment.

【0032】また、1000℃以下の低温で長時間熱処
理を行うと、図2のb2に示すように、基板の内部に酸
素析出核が成長し、デバイス工程でのIG効果も期待で
きる。また、この熱処理でも単結晶育成時に形成される
結晶欠陥(grown−in欠陥)25を低減すること
ができない。
When heat treatment is performed at a low temperature of 1000 ° C. or less for a long time, oxygen precipitation nuclei grow inside the substrate as shown in b2 in FIG. 2, and an IG effect in the device process can be expected. Further, even with this heat treatment, crystal defects (grown-in defects) 25 formed during the growth of a single crystal cannot be reduced.

【0033】その後、両面研磨機で研磨するが、ここで
研磨の条件を変えて表面と裏面の研磨量を変える。この
条件としては、上下の定盤の回転数を変えたり、上下の
定盤に張り付けている研磨パッドを変更する等の手段に
よって実現でき、表面の歪層21及び転位層23を、裏
面の歪層22を除去でき、図2cに示すように、裏面に
転位層24を有し、表面にCOP28の存在する半導体
基板20が製造される。
Thereafter, polishing is performed by a double-side polishing machine. Here, the polishing conditions are changed to change the polishing amount of the front surface and the back surface. This condition can be realized by changing the number of rotations of the upper and lower platens, changing the polishing pad attached to the upper and lower platens, and the like. The layer 22 can be removed, and a semiconductor substrate 20 having the dislocation layer 24 on the back surface and the COP 28 on the front surface is manufactured as shown in FIG. 2c.

【0034】この後、表面のCOP28の除去のために
水素ベークを行い、次いで表面にエピタキシャル成長を
行いエピタキシャル膜29形成する。さらに、面取り工
程などを上記の両面研磨工程前、あるいは熱処理工程前
に行うことも可能である。また、上記の両面研磨工程の
前後の適当な工程時に端面の鏡面研磨工程を加えること
ができる。またさらに、両面研磨工程の後、裏面側にC
VD酸化膜を形成しても、より平坦度を向上させるため
に局所プラズマエッチング加工を実施してもよい。
Thereafter, hydrogen baking is performed to remove COP 28 on the surface, and then epitaxial growth is performed on the surface to form an epitaxial film 29. Further, the chamfering step or the like can be performed before the double-side polishing step or the heat treatment step. In addition, a mirror polishing process of the end face can be added at an appropriate step before and after the double-side polishing step. Further, after the double-side polishing step, C
Even if a VD oxide film is formed, local plasma etching may be performed to further improve the flatness.

【0035】[0035]

【発明の効果】この発明による半導体基板は、研削工程
で両面に加工歪層を形成、その後熱処理で歪層より転位
を形成し、両面同時研磨を行い裏面のみに転位層を残す
鏡面研磨工程を経ることにより、エッチング工程が不要
でゲッタリング層を設けることができ、表裏面が鏡面で
裏面側に転位層を有する構成であるため、パーティクル
発生の心配がなく、デバイスの初期から最終工程までゲ
ッタリング能の減少又は消滅がなく、表面にCOPがな
く、両面同時研磨による極めて平坦度の良い半導体基板
を製造性よく製造できる。
The semiconductor substrate according to the present invention includes a mirror polishing step in which a strained layer is formed on both sides in a grinding step, dislocations are formed from the strained layer by heat treatment, and both sides are simultaneously polished to leave a dislocation layer only on the back side. Through this process, a gettering layer can be provided without the need for an etching step, and since the front and back surfaces have a mirror surface and a dislocation layer on the back surface side, there is no need to worry about particle generation, and the gettering process can be performed from the initial stage to the final process of the device. There is no decrease or disappearance of the ring ability, no COP on the surface, and a semiconductor substrate with extremely good flatness by simultaneous double-side polishing can be manufactured with good manufacturability.

【図面の簡単な説明】[Brief description of the drawings]

【図1】a〜cはこの発明による半導体基板の作製フロ
ーを示す半導体基板の断面説明図である。
FIGS. 1A to 1C are cross-sectional views of a semiconductor substrate showing a flow of manufacturing a semiconductor substrate according to the present invention.

【図2】a〜dはこの発明による他の半導体基板の作製
フローを示す半導体基板の断面説明図である。
FIGS. 2A to 2D are cross-sectional views of a semiconductor substrate showing a flow of manufacturing another semiconductor substrate according to the present invention.

【図3】a〜dは従来の製造方法による半導体基板の作
製フローを示す半導体基板の断面説明図である。
FIGS. 3A to 3D are cross-sectional explanatory views of a semiconductor substrate showing a flow of fabricating the semiconductor substrate by a conventional manufacturing method.

【符号の説明】[Explanation of symbols]

1,10,20 半導体基板 2,3 加工歪層 4,5,13,14,23,24 転位層 11,12,21,22 歪層 15,25 結晶欠陥 16,26,27 酸素析出核 17 結晶欠陥のない表層 28 COP 29 エピタキシャル膜 1,10,20 Semiconductor substrate 2,3 Work strain layer 4,5,13,14,23,24 Dislocation layer 11,12,21,22 Strain layer 15,25 Crystal defect 16,26,27 Oxygen precipitation nucleus 17 Crystal Defect-free surface layer 28 COP 29 epitaxial film

─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成10年10月16日[Submission date] October 16, 1998

【手続補正1】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0007[Correction target item name] 0007

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0007】[0007]

【発明が解決しようとする課題】しかし、従来の製造方
法においては、片面に転層を残すためにエッチング工
程と片面研磨工程を必要とし、工程が複雑になってい
る。また、裏面側表面がエッチング面であるため、裏面
側からパーティクルが発生する問題があり、さらにはデ
バイスの高集積度化に伴う半導体基板の高平坦度化に対
応し難いという問題があった。
[SUMMARY OF THE INVENTION However, in the conventional manufacturing method requires an etching step and single side polishing step in order to leave dislocation layer on one side, the process is complicated. Further, since the back side surface is an etched surface, there is a problem that particles are generated from the back side, and further, there is a problem that it is difficult to cope with high flatness of a semiconductor substrate accompanying high integration of devices.

【手続補正2】[Procedure amendment 2]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図2[Correction target item name] Figure 2

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図2】 FIG. 2

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 裏面に転位層を有し表裏面が鏡面である
半導体基板。
1. A semiconductor substrate having a dislocation layer on the back surface and mirror surfaces on the front and back surfaces.
【請求項2】 請求項1において、表面にgrown−
in欠陥の存在しない層を有する半導体基板。
2. The method according to claim 1, wherein a surface of the ground-
A semiconductor substrate having a layer free of in-defects.
【請求項3】 半導体基板の表裏面に加工歪層を形成
し、その後、加工歪層から転位を発生させて転位層を形
成し、さらに両面同時研磨を行い裏面のみに転位層を残
存させて、表裏面が鏡面で裏面に転位層を有する基板を
得る半導体基板の製造方法。
3. A distorted layer is formed on the front and back surfaces of the semiconductor substrate, dislocations are generated from the distorted layer to form dislocation layers, and both sides are simultaneously polished to leave dislocation layers only on the back surface. And a method of manufacturing a semiconductor substrate for obtaining a substrate having a mirror surface on both sides and a dislocation layer on the back surface.
【請求項4】 請求項3において、1100℃以上融点
以下の温度範囲で熱処理を行い転位層を形成する半導体
基板の製造方法。
4. The method for manufacturing a semiconductor substrate according to claim 3, wherein a heat treatment is performed in a temperature range of 1100 ° C. or more and a melting point or less to form a dislocation layer.
【請求項5】 半導体基板の表裏面に加工歪層を形成
し、その後、500℃以上1000℃以下の温度範囲で
熱処理を行い加工歪層から転位を発生させて転位層を形
成し、さらに両面同時研磨を行い裏面のみに転位層を残
存させ、表面にエピタキシャルシリコン層を形成する半
導体基板の製造方法。
5. A distorted layer is formed on the front and back surfaces of the semiconductor substrate, and then heat treatment is performed at a temperature in the range of 500 ° C. to 1,000 ° C. to generate dislocations from the distorted layer to form dislocation layers. A method of manufacturing a semiconductor substrate in which a dislocation layer is left only on a back surface by performing simultaneous polishing and an epitaxial silicon layer is formed on a front surface.
【請求項6】 請求項3または請求項5において、半導
体基板の表裏面に異なる深さで加工歪層を形成する半導
体基板の製造方法。
6. The method of manufacturing a semiconductor substrate according to claim 3, wherein a strained layer is formed at different depths on the front and back surfaces of the semiconductor substrate.
【請求項7】 請求項6において、半導体基板の表裏面
に作用させる砥粒径を変えて異なる深さで加工歪層を形
成する半導体基板の製造方法。
7. The method of manufacturing a semiconductor substrate according to claim 6, wherein the processing strain layers are formed at different depths by changing the abrasive grain diameter acting on the front and back surfaces of the semiconductor substrate.
【請求項8】 請求項3または請求項5において、両面
同時研磨で表裏面の研磨速度比を制御し裏面のみに転位
層を残す半導体基板の製造方法。
8. The method of manufacturing a semiconductor substrate according to claim 3, wherein a polishing rate ratio of the front and back surfaces is controlled by simultaneous polishing of both surfaces to leave a dislocation layer only on the back surface.
【請求項9】 請求項3または請求項5において、加工
歪層の形成工程と鏡面研磨工程を両面同時加工で連続的
に行う半導体基板の製造方法。
9. The method of manufacturing a semiconductor substrate according to claim 3, wherein the step of forming a work strain layer and the step of mirror polishing are continuously performed by simultaneous double-sided processing.
JP9276298A 1998-03-19 1998-03-19 Semiconductor substrate and manufacture thereof Pending JPH11274162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9276298A JPH11274162A (en) 1998-03-19 1998-03-19 Semiconductor substrate and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9276298A JPH11274162A (en) 1998-03-19 1998-03-19 Semiconductor substrate and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH11274162A true JPH11274162A (en) 1999-10-08

Family

ID=14063448

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH11274162A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006068127A1 (en) * 2004-12-24 2006-06-29 Sumco Techxiv Corporation Method for producing epitaxial silicon wafer
US7993452B2 (en) 2006-03-31 2011-08-09 Sumco Techxiv Corporation Method of manufacturing epitaxial silicon wafer
US8021484B2 (en) 2006-03-30 2011-09-20 Sumco Techxiv Corporation Method of manufacturing epitaxial silicon wafer and apparatus therefor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006068127A1 (en) * 2004-12-24 2006-06-29 Sumco Techxiv Corporation Method for producing epitaxial silicon wafer
JP2006179831A (en) * 2004-12-24 2006-07-06 Komatsu Electronic Metals Co Ltd Method of manufacturing epitaxial silicon wafer
US7537658B2 (en) 2004-12-24 2009-05-26 Sumco Techxiv Corporation Method for producing epitaxial silicon wafer
US8021484B2 (en) 2006-03-30 2011-09-20 Sumco Techxiv Corporation Method of manufacturing epitaxial silicon wafer and apparatus therefor
US8888913B2 (en) 2006-03-30 2014-11-18 Sumco Techxiv Corporation Method of manufacturing epitaxial silicon wafer and apparatus therefor
US7993452B2 (en) 2006-03-31 2011-08-09 Sumco Techxiv Corporation Method of manufacturing epitaxial silicon wafer

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