JP2010040950A - Method of manufacturing semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor wafer, in which a wafer reduced in roughness due to a surface reforming heat treatment and having less sticking of foreign matter and less surface layer defects is obtained. <P>SOLUTION: The method of manufacturing the semiconductor wafer includes an etching step S7 of etching the wafer, a surface reforming step S12 of reforming a surface of the wafer, a first thickness measuring step S13 of measuring the thickness of the wafer after the surface reforming step S12 or between the etching step S7 and surface reforming step S12, main surface polishing steps S15 and S16 of polishing a main surface of the wafer, a second thickness measuring step S18 of measuring the thickness of the wafer after the main surface polishing steps S15 and S16, an actual polishing thickness calculating step S19 of calculating an actual polishing thickness of the wafer in the main surface polishing steps S15 and S16 by comparing the thickness obtained by the first thickness measuring step S13 with the thickness obtained by the second thickness measuring step S18, and a determination step S20 of determining whether the quality of the wafer is good on the basis of a maximum polishing thickness and a minimum polishing thickness of the wafer obtained by the main surface polishing steps S15 and S16. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor wafer.

  In a semiconductor wafer such as a silicon wafer (hereinafter, also simply referred to as “wafer”), the main surface is mirror-polished and then heat-treated in an atmosphere of high-temperature argon gas or hydrogen gas to thereby remove the surface of the wafer. Performing modification (hereinafter also referred to as “surface modification heat treatment”) is generally performed. The surface modification heat treatment generally refers to eliminating void (cavity) defects (V defects) generated by agglomeration of vacancies such as COP (Crystal Originated Particle) on the surface of the wafer. In addition, it has been proposed to polish the main surface of a wafer that has been subjected to surface modification heat treatment to remove roughness generated by the surface modification heat treatment and adhered foreign matter (for example, Patent Document 1 below). reference). The main surface polishing step referred to here is hereinafter referred to as a “main surface polishing step”.

  Here, the range in which voids disappear due to the surface modification heat treatment in the wafer (the range in the thickness direction of the wafer) is limited, and the maximum allowable polishing thickness in the main surface polishing process (hereinafter referred to as “maximum polishing thickness”) Say) has an upper limit. On the other hand, for flattening the main surface, there is a lower limit to the minimum polishing thickness (hereinafter also referred to as “minimum polishing thickness”) required in the main surface polishing step.

JP 2006-4983 A

  In various processes (grinding, etching, polishing) performed on the wafer, a target thickness of the wafer after the various processes and tolerances for the target thickness are set. However, when polishing is performed subsequent to the surface modification heat treatment, the actual polishing thickness of the main surface of the wafer subjected to the surface modification heat treatment (hereinafter referred to as “actual polishing thickness”) is calculated by integrating the tolerances in various processes. Is difficult to be between the maximum polishing thickness and the minimum polishing thickness. If the actual polishing thickness is larger than the maximum polishing thickness, the surface layer from which void defects have been eliminated by the surface modification heat treatment is removed, and a problem arises in that a semiconductor wafer having a low withstand pressure performance of an oxide film is produced. Further, if the polishing amount after the surface modification heat treatment is thinner than the minimum polishing thickness, there arises a problem that a semiconductor wafer having a large roughness caused by the surface modification heat treatment and from which attached foreign matters are not removed is produced. .

  Therefore, according to the present invention, the roughness caused by the surface modification heat treatment can be reduced by setting the actual polishing thickness with respect to the main surface in the wafer subjected to the surface modification heat treatment to an appropriate range, and the adhesion of foreign matters is reduced. And it aims at providing the manufacturing method of the semiconductor wafer from which a semiconductor wafer with few surface layer defects is obtained.

  (1) A semiconductor wafer manufacturing method of the present invention includes an ingot growth step of pulling up a semiconductor single crystal to grow a semiconductor ingot, and slicing the semiconductor ingot obtained by the ingot growth step to obtain a semiconductor wafer. An etching process for etching the semiconductor wafer obtained by the slicing process, and a surface modification process for modifying the surface of the semiconductor wafer by performing a heat treatment on the semiconductor wafer that has undergone the etching process; A first thickness measurement step for measuring the thickness of the semiconductor wafer after the surface modification step or between the etching step and the surface modification step, and at least in the semiconductor wafer that has undergone the first thickness measurement step Main surface polishing step for polishing the main surface, and the main surface polishing step Comparing the thickness of the semiconductor wafer measured by the second thickness measurement step with the thickness of the semiconductor wafer measured by the second thickness measurement step and the second thickness measurement step of measuring the thickness of the semiconductor wafer that has passed An actual polishing thickness calculating step for calculating an actual polishing thickness that is an actual polishing thickness of the semiconductor wafer in the main surface polishing step, and a maximum polishing thickness that is a maximum allowable polishing thickness in the main surface polishing step, and The minimum polishing thickness that is the minimum required polishing thickness in the main surface polishing step is calculated, and the quality of the semiconductor wafer that has undergone the actual polishing thickness calculation step based on the calculated maximum polishing thickness and the minimum polishing thickness And a determination step of determining whether the quality is good or bad.

  (2) In the determination step, the semiconductor wafer that has undergone the actual polishing thickness calculation step is determined as non-defective when the actual polishing thickness is between the maximum polishing thickness and the minimum polishing thickness, and the actual polishing It is preferable to determine a non-recyclable defective product when the thickness is larger than the maximum polished thickness, and to determine a recyclable defective product when the actual polished thickness is smaller than the minimum polished thickness.

  (3) The main surface polishing step, the second thickness measuring step, and the actual polishing thickness until the semiconductor wafer determined to be the recyclable defective product by the determination step is determined to be a non-defective product by the determination step. It is preferable to perform the calculation step and the determination step.

  (4) In the determination step, the maximum polishing thickness is calculated based on the growth conditions in the ingot growth step and / or the heat treatment conditions in the surface modification step, and the minimum polishing thickness is determined by the etching conditions in the etching step. It is preferable to calculate based on this.

  According to the present invention, by setting the actual polishing thickness with respect to the main surface in the wafer subjected to the surface modification heat treatment within an appropriate range, the roughness caused by the surface modification heat treatment can be reduced and the adhesion of foreign matters can be reduced. A semiconductor wafer having few surface layer defects can be obtained.

  Hereinafter, a first embodiment of a semiconductor wafer manufacturing method of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing the first half of the first embodiment of the semiconductor wafer manufacturing method of the present invention. FIG. 2 is a flowchart showing a continuation of the flow shown in FIG.

The wafer is made of, for example, a silicon wafer or a gallium arsenide wafer.
The shape of the wafer viewed in the thickness direction is generally a perfect circle, and the diameter is preferably 200 mm or more, more preferably 300 mm or more. Specifically, the diameter of the wafer is, for example, 200 mm, 300 mm, or 450 mm. The diameter of the wafer here is a target value in manufacturing, and includes a predetermined tolerance (allowable error) and the like. The shape of the wafer viewed in the thickness direction may be elliptical.
The thickness t of the wafer is, for example, 600 to 2000 μm, and preferably 700 to 1200 μm.

[First Embodiment]
Next, a method for manufacturing a semiconductor wafer according to the first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG.1 and FIG.2, the manufacturing method of the semiconductor wafer of a 1st embodiment is equipped with following process S1-S7 and process S11-S21. In particular, the semiconductor wafer manufacturing method of the first embodiment includes the surface modification step S12, the first thickness measurement step S13, the double-side polishing step S15 and the mirror polishing step S16 as the main surface polishing step, and the second thickness measurement. It comprises a step S18, an actual polishing thickness calculation step S19, and a determination step S20.

(S1) Ingot growth step S1
A semiconductor single crystal is pulled up by the Czochralski method (CZ method) to grow a single crystal semiconductor ingot. A semiconductor ingot can be grown by a floating zone method (FZ method).

(S2) Outline Grinding Step The semiconductor ingot grown through the ingot growth step S1 is cut at the front end and the end. Then, the peripheral surface of the unground semiconductor ingot is ground into a perfect circle. As a result, a semiconductor ingot having a perfect circular cross section is obtained. Orientation flats and notches are formed on the periphery of the semiconductor ingot as necessary.

(S3) Slicing Step The semiconductor ingot that has undergone the external grinding step S2 is sliced in a direction orthogonal to the central axis. For the slice, for example, a wire saw is used. Thereby, a semiconductor wafer is obtained.

(S4) Chamfering Step Chamfering is performed on the peripheral portion of the wafer obtained through the slicing step S3 in order to prevent chipping and chipping of the peripheral portion of the wafer. For example, the peripheral edge of the wafer is chamfered into a predetermined shape by a chamfering grindstone. As a result, a chamfered surface having a predetermined angle is formed on the peripheral edge of the wafer.

(S5) Lapping process The unevenness of the main surface of the wafer generated in the slicing process S3 or the like is flattened by lapping with respect to the wafer that has undergone the chamfering process S4. For example, a wafer is disposed between lapping platens parallel to each other, and a lapping solution that is a mixture of alumina abrasive grains, a dispersant, water, and the like is poured between the lapping platen and the wafer. Then, the wafers are rotated with each other under pressure and rubbed together to wrap both the main surface and the back surface of the wafer. Thereby, the flatness of the main surface and the back surface of the wafer and the parallelism of the wafer are increased.
In addition, it can replace with lapping process S5 and can also perform a double-headed grinding process or a surface grinding process.

(S6) Surface grinding process The wafer subjected to the lapping process S5 is subjected to surface grinding in order to further increase the flatness of the main surface of the wafer. Surface grinding can be performed, for example, by holding one surface of a wafer by vacuum suction and bringing the wafer and a cup-shaped fine diamond grindstone into contact with each other while rotating.

(S7) Etching Step The wafer that has undergone the surface grinding step S6 is dipped in an etchant and subjected to an etching process. For example, an etching solution is supplied to the main surface of the wafer while spinning the wafer, the supplied etching solution is spread over the entire main surface of the wafer by centrifugal force due to the spin, and the entire main surface of the wafer is etched. The surface roughness Ra of the main surface is controlled to a predetermined surface roughness. In this way, the work-affected layer generated by the machining process such as the chamfering step S4, the lapping step S5, the surface grinding step S6, etc. is almost completely removed.

(S11) Pre-heat treatment cleaning step The wafer subjected to the etching step S7 is cleaned. For example, the pre-heat treatment cleaning can be performed by HF cleaning in addition to RCA cleaning. Thereby, the outer surface of the wafer immediately before the heat treatment step (surface modification step) S12 can be cleaned.

(S12) Heat treatment step (surface modification step)
The wafer that has undergone the pre-heat treatment cleaning step S11 is subjected to heat treatment in an atmosphere of 900 ° C. or higher. The temperature of the atmosphere is preferably 1000 ° C. or higher, more preferably 1100 ° C. or higher. The temperature of the atmosphere is preferably 1350 ° C. or lower. The heat treatment is preferably performed for 10 minutes to 16 hours. In this way, the surface modification heat treatment is performed on the wafer. The surface modification heat treatment refers to eliminating void (cavity) defects (V defects) generated by agglomeration of vacancies such as COP (Crystal Originated Particle) on the surface of the wafer.

As the atmospheric gas in the heat treatment, for example, argon gas, hydrogen gas, nitrogen gas, or a mixed gas of argon gas and hydrogen gas is used.
Further, in order to eliminate COP by injecting silicon between the lattices, it is possible to switch the atmospheric gas to O ₂ after the surface modification step S12, perform the heat treatment, and then perform the oxide film peeling process. Good.

(S13) First thickness measurement step The thickness t of the wafer that has undergone the heat treatment step (surface modification step) S12 is measured. Thereby, the thickness t of the wafer before the double-side polishing step S15 (main surface polishing step) is confirmed.
In addition, 1st thickness measurement process S13 can also be performed between etching process S7 and heat processing process (surface modification process) S12. For example, the first thickness measurement step S13 can be performed between the etching step S7 and the pre-heat treatment cleaning step S11.

(S14) Mirror chamfering step A mirror chamfering process is performed on the wafer that has undergone the heat treatment step (surface modification step) S12.
In addition, about a main surface, both surfaces of a main surface and a back surface may be grind | polished simultaneously, or each surface of a main surface or a back surface may be grind | polished in order. Moreover, about the main surface, you may grind only the surface side which contacts the support boat of a heat processing apparatus.
The mirror chamfering can be performed, for example, using the techniques described in Japanese Patent Application Laid-Open No. 2006-156688 and Japanese Patent Application Laid-Open No. 9-183051.

(S15) Double-side polishing step (main surface polishing step)
Double-side polishing as rough polishing is performed using a double-side simultaneous polishing apparatus that simultaneously polishes the main surface and back surface of the wafer that has undergone the mirror chamfering step S14. Instead of the double-side polishing step S15, rough polishing may be performed on each side of the main surface and back surface of the wafer.

(S16) Mirror polishing process (main surface polishing process)
At least the main surface of the wafer that has undergone the double-side polishing step S15 is mirror-polished. This mirror polishing is performed using an apparatus that performs mirror polishing on only one side of the wafer. Mirror polishing may be performed using a double-sided simultaneous polishing apparatus that simultaneously polishes the main surface and the back surface.

  The double-side polishing step S15 and the mirror polishing step S16 are steps corresponding to the “main surface polishing step” in the present invention, and at least the main surface of the wafer that has undergone the first thickness measurement step S13 may be polished.

(S17) Cleaning process after heat treatment The wafer subjected to the mirror polishing process S16 is cleaned. For this cleaning, for example, RCA cleaning is used. Thereby, contamination of the wafer in the heat treatment step (surface modification step) S12 and the polishing steps S14 to S16 can be cleaned.

(S18) Second thickness measurement step The thickness t of the wafer that has undergone the post-heat treatment cleaning step S17 is measured. Thereby, the thickness t of the wafer immediately after the post-heat treatment cleaning step S17 can be confirmed.

(S19) Actual polishing thickness calculation step An actual polishing thickness t3 that is an actual polishing thickness of the wafer in the main surface polishing step (double-side polishing step S15 and mirror polishing step S16) is calculated. Specifically, the thickness t (t1) of the wafer measured in the first thickness measurement step S13 is compared with the thickness t (t2) of the wafer measured in the second thickness measurement step S18. The difference between the thickness t2 and the thickness t2 (t2−t1) is defined as an actual polishing thickness t3.

(S20) Determination Step Based on the maximum polishing thickness t4 and the minimum polishing thickness t5, the quality of the wafer that has undergone the actual polishing thickness calculation step S19 is determined. Specifically, the maximum polishing thickness t4 that is the maximum allowable polishing thickness in the main surface polishing step (double-side polishing step S15 and mirror polishing step S16) and the minimum polishing thickness that is the minimum required polishing thickness in the main surface polishing step. t5 is calculated. Based on the calculated maximum polishing thickness t4 and the minimum polishing thickness t5, the quality of the wafer that has undergone the actual polishing thickness calculation step S19 is determined.

The maximum polishing thickness t4 is calculated based on the growth conditions in the ingot growth step S1 and / or the heat treatment conditions in the heat treatment step (surface modification step) S12.
Examples of the growth conditions in the ingot growth step S1 include the pulling rate of the semiconductor single crystal, the concentration of oxygen in the semiconductor ingot, the concentration of nitrogen in the semiconductor ingot, and the size and number of void defects. All is fine.
The heat treatment conditions in the surface modification step S12 include, for example, the temperature of the atmospheric gas, the type of the atmospheric gas, and the time of the heat treatment, and some or all of them may be used.
The calculation condition of the maximum polishing thickness t4 may be only the growth condition in the ingot growth step S1, only the heat treatment condition in the surface modification step S12, or both conditions.

The minimum polishing thickness t5 is calculated based on the etching conditions in the etching step S7.
Examples of the etching conditions in the etching step S7 include the depth of processing distortion of the wafer before the etching step S7, the etching solution used in the etching step S7, and the etching thickness of the wafer by the etching step S7. But all or all.

  In the first embodiment, the wafer that has undergone the actual polishing thickness calculation step S19 is determined as non-defective when the actual polishing thickness t3 is between the maximum polishing thickness t4 and the minimum polishing thickness t5. If it is determined that the product is non-defective (Y), the wafer is subjected to a finish cleaning step S21.

  Further, when the actual polishing thickness t3 is larger than the maximum polishing thickness t4, it is determined as a non-recyclable defective product. In this case, since the wafer cannot be regenerated, it is excluded from the wafer manufacturing process.

On the other hand, when the actual polishing thickness t3 is smaller than the minimum polishing thickness t5, it is determined as a recyclable defective product. In this case, the wafer is defective at this point, but can be made good by polishing again.
If it is determined as a recyclable defective product (N), the main surface polishing step (double-side polishing step S15 and mirror polishing step S16) and cleaning after heat treatment until the wafer is determined to be non-defective in the determination step S20. Step S17, second thickness measurement step S18, actual polishing thickness calculation step S19, and determination step S20 are performed.

(S21) Finishing cleaning process After each of the processes S1 to S20, finishing cleaning is performed on the wafer determined to be a non-defective product (Y) in the determination process S20. For the finish cleaning, for example, an RCA cleaning solution is used.

According to the semiconductor wafer manufacturing method of the first embodiment, for example, the following effects are exhibited.
In the semiconductor wafer manufacturing method of the first embodiment, the main surface is compared by comparing the wafer thickness t1 measured in the first thickness measurement step S13 with the wafer thickness t2 measured in the second thickness measurement step S18. In the actual polishing thickness calculation step S19 for calculating the actual polishing thickness t3 in the polishing step (double-side polishing step S15 and mirror polishing step S16), and the maximum allowable polishing thickness t4 and the main surface polishing step that are maximally allowed in the main surface polishing step. A determination step S20 that calculates a minimum required minimum polishing thickness t5, and determines quality of the wafer that has undergone the actual polishing thickness calculation step S19 based on the calculated maximum polishing thickness t4 and the minimum polishing thickness t5. ing.

  Therefore, the actual polishing thickness t3 for the main surface is easily set to an appropriate range, that is, between the maximum polishing thickness t4 and the minimum polishing thickness t5 for the wafer subjected to the surface modification heat treatment in the surface modification step S12. can do. Therefore, it is possible to reduce the roughness generated on the surface layer of the wafer in the surface modification step S12, and to obtain a wafer with less foreign matter adhesion and less surface layer defects.

  Further, in the determination step S20, the wafer subjected to the actual polishing thickness calculation step S19 is determined to be non-defective when the actual polishing thickness t3 is between the maximum polishing thickness t4 and the minimum polishing thickness t5, and the actual polishing thickness t3 is the maximum. When it is larger than the polishing thickness t4, it is determined as a non-recyclable defective product, and when the actual polishing thickness t3 is smaller than the minimum polishing thickness t5, it is determined as a recyclable defective product. Therefore, non-recyclable defective products can be excluded from the wafer manufacturing process, while recyclable defective products can be made non-defective by polishing again.

  The main surface polishing step (double-side polishing step S15 and mirror-polishing step S16), post-heat treatment cleaning step S17, and the like until the wafer determined to be a recyclable defective product in the determination step S20 is determined to be a non-defective product in the determination step S20. 2 thickness measurement process S18, actual grinding | polishing thickness calculation process S19, and determination process S20 are performed. Therefore, the yield (yield) of the wafer can be improved to the maximum.

  Next, a second embodiment, which is another embodiment of the method for producing a semiconductor wafer of the present invention, will be described. About another embodiment, a different point from a 1st embodiment is mainly demonstrated, the same code | symbol is attached | subjected about the structure similar to a 1st embodiment, and description is abbreviate | omitted. The description about the first embodiment is applied as appropriate to points that are not specifically described regarding the other embodiments. In other embodiments, the same effects as in the first embodiment can be obtained.

[Second Embodiment]
FIG. 3 is a flowchart (corresponding to FIG. 2) showing the second half of the second embodiment of the semiconductor wafer of the present invention. As shown in FIG. 3, in the wafer manufacturing method of the second embodiment, the order of the mirror chamfering step S14 and the double-side polishing step S15 is different from that of the wafer manufacturing method of the first embodiment. Other than that, it is the same as the first embodiment.

As mentioned above, although the embodiment of the manufacturing method of the semiconductor wafer of this invention was described, this invention is not restrict | limited to the embodiment mentioned above.
For example, the first thickness measurement step 13 can be performed between the etching step S7 and the surface modification step S12.

When the main surface and the back surface of the wafer are polished one by one in the main surface polishing step, the maximum polishing thickness t4 is obtained after polishing the main surface and the main back surface in the first thickness measurement step S13 and the second thickness measurement step S18, respectively. The actual polishing thickness t3 may be calculated by measuring the minimum polishing thickness t5.
In the main surface polishing step, single-side polishing (rough polishing or mirror polishing) of only the main surface side of the wafer can be performed. Further, the surface grinding step S6 can be omitted.

  EXAMPLES Hereinafter, although an Example demonstrates this invention further in detail, this invention is not limited to these.

〔Example〕
In the ingot growth step S1, the single crystal silicon ingot is grown by pulling up the silicon single crystal by the Czochralski method. For this single crystal silicon ingot, the outer grinding step S2, the slicing step S3, the chamfering step S4, the lapping step S5, the surface grinding step S6, the etching step S7, and the pre-heat treatment cleaning step S11 are sequentially performed to obtain a diameter of 300 mm. Get a silicon wafer. This silicon wafer is obtained by slicing a portion where there are many void defects in a single crystal silicon ingot. As a heat treatment step (surface modification step) S12, the obtained silicon wafer was subjected to a heat treatment for 240 minutes in an argon gas atmosphere at 1150 ° C. using a vertical heat treatment apparatus.

  Thereafter, the first thickness measurement step S13 is performed, and the wafer thickness t1 is measured after the surface modification step S12 and after the mirror chamfering step S14 and before the double-side polishing step S15 and the mirror polishing step S16. A capacitance type thickness measuring machine was used for the measurement of the thickness t1.

  Then, mirror polishing (mirror chamfering) was performed as a mirror chamfering step S14. Since the main surface is roughened by the polishing agent used when performing this mirror polishing, a double-side polishing step S15 and a mirror polishing step S16 are performed after the mirror chamfering step S14, and then a post-heat treatment cleaning step S17 is performed.

  Thereafter, the second thickness measurement step S18 is performed, and after the mirror chamfering step S14, the wafer thickness t2 after the double-side polishing step S15 and the mirror polishing step S16 is measured. A capacitance type thickness measuring machine was used for the measurement of the thickness t2.

  Thereafter, the actual polishing thickness calculation step S19 is performed, and the difference (t2−t1) between the wafer thickness t1 measured in the first thickness measurement step S13 and the wafer thickness t2 measured in the second thickness measurement step S18. The actual polishing thickness t3 was calculated.

  Then, determination process S20 was performed. The maximum polishing thickness t4 was calculated based on the growth conditions in the ingot growth step S1 and / or the heat treatment conditions in the heat treatment step (surface modification step) S12. The conditions for calculating the maximum polishing thickness t4 in the examples are, for example, Conditions 1-1 to 1-4 shown in [Table 1] below. In addition, a graph showing the tendency of the calculation condition of the maximum polishing thickness t4 can be created from the conditions 1-1 to 1-4, and the calculation condition of the maximum polishing thickness t4 can be set from this graph.

  Further, the minimum polishing thickness t5 was calculated based on the etching conditions in the etching step S7. The calculation conditions of the minimum polishing thickness t5 in the examples are, for example, Conditions 2-1 to 2-3 shown in [Table 2] below.

  In the determination step S20, the wafer that has undergone the actual polishing thickness calculation step S19 is determined as non-defective when the actual polishing thickness t3 is between the maximum polishing thickness t4 and the minimum polishing thickness t5, and the actual polishing thickness t3 is the maximum polishing thickness. When it was larger than t4, it was determined as a non-recyclable defective product, and when the actual polishing thickness t3 was smaller than the minimum polishing thickness t5, it was determined as a recyclable defective product. Then, the main surface polishing step (double-side polishing step S15 and mirror-polishing step S16), second thickness measurement step S18, actual polishing until the wafer determined to be a recyclable defective product is determined to be non-defective by the determination step S20. Thickness calculation process S19 and determination process S20 were performed.

  Thereafter, a finishing cleaning step S21 was performed.

  In the embodiment, by performing the above-described steps, the actual polishing thickness t3 with respect to the main surface is set to an appropriate range, that is, the maximum polishing thickness t4 with respect to the wafer subjected to the surface modification heat treatment in the surface modification step S12. And the minimum polishing thickness t5 could be easily set. Therefore, it was possible to reduce the roughness generated on the surface layer of the wafer in the surface modification step S12, and to obtain a wafer with less foreign matter adhesion and less surface layer defects.

It is a flowchart which shows the first half of the 1st embodiment of the manufacturing method of the semiconductor wafer of this invention. 2 is a flowchart showing a continuation of the flow shown in FIG. 1. It is a flowchart (corresponding to FIG. 2) showing the second half of the second embodiment of the semiconductor wafer of the present invention.

Explanation of symbols

S1 Ingot growth step S3 Slicing step S7 Etching step S12 Surface modification step S13 First thickness measurement step S15 Double-side polishing step (main surface polishing step)
S16 Mirror polishing process (main surface polishing process)
S18 Second thickness measurement step S19 Actual polishing thickness calculation step S20 Determination step

Claims (4)

An ingot growth process in which a semiconductor ingot is grown by pulling up a semiconductor single crystal;
Slicing the semiconductor ingot obtained by the ingot growth step to obtain a semiconductor wafer; and
An etching step of performing an etching process on the semiconductor wafer obtained by the slicing step;
A surface modification step of modifying the surface of the semiconductor wafer by applying a heat treatment to the semiconductor wafer that has undergone the etching step;
A first thickness measurement step for measuring the thickness of the semiconductor wafer after the surface modification step or between the etching step and the surface modification step;
A main surface polishing step of polishing at least the main surface of the semiconductor wafer that has undergone the first thickness measurement step;
A second thickness measuring step for measuring the thickness of the semiconductor wafer that has undergone the main surface polishing step;
By comparing the thickness of the semiconductor wafer measured by the first thickness measurement step with the thickness of the semiconductor wafer measured by the second thickness measurement step, the actual polishing of the semiconductor wafer in the main surface polishing step An actual polishing thickness calculating step of calculating an actual polishing thickness which is a thickness;
The maximum polishing thickness that is the maximum allowable polishing thickness in the main surface polishing step and the minimum polishing thickness that is the minimum required polishing thickness in the main surface polishing step are calculated, and the calculated maximum polishing thickness and the minimum polishing are calculated. And a determination step of determining whether the quality of the semiconductor wafer that has undergone the actual polishing thickness calculation step is based on the thickness, and a method for manufacturing a semiconductor wafer.   In the determination step, the semiconductor wafer that has undergone the actual polishing thickness calculation step is determined as non-defective when the actual polishing thickness is between the maximum polishing thickness and the minimum polishing thickness, and the actual polishing thickness is 2. The semiconductor wafer according to claim 1, wherein the semiconductor wafer is determined to be a non-recyclable defective product when larger than a maximum polishing thickness, and is determined to be a recyclable defective product when the actual polishing thickness is smaller than the minimum polishing thickness. Manufacturing method.   The main surface polishing step, the second thickness measurement step, the actual polishing thickness calculation step, and the semiconductor wafer that has been determined as the recyclable defective product by the determination step until the determination is made as a non-defective product by the determination step. The semiconductor wafer manufacturing method according to claim 2, wherein the determination step is performed.   In the determination step, the maximum polishing thickness is calculated based on growth conditions in the ingot growth step and / or heat treatment conditions in the surface modification step, and the minimum polishing thickness is calculated based on etching conditions in the etching step. The method for producing a semiconductor wafer according to claim 1, wherein:

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