JPH1126942A - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JPH1126942A
JPH1126942A JP9173837A JP17383797A JPH1126942A JP H1126942 A JPH1126942 A JP H1126942A JP 9173837 A JP9173837 A JP 9173837A JP 17383797 A JP17383797 A JP 17383797A JP H1126942 A JPH1126942 A JP H1126942A
Authority
JP
Japan
Prior art keywords
low
wiring conductor
resistance
conductor
resistance wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9173837A
Other languages
Japanese (ja)
Inventor
Yasuhiro Sasaki
康博 佐々木
Shinya Terao
慎也 寺尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP9173837A priority Critical patent/JPH1126942A/en
Publication of JPH1126942A publication Critical patent/JPH1126942A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent generation of cracks in an insulating board and separation of a low-resistance wiring conductor, by providing a specified gap on the interface between a low-resistance wiring conductor having a specified thickness and an insulating layer having the low-resistance wiring conductor within the same layer. SOLUTION: On the boundary between an insulating base 3 made of a plurality of insulating layers 2 and the insulating layers 2 on the surface thereof, a low-resistance wiring conductor 6 having a gap 4 of 0.01 to 0.5 mm integrally provided thereon and having a thickness not smaller than 50 μm is provided. The low-resistance wiring conductor 6 formed on the outermost surface is connected to a wiring conductor 8 between the insulating layers from a via-hole conductor 7 connected to the low- resistance wiring conductor 6 provided on the inner insulating layer 2, and is further connected to a via-hole conductor 9. Also, this low-resistance wiring conductor 6 is connected to a via-hole conductor 10 provided on the other outermost surface, and is led out to the other surface of the insulating base 3. Thus, crack of the insulating base and separation of the low-resistance wiring conductor are not generated. Therefore, the thickness of the low-resistance wiring conductor can be increased, and higher density and lower resistance can be realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子が収容
搭載される半導体素子収納用パッケージや、半導体素子
の他にコンデンサや抵抗体等の各種電子部品が搭載され
る混成集積回路装置等で、大電流を流すことが可能な低
抵抗配線導体を有する多層配線基板に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for accommodating a semiconductor element in which a semiconductor element is accommodated and mounted, and a hybrid integrated circuit device in which various electronic components such as a capacitor and a resistor are mounted in addition to the semiconductor element. The present invention relates to a multilayer wiring board having a low-resistance wiring conductor through which a large current can flow.

【0002】[0002]

【従来の技術】従来、半導体素子収納用パッケージや混
成集積回路装置等に用いられる多層配線基板は、一般に
アルミナ質焼結体等の電気絶縁性のセラミック焼結体か
ら成る絶縁基体を用い、その上面の略中央部に設けた凹
部周辺から下面に、あるいはその内部及び表面に、タン
グステン(W)、モリブデン(Mo)、マンガン(M
n)等の高融点金属から成る複数の配線導体を配設する
と共に、各配線導体を絶縁基体内に設けた前記同様の高
融点金属から成るビアホール導体で接続した構造を成し
ている。
2. Description of the Related Art Conventionally, a multilayer wiring board used for a package for housing a semiconductor element, a hybrid integrated circuit device or the like generally uses an insulating substrate made of an electrically insulating ceramic sintered body such as an alumina sintered body. Tungsten (W), molybdenum (Mo), manganese (M)
n) and a plurality of wiring conductors made of a high melting point metal are arranged, and each wiring conductor is connected to a via hole conductor made of the same high melting point metal provided in the insulating base.

【0003】そして、前述のように構成された多層配線
基板は、例えば半導体素子収納用パッケージに適用した
場合には、その絶縁基体の凹部底面に半導体素子をガラ
スあるいは樹脂、ロウ材等の接着剤を介して接着固定す
ると共に、半導体素子の各電極が凹部周辺に位置する配
線導体にボンディングワイヤを介して電気的に接続さ
れ、金属やセラミックス等から成る蓋体を前記凹部を塞
ぐように前記接着剤と同様の封止剤を介して接合し、絶
縁基体の凹部内に半導体素子を気密に収容することによ
り最終製品としての半導体装置としていた。
When the multilayer wiring board constructed as described above is applied to, for example, a package for accommodating a semiconductor element, the semiconductor element is attached to the bottom surface of the concave portion of the insulating base by an adhesive such as glass, resin, brazing material or the like. Each electrode of the semiconductor element is electrically connected to a wiring conductor located around the concave portion via a bonding wire, and the lid is made of metal, ceramics, or the like, so that the lid is closed so as to cover the concave portion. A semiconductor device as a final product has been obtained by bonding via a sealing agent similar to the agent and hermetically housing the semiconductor element in a concave portion of the insulating base.

【0004】かかる半導体装置は、その絶縁基体に設け
た配線導体の一部に鉄−ニッケル(Fe−Ni)合金等
から成る外部リード端子が銀ロウ等のロウ材を介して取
着されており、該外部リード端子を外部電気回路に接続
することによって、半導体素子の各電極は配線導体、ボ
ンディングワイヤ及び外部リード端子を介して外部電気
回路に電気的に接続されている。
In such a semiconductor device, an external lead terminal made of an iron-nickel (Fe-Ni) alloy or the like is attached to a part of a wiring conductor provided on the insulating base via a brazing material such as silver brazing. By connecting the external lead terminal to an external electric circuit, each electrode of the semiconductor element is electrically connected to the external electric circuit via a wiring conductor, a bonding wire and the external lead terminal.

【0005】しかしながら、前記従来の多層配線基板
は、配線導体及びビアホール導体を形成するWやMoの
電気抵抗値が4〜8×10-6Ω・cmと極めて高いた
め、配線間の電気抵抗値を小さくして、例えば25〜6
0Aもの大電流を流せることが要求されるような多層配
線基板、具体的には昨今の配線導体のより低抵抗化が望
まれている、例えば、車載環境のような厳しい環境下で
使用される各種制御機器等をはじめとする用途には適用
できなかった。
However, in the conventional multilayer wiring board, since the electrical resistance of W or Mo forming the wiring conductor and the via-hole conductor is extremely high at 4 to 8 × 10 −6 Ω · cm, the electrical resistance between the wirings is low. , For example, 25-6
It is used in a multilayer wiring board which is required to be able to flow a large current of 0 A, specifically, in a severe environment such as an on-vehicle environment, for example, where it is desired to lower the resistance of a wiring conductor in recent years. It could not be applied to applications such as various control devices.

【0006】従って、前述のような多層配線基板におけ
る配線導体の抵抗値を低減して大電流を流せるようにす
るために、多層配線基板を構成する絶縁基体に銅(C
u)の厚膜や無電解メッキにより配線導体を形成するこ
とが行われていた。
Accordingly, in order to reduce the resistance value of the wiring conductor in the above-described multilayer wiring board and allow a large current to flow, the insulating base constituting the multilayer wiring board is made of copper (C).
The wiring conductor is formed by a thick film u) or electroless plating.

【0007】しかし、かかる配線導体では、配線の高密
度化のために配線パターンの線幅が多層配線基板の面積
により制限され、一定以上に幅広く形成することができ
ず、しかも、前記配線導体の形成方法では後の工程に悪
影響を及ぼさず短時間に低コストで充分な厚さの配線導
体を得ることが困難であり、前記低抵抗化を満足するも
のではなかった。
However, in such a wiring conductor, the line width of the wiring pattern is limited by the area of the multilayer wiring board in order to increase the wiring density, and cannot be formed wider than a certain width. In the formation method, it is difficult to obtain a wiring conductor having a sufficient thickness at a low cost in a short time without adversely affecting the subsequent steps, and the above-mentioned low resistance has not been satisfied.

【0008】そこで、配線導体の抵抗値を低減して大電
流を流せるようにするために、多層配線基板を構成する
絶縁基体に配線用空間部や溝を形成し、該配線用空間部
や溝に電気抵抗値の低い銅(Cu)や銀(Ag)等の低
融点金属から成る配線導体材料を厚く充填して低抵抗配
線導体としたものが提案されている(特開平5−216
35号公報、特開昭63―194号公報参照)。
Therefore, in order to reduce the resistance value of the wiring conductor and allow a large current to flow, a wiring space or groove is formed in an insulating base constituting the multilayer wiring board, and the wiring space or groove is formed. A low-resistance wiring conductor is proposed by thickly filling a wiring conductor material made of a low melting point metal such as copper (Cu) or silver (Ag) having a low electric resistance value (Japanese Patent Laid-Open No. 5-216).
No. 35, JP-A-63-194).

【0009】[0009]

【発明が解決しようとする課題】しかしながら、前記低
抵抗配線導体を、例えば50μm以上に厚く形成する
と、該低抵抗配線導体と絶縁基体との熱膨張差に起因す
る熱応力が多層配線基板内に残留し、特に、低抵抗配線
導体端部近傍のセラミックスに応力が集中して大きな応
力となり、その結果、前記絶縁基体にクラックを発生さ
せたり、該クラックが進展して他の配線導体を断線した
り、前記絶縁基体の配線用空間部や溝に充填して形成し
た低抵抗配線導体が、該配線用空間部や溝から剥離して
低抵抗配線導体に接続された他の配線導体と断線する恐
れがある等の課題があった。
However, if the low-resistance wiring conductor is formed to be thicker than, for example, 50 μm, the thermal stress caused by the difference in thermal expansion between the low-resistance wiring conductor and the insulating base is generated in the multilayer wiring board. Residual, in particular, stress concentrates on the ceramics near the end of the low-resistance wiring conductor and becomes a large stress, and as a result, cracks are generated in the insulating base or the cracks develop and break other wiring conductors. Or the low-resistance wiring conductor formed by filling the wiring space or groove of the insulating base is separated from the wiring space or groove and disconnected from other wiring conductors connected to the low-resistance wiring conductor. There were problems such as fear.

【0010】[0010]

【発明の目的】本発明は、前記課題を解消せんとして成
されたもので、その目的は絶縁基体に50μm以上の厚
さを有する低抵抗配線導体を設けても、該低抵抗配線導
体との熱膨張差による絶縁基体のクラックや、該クラッ
クの進展による他の配線導体の断線等が発生せず、更
に、低抵抗配線導体が絶縁基体の配線用空間部や溝から
剥離せず、従って低抵抗配線導体に接続された他の配線
導体を断線したりすることがなく、配線導体の低抵抗化
を実現して大電流を流すことが可能な、信頼性の高い低
抵抗配線導体を有する多層配線基板を提供することにあ
る。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a low-resistance wiring conductor having a thickness of 50 μm or more on an insulating substrate. Cracks in the insulating base due to the difference in thermal expansion, breakage of other wiring conductors due to the progress of the cracks, etc. do not occur. A multilayer having a highly reliable low-resistance wiring conductor capable of realizing a low resistance of the wiring conductor and allowing a large current to flow without breaking other wiring conductors connected to the resistance wiring conductor. It is to provide a wiring board.

【0011】[0011]

【課題を解決するための手段】本発明者等は、前記目的
を達成するために鋭意検討した結果、低抵抗配線導体を
複数の絶縁層から成る絶縁基体と一体化した多層配線基
板において、厚さが50μm以上と成る低抵抗配線導体
と該低抵抗配線導体を同一層内に有する絶縁層との界面
に間隙を設けることにより、絶縁基体のクラックや低抵
抗配線導体の剥離等、前記課題が解消できることを知見
し、本発明に至った。
Means for Solving the Problems As a result of extensive studies to achieve the above object, the present inventors have found that a multilayer wiring board in which a low-resistance wiring conductor is integrated with an insulating base made up of a plurality of insulating layers has a large thickness. By providing a gap at the interface between a low-resistance wiring conductor having a thickness of 50 μm or more and an insulating layer having the low-resistance wiring conductor in the same layer, the above-described problems such as cracking of the insulating base and peeling of the low-resistance wiring conductor are solved. The inventors have found that the problem can be solved, and have reached the present invention.

【0012】即ち、本発明の多層配線基板は、複数の絶
縁層から成る絶縁基体と一体化した厚さが50μm以上
の低抵抗配線導体が、該低抵抗配線導体を同一層内に有
する絶縁層の低抵抗配線導体との境界に0.01〜0.
5mmの間隙を有することを特徴とするものである。
That is, in the multilayer wiring board of the present invention, a low-resistance wiring conductor having a thickness of 50 μm or more integrated with an insulating base composed of a plurality of insulating layers has the low-resistance wiring conductor in the same layer. 0.01 to 0. 0 at the boundary with the low-resistance wiring conductor.
It has a gap of 5 mm.

【0013】[0013]

【作用】本発明の多層配線基板によれば、絶縁基体と一
体化した厚さ50μm以上の低抵抗配線導体を同一層内
に有する絶縁層の低抵抗配線導体との境界に間隙を設け
たことから、絶縁基体と低抵抗配線導体との熱膨張率の
相違に起因する熱応力が全く発生せず、従って、前記熱
応力が関与する課題は全て解消することになり、絶縁基
体のクラックや低抵抗配線導体が絶縁基体の配線用空間
部や溝から剥離して該低抵抗配線導体に接続された他の
配線導体を断線することもなく、配線導体の低抵抗化を
実現して大電流を流すことが可能となる
According to the multilayer wiring board of the present invention, a gap is provided at the boundary between the low-resistance wiring conductor of the insulating layer and the low-resistance wiring conductor having a thickness of 50 μm or more integrated with the insulating base in the same layer. Therefore, no thermal stress is generated at all due to the difference in the coefficient of thermal expansion between the insulating base and the low-resistance wiring conductor, so that all the problems involving the thermal stress are eliminated, and cracks and low The resistive wiring conductor does not peel off from the wiring space or groove of the insulating base and break other wiring conductors connected to the low-resistance wiring conductor. Will be able to shed

【0014】[0014]

【発明の実施の形態】以下、本発明の多層配線基板を図
面に基づき詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer wiring board according to the present invention will be described in detail with reference to the drawings.

【0015】図1は、本発明の多層配線基板の一実施例
を示す断面図であり、図2は、本発明の多層配線基板を
低抵抗配線導体を含む断面で切断した斜視図である。
FIG. 1 is a sectional view showing an embodiment of the multilayer wiring board of the present invention, and FIG. 2 is a perspective view of the multilayer wiring board of the present invention cut along a section including a low-resistance wiring conductor.

【0016】図1及び図2において、1は複数の絶縁層
2から成る絶縁基体3と、絶縁基体3の表層での絶縁層
2との境界に、間隙4を設けて一体化した50μm以上
の厚さ5を有する低抵抗配線導体6を設けた多層配線基
板である。
In FIGS. 1 and 2, reference numeral 1 denotes a unit of 50 μm or more integrated with a gap 4 at a boundary between an insulating base 3 composed of a plurality of insulating layers 2 and the insulating layer 2 on the surface of the insulating base 3. This is a multilayer wiring board provided with a low-resistance wiring conductor 6 having a thickness of 5.

【0017】多層配線基板1の表層に形成された低抵抗
配線導体6は、図1に示すように内部の絶縁層2に設け
た低抵抗配線導体6と接続したビアホール導体7から絶
縁層間の配線導体8に、更に配線導体8からビアホール
導体9に接続されると共に、他方の表層に設けたビアホ
ール導体10に接続することにより絶縁基体3の他方の
面に導出されている。
As shown in FIG. 1, the low-resistance wiring conductor 6 formed on the surface layer of the multilayer wiring board 1 is connected to the via-hole conductor 7 connected to the low-resistance wiring conductor 6 provided on the inner insulating layer 2 and is connected to the wiring between the insulating layers. The conductor 8 is further connected to the via-hole conductor 9 from the wiring conductor 8 and connected to the via-hole conductor 10 provided on the other surface layer, so that the conductor 8 is led out to the other surface of the insulating base 3.

【0018】また、図3は本発明の多層配線基板の他の
実施例を示す断面図であり、多層配線基板1は一方の表
層に絶縁層2との境界に間隙4を設けて低抵抗配線導体
6を複数配設し、低抵抗配線導体6から他方の表層にサ
ーマルビアを兼ねたビアホール導体7が導出されて表面
に形成された配線導体11に接続されている。
FIG. 3 is a cross-sectional view showing another embodiment of the multilayer wiring board of the present invention. The multilayer wiring board 1 is provided with a gap 4 at one boundary between the insulating layer 2 and a low-resistance wiring board. A plurality of conductors 6 are provided, and a via-hole conductor 7 also serving as a thermal via is led out from the low-resistance wiring conductor 6 to the other surface layer and connected to a wiring conductor 11 formed on the surface.

【0019】本発明の多層配線基板における低抵抗配線
導体と絶縁層との境界に設けた間隙は、低抵抗配線導体
の対象となる側面に直角方向の該低抵抗配線導体の長さ
Lと、低抵抗配線導体の熱膨張係数α1 と絶縁基体のの
熱膨張係数α2 との熱膨張係数の差Δα、及び絶縁基体
の製造工程から稼働時の全熱履歴中の最高温度と最低温
度の差ΔTとの相関から、L・Δα・ΔT/2(1−Δ
T・α2 )が必要な間隙として理論上、算出される。
The gap provided at the boundary between the low-resistance wiring conductor and the insulating layer in the multilayer wiring board of the present invention has a length L of the low-resistance wiring conductor perpendicular to the side surface of the low-resistance wiring conductor, difference Δα in thermal expansion coefficient between the thermal expansion coefficient alpha 2 of the thermal expansion coefficient alpha 1 and the insulating substrate of the low-resistance wiring conductors, and during operation from the manufacturing process of the insulating substrate between the maximum temperature and the minimum temperature in the total heat history From the correlation with the difference ΔT, L · Δα · ΔT / 2 (1-Δ
T · α 2 ) is theoretically calculated as the required gap.

【0020】しかしながら、前記間隙が0.01mm未
満では前記熱応力の発生を完全に阻止することができな
い場合を生じ、しかも、例えば低抵抗配線導体を設ける
のに、前記絶縁基体の配線用空間部や溝に導電材料の粉
末を充填後、加熱して形成した場合、前記導電材料の粉
末を粒度配合することにより該導電材料の線収縮率を
0.1%程度まで制御することが可能ではあるが、焼成
収縮にバラツキがあるために前記間隙を0.01mm未
満に制御することが困難である。
However, if the gap is less than 0.01 mm, it may not be possible to completely prevent the generation of the thermal stress. In addition, for example, in order to provide a low-resistance wiring conductor, the wiring space of the insulating base is required. When the conductive groove is formed by heating after filling the conductive material powder into the grooves or grooves, the linear shrinkage of the conductive material can be controlled to about 0.1% by blending the particle size of the conductive material powder. However, since the firing shrinkage varies, it is difficult to control the gap to less than 0.01 mm.

【0021】また、前記間隙が0.5mmを越えると多
層配線基板の配線の高密度化ができなくなり、更に配線
上にスクリーン印刷法によりオーバーコート層や半田塗
布等を行う際に、該オーバーコート剤や半田が前記間隙
に侵入して所定の印刷パターンが形成できなかったり、
塗布量がばらつく他、メッキ法により間隙を保持したま
ま被覆できない等の問題が発生することから、前記間隙
は0.01〜0.5mmの範囲に限定される。
Further, if the gap exceeds 0.5 mm, it is impossible to increase the density of the wiring of the multilayer wiring board. Further, when applying an overcoat layer or solder coating on the wiring by a screen printing method, the overcoating is not possible. Agent or solder cannot enter the gap to form a predetermined print pattern,
The gap is limited to the range of 0.01 to 0.5 mm because the coating amount varies and other problems such as the coating cannot be performed while maintaining the gap by the plating method.

【0022】また、本発明における低抵抗配線導体の厚
さは、低抵抗配線導体の低抵抗化をはかり、かつ前記課
題を解消するためにはその厚さは50μm以上となる。
In the present invention, the thickness of the low-resistance wiring conductor is set to 50 μm or more in order to reduce the resistance of the low-resistance wiring conductor and to solve the above-mentioned problem.

【0023】尚、本発明の多層配線基板において、低抵
抗配線導体を構成する導電材料は、低抵抗で大電流を流
すことができるものであればいずれでも良く、例えば銅
(Cu)や銀(Ag)、アルミニウム(Al)等が挙げ
られ、特に熱伝導性に優れ加工が容易で安価である等の
点からは銅(Cu)が最適である。
In the multilayer wiring board of the present invention, the conductive material constituting the low-resistance wiring conductor may be any conductive material having low resistance and capable of flowing a large current, such as copper (Cu) or silver ( Ag), aluminum (Al), etc., and particularly, copper (Cu) is most suitable in terms of excellent thermal conductivity, easy processing and low cost.

【0024】また、ビアホール導体はタングステン
(W)やモリブデン(Mo)、レニウム(Re)、コバ
ルト(Co)等の高融点金属を主成分とするものが挙げ
られ、特に絶縁基体との熱膨張率の整合性及びコストの
点からはMoが好適である。
The via-hole conductor may be a conductor mainly composed of a high melting point metal such as tungsten (W), molybdenum (Mo), rhenium (Re), or cobalt (Co). Mo is preferred from the viewpoints of consistency and cost.

【0025】一方、配線導体については、セラミックス
から成る絶縁基体と配線導体を同時焼成で形成する場
合、前記スルーホール導体と同様の高融点金属が使用で
き、更に熱伝導性や低抵抗配線が必要とされる場合、ポ
ストファイヤー法やメッキ法により銅(Cu)や銀(A
g)、ニッケル(Ni)、アルミニウム(Al)等で形
成でき、前記同時焼成の場合には焼成温度と融点の関係
からWが、ポストファイヤー法やメッキ法で形成する場
合には、電気特性上、Cuが好適となる。
On the other hand, as for the wiring conductor, when the insulating base made of ceramics and the wiring conductor are formed by simultaneous firing, the same high melting point metal as the through-hole conductor can be used, and furthermore, heat conductivity and low resistance wiring are required. In the case of copper (Cu) or silver (A) by a post-fire method or a plating method,
g), nickel (Ni), aluminum (Al), and the like. In the case of the simultaneous firing, W is determined from the relationship between the firing temperature and the melting point. , Cu are preferred.

【0026】また、前記ビアホール導体は、表面実装さ
れたパワーMOSFET等からの発熱を熱伝導により表
層に形成された低抵抗配線導体と接続することで、該低
抵抗配線導体とヒートシンクの効果を奏するものであ
る。
Also, the via-hole conductor has the effect of the low-resistance wiring conductor and the heat sink by connecting the heat generated from the surface-mounted power MOSFET and the like to the low-resistance wiring conductor formed on the surface layer by heat conduction. Things.

【0027】また、前記絶縁基体は一般に多層配線基板
に適用されるアルミナ(Al2 3)や窒化アルミニウ
ム(AlN)、窒化珪素(Si3 4 )等を主成分とす
るセラミック焼結体であればいずれにも適用できるが、
とりわけアルミナ質焼結体から成るものが望ましく、例
えばアルミナ(Al2 3 )、シリカ(SiO2 )、マ
グネシア(MgO)、カルシア(CaO)等の原料粉末
に周知の有機性バインダーと有機溶剤、可塑剤、分散剤
等を添加混合して調製した泥漿を、周知のドクターブレ
ード法やカレンダーロール法等のシート成形法により成
形したセラミックグリーンシートに所定の打ち抜き加工
を施すと共にこれを複数枚積層し、約1600℃の温度
で焼成することにより得られる。
The insulating base is a ceramic sintered body mainly composed of alumina (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ) or the like generally applied to a multilayer wiring board. If applicable, any can be applied,
In particular, those made of an alumina-based sintered body are desirable. For example, an organic binder and an organic solvent, which are well known in raw material powders such as alumina (Al 2 O 3 ), silica (SiO 2 ), magnesia (MgO), and calcia (CaO), The slurry prepared by adding and mixing a plasticizer, a dispersant, and the like is subjected to a predetermined punching process on ceramic green sheets formed by a sheet forming method such as a well-known doctor blade method or a calendar roll method, and a plurality of the green sheets are laminated. , At about 1600 ° C.

【0028】更に、本発明の多層配線基板に大電流を必
要とするパワーMOSFET等を表面実装する際、パワ
ーMOSFET用配線にも低抵抗の配線導体を形成して
おくと共に、前述のようにパワーMOSFETが表面実
装される部分にサーマルビアを兼用したビアホール導体
を多数設け、低抵抗配線導体のヒートシンク作用と併用
して熱放散性を向上させることが望ましい。
Further, when a power MOSFET or the like requiring a large current is surface-mounted on the multilayer wiring board of the present invention, a low-resistance wiring conductor is also formed on the power MOSFET wiring, and the power It is desirable to provide a large number of via-hole conductors that also serve as thermal vias in the portion where the MOSFET is mounted on the surface, and to improve the heat dissipation property in combination with the heat sink function of the low-resistance wiring conductor.

【0029】[0029]

【実施例】次に、以下のようにして本発明の多層配線基
板を評価した。先ず、Al2 3 、SiO2 、MgO、
CaO等の原料粉末にアクリル系の有機性バインダーと
可塑剤、溶剤を添加混合して泥漿を調製し、該泥漿をド
クターブレード法により厚さ約300μmのシート状に
成形した。
Next, the multilayer wiring board of the present invention was evaluated as follows. First, Al 2 O 3 , SiO 2 , MgO,
A slurry was prepared by adding and mixing an acrylic organic binder, a plasticizer, and a solvent to a raw material powder such as CaO, and the slurry was formed into a sheet having a thickness of about 300 μm by a doctor blade method.

【0030】次いで、前記セラミックグリーンシートの
所定位置に打ち抜き加工を施して低抵抗配線導体用空間
部とスルーホールをそれぞれ形成した後、Wを主成分と
する印刷用ペーストを用いて所定の配線パターンを印刷
形成すると共に、スルーホールにも所定のペーストを充
填した。
Next, a predetermined portion of the ceramic green sheet is punched to form a low-resistance wiring conductor space and a through hole, and then a predetermined wiring pattern is formed using a printing paste containing W as a main component. And a predetermined paste was filled into the through holes.

【0031】その後、前記低抵抗配線導体用空間部を有
するセラミックグリーンシートを表層とし、それらを所
定の厚さとなるように複数枚積層した後、配線パターン
を形成し、スルーホールに所定のペーストを充填したセ
ラミックグリーンシートを複数枚積層後、約1600℃
の温度で焼成して縦50mm、横5mm、深さがそれぞ
れ0.1、0.5、1.0mmの低抵抗配線導体用空間
を有する絶縁基体を作製した。
Thereafter, a plurality of ceramic green sheets each having a space portion for the low-resistance wiring conductor are laminated to a predetermined thickness, a wiring pattern is formed, and a predetermined paste is applied to the through holes. After laminating a plurality of filled ceramic green sheets, about 1600 ° C
To produce an insulating substrate having a low-resistance wiring conductor space having a length of 50 mm, a width of 5 mm, and a depth of 0.1, 0.5, and 1.0 mm, respectively.

【0032】かくして得られた絶縁基体の低抵抗配線導
体用空間部に、低抵抗配線導体として長手方向に種々の
間隙を設定して粒度配合したCu粉末を充填して加熱融
着させたもの、及び同じく長手方向に種々の間隙を設定
して寸法を決定した銅板を接合させたものをそれぞれ作
製して評価用の多層配線基板を得た。
The low resistance wiring conductor space portion of the insulating substrate thus obtained is filled with Cu powder mixed with a particle size with various gaps set in the longitudinal direction as a low resistance wiring conductor, and heated and fused. In addition, similarly, copper foils of which dimensions were determined by setting various gaps in the longitudinal direction were bonded to each other to obtain multilayer wiring boards for evaluation.

【0033】尚、前記間隙を設けずに低抵抗配線導体を
絶縁基体の低抵抗配線導体用空間部に形成したものを比
較例とした。
A comparative example in which the low-resistance wiring conductor was formed in the space for the low-resistance wiring conductor of the insulating base without providing the gap was used as a comparative example.

【0034】かくして得られた前記評価用の多層配線基
板を用いて、−65℃と150℃の温度をそれぞれ10
分間加える履歴を1サイクルとする冷熱サイクルを30
00サイクルまで実施して液槽熱衝撃信頼性試験を行っ
た。
Using the multilayer wiring board for evaluation thus obtained, the temperatures of -65 ° C and 150 ° C
30 cycles of cooling and heating with one cycle of addition for one minute
The test was performed up to 00 cycles to perform a liquid tank thermal shock reliability test.

【0035】前記試験後、デジタルマイクロスコープを
用いて前記評価用の多層配線基板の間隙内部の接合部分
及び熱応力が最も集中する間隙の四隅を外観検査し、前
記低抵抗配線導体のクラックや剥離、あるいは絶縁層の
クラック等の欠陥の有無を調査した。
After the above test, the appearance of the joint inside the gap of the multilayer wiring board for evaluation and the four corners of the gap where the thermal stress is most concentrated using a digital microscope, and cracks or peeling of the low resistance wiring conductor. Or the presence or absence of defects such as cracks in the insulating layer.

【0036】その後、前記評価用の多層配線基板の低抵
抗配線導体の中央部に直径が0.8mmの銅線を半田で
接合し、10mm/minの速度で引っ張り試験を行
い、破断モードと接合強度を測定した。
Thereafter, a copper wire having a diameter of 0.8 mm was bonded to the center of the low-resistance wiring conductor of the multilayer wiring board for evaluation by soldering, and a tensile test was performed at a speed of 10 mm / min. The strength was measured.

【0037】一方、前記評価用の多層配線基板の配線導
体の導通評価は、60Aの電流を1分間通電して遮断す
るのを1サイクルとする通電サイクル試験を30000
サイクル実施し、通電サイクル試験前後の抵抗値を、低
抵抗配線導体と該低抵抗配線導体と接続し、絶縁基板の
他方の表面に導出した配線導体との間で測定して抵抗変
化率を算出し、該抵抗変化率が5%以下を優、6〜10
%を良、11〜20%を可、21%以上を不良と評価し
た。
On the other hand, the continuity evaluation of the wiring conductors of the multilayer wiring board for evaluation was carried out by conducting a 30,000 current cycle test in which a current of 60 A was applied for 1 minute and cut off as one cycle.
Conduct the cycle, measure the resistance value before and after the energization cycle test, measure the resistance change rate between the low-resistance wiring conductor and the wiring conductor connected to the low-resistance wiring conductor and led out to the other surface of the insulating substrate And the rate of change of resistance is 5% or less,
% Was evaluated as good, 11 to 20% as acceptable, and 21% or more as poor.

【0038】[0038]

【表1】 [Table 1]

【0039】表から明らかなように、比較例の試料番号
1、7、13、19、25、31には、いずれにも低抵
抗配線導体のクラックや剥離、あるいは絶縁層のクラッ
ク等の欠陥が認められ、導通不良を起こしており、ま
た、本発明の請求範囲外である試料番号6、12、1
8、24、30、36ではいずれも空隙に半田が侵入し
ており、クラック等の欠陥が認められた。
As is clear from the table, in each of the sample numbers 1, 7, 13, 19, 25, and 31 of the comparative examples, defects such as cracks and peeling of the low-resistance wiring conductor and cracks of the insulating layer were observed. Sample Nos. 6, 12, and 1 which were observed and had poor continuity and were outside the scope of the present invention.
In each of 8, 24, 30, and 36, the solder penetrated into the voids, and defects such as cracks were observed.

【0040】それに対して本発明では、いずれも前記結
果は認められず、接合強度も10.0kgf/mm2
上と高く、60Aもの大電流にも充分対応可能であるこ
とが確認できた。
On the other hand, in the present invention, none of the above results was observed, and it was confirmed that the bonding strength was as high as 10.0 kgf / mm 2 or more, and that it could sufficiently cope with a large current of 60 A.

【0041】尚、本発明の実施例は低抵抗配線導体を絶
縁基体の表層に形成した多層配線基板で説明したが、本
発明はこれに限定されるものではなく、本発明の要旨を
逸脱しない範囲であれば種々の変更が可能であり、例え
ば、前記低抵抗配線導体を絶縁基体内部に埋設して多層
配線基板としたものにも適用し得るものである。
Although the embodiments of the present invention have been described with reference to a multilayer wiring board in which a low-resistance wiring conductor is formed on the surface of an insulating base, the present invention is not limited to this and does not depart from the gist of the present invention. Various changes are possible within the range, and for example, the present invention can also be applied to a multilayer wiring board in which the low-resistance wiring conductor is embedded in an insulating base.

【0042】[0042]

【発明の効果】以上詳述したように、本発明の多層配線
基板によれば、絶縁基体と一体化した厚さが50μm以
上の低抵抗配線導体を同一層内に有する絶縁層と該低抵
抗配線導体との境界に0.01〜0.5mmの間隙を設
けたことから、多層配線基板を構成する絶縁基体や低抵
抗配線導体自体にもクラックが発生したり、該低抵抗配
線導体が絶縁基体から剥離したりせず、従って低抵抗配
線導体に接続された配線導体や他の配線導体にも断線等
が起こらず、しかも低抵抗配線導体を厚くすることが可
能となり、高密度化と共に低抵抗化が実現でき、大電流
に適応し得る信頼性に優れた、例えば、車載環境のよう
な厳しい環境下においても故障することなく稼働させる
ことが可能となる。
As described above in detail, according to the multilayer wiring board of the present invention, the insulating layer having a low-resistance wiring conductor having a thickness of 50 μm or more integrated with the insulating base in the same layer is provided. Since a gap of 0.01 to 0.5 mm is provided at the boundary with the wiring conductor, cracks may occur in the insulating base and the low-resistance wiring conductor constituting the multilayer wiring board, and the low-resistance wiring conductor may be insulated. It does not peel off from the substrate, so that there is no disconnection etc. in the wiring conductor connected to the low-resistance wiring conductor or other wiring conductors. Resistance can be realized, and it is possible to operate without failure even in a severe environment such as an in-vehicle environment, which has excellent reliability adaptable to a large current.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層配線基板の一実施例を示す断面図
である。
FIG. 1 is a sectional view showing one embodiment of a multilayer wiring board of the present invention.

【図2】本発明の多層配線基板を低抵抗配線導体を含む
断面で切断した斜視図である。
FIG. 2 is a perspective view of a multilayer wiring board of the present invention cut along a cross section including a low-resistance wiring conductor.

【図3】本発明の多層配線基板の他の実施例を示す断面
図である。
FIG. 3 is a sectional view showing another embodiment of the multilayer wiring board of the present invention.

【符号の説明】[Explanation of symbols]

1 多層配線基板 2 絶縁層 3 絶縁基体 4 間隙 5 厚さ 6 低抵抗配線導体 DESCRIPTION OF SYMBOLS 1 Multilayer wiring board 2 Insulating layer 3 Insulating base 4 Gap 5 Thickness 6 Low resistance wiring conductor

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】複数の絶縁層から成る絶縁基体と一体化し
た厚さ50μm以上の低抵抗配線導体を有する多層配線
基板であって、前記低抵抗配線導体と該低抵抗配線導体
を同一層内に有する絶縁層との間に0.01〜0.5m
mの間隙を設けたことを特徴とする多層配線基板。
1. A multilayer wiring board having a low-resistance wiring conductor having a thickness of 50 μm or more integrated with an insulating base composed of a plurality of insulating layers, wherein the low-resistance wiring conductor and the low-resistance wiring conductor are in the same layer. 0.01 to 0.5 m between the insulating layer
A multilayer wiring board having a gap of m.
JP9173837A 1997-06-30 1997-06-30 Multilayer wiring board Pending JPH1126942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9173837A JPH1126942A (en) 1997-06-30 1997-06-30 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9173837A JPH1126942A (en) 1997-06-30 1997-06-30 Multilayer wiring board

Publications (1)

Publication Number Publication Date
JPH1126942A true JPH1126942A (en) 1999-01-29

Family

ID=15968084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9173837A Pending JPH1126942A (en) 1997-06-30 1997-06-30 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JPH1126942A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035833A (en) * 2021-05-28 2021-06-25 浙江集迈科微电子有限公司 Multilayer wiring adapter plate and preparation method thereof
WO2024062975A1 (en) * 2022-09-20 2024-03-28 株式会社村田製作所 Ceramic substrate and method for producing ceramic substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035833A (en) * 2021-05-28 2021-06-25 浙江集迈科微电子有限公司 Multilayer wiring adapter plate and preparation method thereof
CN113035833B (en) * 2021-05-28 2021-09-28 浙江集迈科微电子有限公司 Multilayer wiring adapter plate and preparation method thereof
WO2024062975A1 (en) * 2022-09-20 2024-03-28 株式会社村田製作所 Ceramic substrate and method for producing ceramic substrate

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