JPH1126762A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a cobalt silicide film by suppressing the increase in junction leak at the p-n junction under the film by forming a Co film on the cobalt silicide layer after the cobalt silicide layer on source and drain electrodes is once grown, performing the process for forming the silicide at least once, and forming the film to the specified film thickness. SOLUTION: A thermal CVD-SiO2 film 8 is formed as an implantation through film on the entire surface of an Si substrate. After the film is removed, a CO film 10 is formed, and a TiN film 11 is formed on the film 10. Heat treatment is performed under the nitrogen atmosphere. A cobalt silicide layer 12 is selectively formed only on the electrode wherein Co and Si are in contact. After the Co film and TiN film remaining unreactive are removed, heat treatment is performed under the nitrogen atmosphere, and the cobalt silicide layer 12 is converted into CoSi2 . A side Co film 13 is formed on the entire surface of the substrate, and a TiN film 14 is formed thereon. The CoSi2 film is different from the CoSi2 film which is formed by heat treatment, wherein the entire quantity of the Co film is formed at one time whiteout separating the CoSi forming process. The cobalt silicide film can be formed without increasing the junction leakage current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure and a manufacturing method of a Si semiconductor device, and more particularly to a structure and a manufacturing method of a MOS transistor having a source and a drain whose surfaces are silicided.

[0002]

2. Description of the Related Art At present, reduction of sheet resistance of source and drain electrodes, contact resistance between electrodes and wiring, and reduction of parasitic capacitance of source and drain have become important issues in high speed operation of MOS transistors. In order to solve this problem, a structure in which the source and drain surfaces are collectively silicided in a self-aligned manner has been applied particularly to a semiconductor device requiring high-speed operation. In this structure, each electrode surface is made of TiSi ₂ , Co
The sheet resistance is reduced by being covered with low-resistance silicide such as Si ₂ , and the contact resistance with the wiring can be greatly reduced as compared with the conventional metal / semiconductor contact. Further, since the area of the source and the drain can be reduced, the parasitic capacitance can also be reduced. Furthermore, a so-called salicide (Selfalign Silicide) technique for simultaneously silicidizing the surface of the gate electrode in a self-aligning manner when the source and drain surfaces are silicided is also widely used.

[0003]

In a conventional silicidation technique on a source and a drain, a silicide is formed by reacting a metal film formed thereon with a Si substrate. Metal atoms diffused in the Si substrate reach the p / n junction formed below, or silicide grows laterally to reach the p / n junction at the LOCOS end, thereby increasing junction leakage. .
The problem is that cobalt silicide (CoS
It is particularly serious in the case where i ₂₎ was selected. If the thickness of the cobalt silicide film formed on the Si substrate is reduced, the junction leakage can be reduced, but the purpose of reducing the sheet resistance of the source and drain cannot be achieved. Further, when the thickness of the cobalt silicide film is reduced, there is a risk that the film is scraped off by over-etching during dry etching of the contact hole opening and disappears, thereby increasing the contact resistance. Therefore, in forming silicide on the source and the drain, a cobalt silicide film having a thickness of 30 nm or more is required.

Accordingly, an object of the present invention is to form a cobalt silicide film on a source and a drain without increasing junction leakage at a p / n junction thereunder. In particular, it is an object of the present invention to form a cobalt silicide film having a thickness exceeding 30 nm, which is sufficient to reduce the sheet resistance, at a p / n junction thereunder without increasing junction leakage. Another object is to reduce the specific resistance of the cobalt silicide film formed at this time.

[0005]

The above object is achieved by forming a cobalt silicide layer on source and drain electrodes to a thickness of 30 nm.
After a cobalt silicide layer having a thickness of less than m is formed once, a Co film is formed on the cobalt silicide layer and the step of silicidizing the Co film is performed at least once to form a film having a predetermined thickness of 30 nm or more. That can be achieved.

It is another object of the present invention to provide a method in which a source and drain electrode surface is formed on a diffusion layer having a width of 50 nm or more and 200 nm or less from a peripheral insulating film toward a MOS transistor and a region where a cobalt silicide layer does not exist and a diffusion inside the region. This can be achieved by a structure including a region where a cobalt silicide layer exists on the layer.

Further, after forming a cobalt silicide layer to a predetermined thickness on the source and drain electrodes, a step of removing the cobalt silicide layer from the surface by a thickness of 2 nm to 5 nm is carried out. Forming a Co film on the layer and causing it to react to obtain a CoSi ₂ film is also effective as a means for achieving the above object.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG. 1 shows a method of manufacturing a semiconductor device according to the present invention. First, the active region is separated by the LOCOS oxide film 2 and the p-well region 3 formed by B doping is formed.
A polysilicon gate pattern is formed on a Si substrate 1 having Specifically, a 10 nm gate oxide film 4 is formed on the active region, and a polysilicon film 5 is
Then, the polysilicon film 5 is processed into a gate electrode pattern by a photo-etching process (FIG. a).

A thermal CVD-SiO ₂ film 6 is formed on the Si substrate.
Is formed to a thickness of 100 nm (FIG. B). The thermal CVD-SiO ₂ film 6 is etched by an anisotropic dry etching technique, and the thermal CVD-SiO ₂ film is removed while leaving the side spacers 7 (FIG. C).

[0010] A thermal CVD-SiO ₂ film 8 is formed as an in-place film on the entire surface of the Si substrate so as to have a thickness of 10 nm, and As ions are collectively implanted on the source, drain and gate electrodes which are not covered by the LOCOS oxide film 2. 950 ° C, 10
The ion-implanted As is activated by the heat treatment for a short time of 2 seconds to form the n + diffusion layer 9 (FIG. D).

Thermal CVD-SiO as an in-place film
₂ After wet removal of the film 8, a Co film 10 is formed on the entire surface of the substrate by a DC magnetron sputtering method to a thickness of 5 nm, and
A TiN film 11 is formed to a thickness of 10 nm (FIG. E).

Heat treatment is performed at 550 ° C. for 30 seconds in a nitrogen atmosphere to selectively form a cobalt silicide layer 12 only on the electrode in contact with Co and Si. At this stage, the cobalt silicide has a composition of Co: Si = 1: x (x ≦ 1) (FIG. F).

After the unreacted Co film and TiN film are removed by wet etching, a heat treatment is carried out at 750 ° C. for 30 seconds in a nitrogen atmosphere to change the cobalt silicide layer 12 to Co: Si =.
Conversion to a 1: 2 stoichiometric compound (CoSi ₂ ) (FIG. G).
Finally, the thickness of the cobalt silicide layer 12 becomes 17 nm.

A Co film 13 is again formed on the entire surface of the substrate by DC magnetron sputtering to a thickness of 5 nm, and a TiN film 14 is further formed thereon.
Is formed to a thickness of 10 nm (FIG. H).

Heat treatment is performed at 550 ° C. for 30 seconds in a nitrogen atmosphere to selectively form a cobalt silicide layer only on the electrode where Co and CoSi ₂ already formed on the substrate are in contact. The cobalt silicide formed at this stage consumes Si in CoSi ₂ on the substrate and Co: Si =
1: Composition of x (x ≦ 1) is obtained. Unreacted Co film and Ti
After the N film is removed by wet etching,
Heat treatment at 50 ° C. for 30 seconds to form a cobalt silicide layer 15
Is converted to a stoichiometric compound (CoSi ₂ ) with Co: Si = 1: 2 (FIG. I). Finally, the thickness of the CoSi ₂ layer 15 becomes 34
nm. The sheet resistance of this CoSi ₂ film is 7.3Ω /
□, the specific resistance is 25 μΩcm. In the logic LSI, the sheet resistance of the diffusion layer is required to be 10Ω / □ or less, which is a value that sufficiently satisfies this.

The CoSi ₂ film thus formed is made of CoS
i ₂ forming step has a significantly different characteristics as CoSi ₂ film formed was formed by heat treatment at a time Co film total amount without splitting, CoSi ₂ of it a source and a drain surface has conventionally been a problem In this case, an increase in junction leakage current at this time is suppressed.

A mechanism for suppressing an increase in junction leak current when the source and drain surfaces are converted to CoSi ₂ according to the present invention will be described below with reference to this embodiment.

One is the CoSi formed according to the present invention.
_This is an effect obtained by changing the state of the interface between the _two films and the Si substrate from that according to the conventional method. The CoSi ₂ film formed by the conventional method has poor flatness at the interface with the Si substrate. In particular, a spike phenomenon occurs in which the cobalt silicide in the middle of the reaction grows deeper into the Si substrate in a needle-like manner until the p / n junction is reached. . Further, even when spike-shaped growth does not occur, a phenomenon occurs in which Co locally diffuses deeply to form non-stoichiometric cobalt silicide microcrystals. A part of the cobalt silicide crystal thus formed destroys the p / n junction surface and causes junction leakage.

On the other hand, according to the present embodiment, the depth of the spike-like growth and the local diffusion of Co is less than half of the conventional depth. This is due to the formation mechanism of CoSi ₂ . CoSi ₂ is more C than Co at the first heat treatment.
oSi and CoSi from CoSi during the second heat treatment
Is formed in two steps reaction to ₂ phenomenon due to local diffusion of the above Co is to occur in the process of CoSi is formed from Co. In the present embodiment, CoS is
The reaction for forming i is only a step of first reacting 5 nm of Co with the Si substrate to form CoSi. The second 5 nm-thick Co film consumes Si in the already formed CoSi ₂ to convert CoSi. Since it is formed, the Si substrate does not participate in the reaction, and the local diffusion phenomenon of Co does not occur. That is, in the present embodiment, Co that causes local diffusion of Co is used.
Is a thickness of 5 nm, which is half the thickness of 10 nm of Co required for forming a CoSi ₂ film of the same thickness by the conventional method, and the depth reached by local diffusion of Co is also the conventional method. And the occurrence of junction leakage can be suppressed.

FIG. 2 shows a reverse IV curve of the n + / p junction fabricated in this embodiment in comparison with a case where a CoSi ₂ film having the same thickness is formed by a conventional method. According to this embodiment, it is possible to satisfy the specification (specification 1) of a junction leakage current density of 2 × 10 ⁻¹⁴ A / μm ² or less when 5 V is applied, which is necessary for a logic LSI.

Table 1 shows that various methods were used to form C on the n + / p junction.
The ratio of the sample satisfying the above specification 1 when the oSi ₂ film is formed and the stricter specification (specification 2) of 1 × 10 ⁻¹⁴ A / μm ² or less is shown. In Table 1, (Co 5 nm + 5n)
m) is the above embodiment, and the film thickness described earlier is the first Co film thickness, and the film thickness described later is the second Co film thickness. For example, (Co 7 nm + 3n
m) means that the first Co film thickness is 7 nm and the second Co film thickness is 3 nm.

Table 1 shows that the specification 1 can be satisfied by dividing the formation of the CoSi ₂ film into two times. Also, comparing the number of samples satisfying the specification 2, the used C
Even when the total film thickness of o is the same, the effect of suppressing junction leakage is highest when the first and second Co film thicknesses are equal, and the effect is higher when the second Co film thickness is thicker. It can be seen that the effect when the film thickness is larger is the smallest. However, even in this case, the occurrence of junction leakage current is suppressed as compared with the conventional method in which all Co films are formed and reacted at once, and the effect of the present invention can be understood. Similarly, (Co 3 nm +
(3 nm + 4 nm) means that the Co film formation is divided into three times,
This is a result when the film thickness is formed in the order of 3 nm, 3 nm, and 4 nm. Also in this case, the occurrence of the junction leak current is suppressed as compared with the conventional method, and the effect of the present invention can be understood.

[0023]

[Table 1]

The junction leakage current generated at the p / n junction includes a surface leakage component generated on a flat junction surface and a peripheral component generated on the outer peripheral portions of the source and the drain. This is an effective way to control. On the other hand, one of the generation mechanisms of the peripheral leak is CoSi ₂
In this mode, the film grows excessively in the lateral direction, and the p / n junction interface below the boundary with the surrounding LOCOS oxide film is destroyed in the lateral direction. The present invention is also effective in suppressing the junction leak by this mode.

According to the present invention, this can be achieved by making the shape of the CoSi ₂ film around the source and drain different from the conventional one. In the CoSi ₂ film formed by the conventional method, as shown in FIG.
While the film is formed to have a substantially uniform thickness until it comes into contact with the COS oxide film 23, according to the present embodiment, as shown in FIG. 4, the diffusion from the end of the surrounding LOCOS oxide film 27 toward the inside of the MOS transistor. A region 29 where the CoSi ₂ layer is not formed occurs on the layer. This is a characteristic when the CoSi ₂ film is formed from a thin Co film having a thickness of less than 10 nm, and it is considered that the difference in the Co film quality depending on the film thickness has an influence.

The width of the area which is not formed in the CoSi ₂ has been shown to depend in a Co film thickness of participating in one time of the reaction, the width of the area that is not formed of CoSi ₂ is to be controlled by utilizing this feature it can. C formed for the first time
By reducing the film thickness and repeatedly forming the CoSi ₂ film many times, the width of the region where CoSi ₂ is not formed can be kept wide even when the finally formed CoSi ₂ film is thick. Also, the width of the area that is not formed of CoSi ₂ enough to tightly Co film formation before the substrate cleaning conditions tend to become narrower and also known, is not formed of CoSi ₂ by the substrate cleaning conditions before Co film It is possible to control the width of the area. In extreme cases, cleaning with diluted hydrofluoric acid before forming the Co film is
CoSiSi when the etching time is longer than
_The region where no ₂ is formed disappears, and the CoSi ₂ film becomes LOC.
It is formed with a uniform film thickness until it comes into contact with the OS oxide film.

Table 2 shows that the film thickness of the finally formed CoSi ₂ is kept constant, and the Co on the diffusion layer is changed by changing the process conditions.
5 V when the width of the region where Si ₂ is not formed is changed
Junction leak current per unit peripheral length at the time of application 1 × 10
The ratio of the sample that can satisfy the specification of ^-14 A / μm or less is shown. According to Table 2, if there is a region where the CoSi ₂ layer does not exist more than 50 nm from the outer LOCOS oxide film toward the inside of the diffusion layer, the peripheral leak component does not increase until the specification cannot be satisfied. It is necessary to keep the width of this region within a range that does not affect device characteristics. For a device having a gate length of 10 μm, C
The gate length loss due to oSi ₂ not being formed is 4
% Or less, that is, a width of 200 nm or less on one side, is a size that is absorbed by manufacturing variations and is within an allowable range.

[0028]

[Table 2]

(Embodiment 2) FIG. 5 illustrates a method of manufacturing a semiconductor device according to the present invention, which is different from Embodiment 1. A polysilicon gate pattern is formed on a Si substrate 31 having an active region separated by a LOCOS oxide film 32 and having ap − well region 33 formed by B doping. Specifically, a 10 nm gate oxide film 34 is formed on the active region, a 250 nm polysilicon film 35 is formed thereon, and the polysilicon film 35 is processed into a gate electrode pattern by a photo-etching process (FIG. A). ). Thermal CVD on this Si substrate
-A SiO ₂ film 36 is formed to a thickness of 100 nm (FIG. B).

This thermal CVD-SiO ₂ film is etched by the anisotropic dry etching technique,
Leaving 7 to remove heat CVD-SiO ₂ film (FIG. C).
Thermal CVD-Si as an in-place film on the entire surface of the Si substrate
An O ₂ film 38 is formed to a thickness of 10 nm. As is ion-implanted on the entire surface of the Si substrate, and As is collectively formed on the source, drain and gate electrodes which are not covered with the LOCOS oxide film 32.
Ion is implanted.

The ion-implanted As is activated by a short-time heat treatment at 900 ° C. for 10 seconds (FIG. D).

Thermal CVD-SiO as an in-place film
_{After the 2} film 38 is wet-removed, a 5 nm-thick Co film 40 is formed on the entire surface of the substrate by DC magnetron sputtering, and a 10 nm-thick TiN film 41 is further formed thereon (FIG. E). Heat treatment is performed at 550 ° C. for 30 seconds in a nitrogen atmosphere to selectively form a cobalt silicide layer 42 only on the electrode where Co and Si come into contact. At this stage, the cobalt silicide is Co: Si
= 1: x (x ≦ 1) composition (FIG. F).

After the unreacted Co film and the TiN film are removed by wet etching, a heat treatment is performed at 750 ° C. for 30 seconds in a nitrogen atmosphere to form the cobalt silicide layer 42 with Co: Si =
Conversion to a 1: 2 stoichiometric compound (CoSi ₂ ) (FIG. G).
Finally, the thickness of the cobalt silicide layer 42 becomes 17 nm.

The steps so far are the same as those in the first embodiment.
Next, 3 nm of the cobalt silicide layer 42 is diluted with diluted hydrofluoric acid.
Etching (FIG. H). The etching rate in hydrofluoric acid diluted 1:99 was 3 nm / min, and etching was performed for 60 seconds.

A Co film 43 is again formed on the entire surface of the substrate by DC magnetron sputtering with a thickness of 5 nm, and a TiN film (4
4) is formed to a thickness of 10 nm (FIG. I). 550 under nitrogen atmosphere
A heat treatment is performed at 30 ° C. for 30 seconds to selectively form a cobalt silicide layer only on the electrode where Co and CoSi ₂ already formed on the substrate are in contact. The cobalt silicide formed at this stage consumes Si in CoSi ₂ on the substrate to have a composition of Co: Si = 1: x (x ≦ 1). After the unreacted Co film and TiN film are removed by wet etching, a heat treatment is performed at 750 ° C. for 30 seconds in a nitrogen atmosphere to convert the cobalt silicide layer 45 to a stoichiometric compound of Co: Si = 1: 2.
(CoSi ₂ ) (FIG. J). Finally, the thickness of the cobalt silicide layer 45 becomes 31 nm.

According to this method, not only the effects described in Embodiment 1 can be obtained, but also effects specific to this method can be obtained. That is, the finally obtained CoSi ₂
The specific resistance of the film can be reduced as compared with the first embodiment. This is because impurities such as titanium or cobalt oxide remaining on the surface are removed by etching the surface of the initially formed CoSi ₂ film. CoSi ₂
It was further formed Co film on the film during the ₂ of CoSi, initially remained in CoSi ₂ film surface impurity causes to increase the rest resistivity to CoSi ₂ film to be formed later. By removing this impurity by this method, the specific resistance of the finally formed CoSi ₂ film was changed from 25 μΩcm in Example 1 to 20 μΩcm. The effect of lowering the specific resistance can be reduced to some extent by etching the CoSi ₂ film on the way, but the sheet resistance of the CoSi ₂ film of Example 1 is 7.3Ω / □ in this embodiment. It can be seen that the resistance is reduced to □, and the effect is greater.

[0037] When etching the CoSi ₂ film surface formed earlier in order to reduce the specific resistance of the CoSi ₂ layer is sufficient with a light etching enough to impurities adhering to the surface can be removed. When the CoSi ₂ film is etched by ₂ nm or more, the effect of reducing the specific resistance of the finally formed CoSi ₂ film is recognized, and even when the CoSi ₂ film is etched by 5 nm or more, the specific resistance cannot be further reduced. That is,
The etching amount of the CoSi ₂ film is suitably 2 nm or more and 5 nm or less.

[0038]

According to the present invention, the increase in the junction leakage current when the source and drain surfaces are converted to CoSi ₂ is because Co locally diffuses deeply into the Si substrate when the Co film reacts with the Si substrate to form CoSi. Is one factor. According to the present invention, Co
The film formation was divided into a plurality of times, and some Co films
Instead of reacting with the substrate, react with CoSi ₂
The formation of oSi reduces the thickness of Co that directly reacts with the Si substrate that causes local diffusion of Co, thereby reducing the amount and depth of diffusion of Co into the Si substrate, and reducing the junction leakage current. Increase can be suppressed.

Another mechanism for increasing the junction leakage current is that the CoSi ₂ film grows too much in the lateral direction and the LO
There is a mode in which the p / n junction interface under the boundary with the COS oxide film is broken laterally. The present invention also has the effect of suppressing an increase in junction leakage due to this mode. The CoSi ₂ film formed on the source and the drain by the conventional method is formed to have a substantially uniform thickness up to the outer peripheral portion in contact with the LOCOS oxide film,
The phenomenon of excessively growing in the lateral direction was easily generated. On the other hand, when the Co film formation is divided into a plurality of times according to the present invention and the process of forming CoSi from Co is divided into a plurality of times,
CoSi formation is suppressed at the outer peripheral portion in contact with the LOCOS oxide film, and a region where silicide is not formed is generated between the LOCOS end and the cobalt silicide film. In this case,
Even if the silicide film grows too much in the lateral direction during the silicide formation reaction, the width of the region where silicide is not originally formed between the silicide film and the LOCOS oxide film is narrowed, and the silicide film may not be formed with the LOCOS oxide film. It does not reach the p / n junction surface existing below the boundary. Therefore, it is possible to suppress an increase in components around the junction leak when the CoSi ₂ film is formed, as compared with the related art.

[0040] Further, removing it to form a further Co film on the CoSi ₂ film previously formed when ₂ of CoSi, impurities remaining in CoSi ₂ film surface formed earlier with cobalt silicide film By doing so, the impurities in the finally formed CoSi ₂ film can be reduced, and the specific resistance of the CoSi ₂ film can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device of the present invention.

FIG. 2 is a reverse IV curve of an n + / p junction (Example (a) and prior art (b)).

FIG. 3 is a cross-sectional view of a semiconductor device manufactured by a conventional method.

FIG. 4 is a cross-sectional view of a semiconductor device manufactured according to the method of the present invention.

FIG. 5 is a sectional view showing a manufacturing process of a semiconductor device different from that of the first embodiment of the present invention.

[Explanation of symbols]

1 ... Si substrate, 2 ... LOCOS oxide film, 3 ... p-well region 4 ... gate oxide film, 5 ... polysilicon film, 6 ... heat CVD-SiO ₂ film, 7 ... side spacers, 8 ... heat CV
D-SiO ₂ film, 9 ... source and drain regions, 10 ...
Co film, 11 ... TiN film, 12 ... Cobalt silicide layer, 13 ... Co film, 14 ... TiN film, 15 ... Cobalt silicide layer, 21 ... Si substrate, 22 ... Source and drain region, 23 ... LOCOS oxide film, 24 ... Cobalt silicide layer, 25 ... Si substrate, 26 ... Source and drain regions, 27 ... LOCOS oxide film, 28 ... Cobalt silicide layer, 29 ... A region where CoSi ₂ is not formed, 31 ...
Si substrate, 32 LOCOS oxide film, 33 p-well region, 34 gate oxide film, 35 polysilicon film, 36
... thermal CVD-SiO ₂ film, 37 ... side spacer, 38
... thermal CVD-SiO ₂ film, 39 ... source and drain regions, 40 ... Co film, 41 ... TiN film 42 ... cobalt silicide layer, 43 ... Co film, 44 ... TiN film 45 ... cobalt silicide layer.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Hiroshi Kaede 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Katsuki Kojima 5, Katsumi-Honcho, Kodaira-shi, Tokyo Hitachi-LSI Engineering Co., Ltd. (72) Inventor Hiromi Abe 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Semiconductor Company Semiconductor Company, Ltd. (72) Invention Person Masayasu Suzuki 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd.

Claims (6)

[Claims] A surface formed of cobalt silicide (C) formed in an active region on a Si substrate separated from its surroundings by an insulating film.
a source and drain electrode covered by an oSi ₂ ) layer, a gate electrode composed of a laminated film of a gate insulating film, a polysilicon layer, and a metal silicide layer which are divided between the source and drain electrodes; In a MOS transistor comprising side spacers covering both sides, a cobalt silicide layer on source and drain electrodes is formed once, a cobalt silicide layer is formed once, then a Co film is formed on the cobalt silicide layer, and the Co film is silicided. Forming a cobalt silicide layer at least once to form a cobalt silicide layer having a predetermined thickness greater than that of the initially formed cobalt silicide layer. 2. A source and drain electrode having a surface covered with a cobalt silicide layer formed in an active region on an Si substrate separated from the surroundings by an insulating film, and a source and a drain electrode are provided separately. In a MOS transistor comprising a gate electrode, which is a laminated film of a gate insulating film, a polysilicon layer, and a metal silicide layer, and side spacers covering both sides of the gate electrode, a cobalt silicide layer on source and drain electrodes is formed by forming a film. After a cobalt silicide layer having a thickness of less than 30 nm is once formed, a Co film is formed on the cobalt silicide layer, and the Co film is silicidized to form a cobalt silicide at least once, thereby obtaining a predetermined thickness of 30 nm or more. A method for manufacturing a MOS transistor, comprising: 3. The method of manufacturing a MOS transistor according to claim 1, wherein a Co film formed on a substrate for forming a cobalt silicide layer first has a second or subsequent film thickness on the cobalt silicide layer. A method for manufacturing a MOS transistor, wherein the thickness is less than or equal to the thickness of a Co film to be formed. 4. A source and drain electrode formed on an active region on a Si substrate which is separated from its surroundings by an insulating film and whose surface is covered with a cobalt silicide layer, and which is provided between the source and drain electrodes. In a MOS transistor comprising a gate electrode, which is a laminated film of a gate insulating film, a polysilicon layer, and a metal silicide layer, and side spacers covering both sides of the gate electrode, the surface of the source and drain electrodes is higher than the outer insulating film. A MOS transistor comprising: a region where a cobalt silicide layer does not exist on a diffusion layer having a width of 50 nm or more and 200 nm or less toward the inside of a MOS transistor; and a region where a cobalt silicide layer exists on a diffusion layer inside the diffusion layer. 5. The method of manufacturing a MOS transistor according to claim 1, wherein the previously formed cobalt silicide layer is removed from the surface by a thickness of 2 nm to 5 nm, and then a Co film is formed on the cobalt silicide layer. A method for manufacturing a MOS transistor, comprising forming a cobalt silicide layer to a predetermined thickness by performing at least once a step of forming and silicidizing the Co film to form CoSi ₂ . 6. A method of manufacturing a MOS transistor according to claim 1, wherein the metal silicide layer on the gate electrode is made of cobalt silicide, and is formed simultaneously with the cobalt silicide layers on the source and drain electrodes. A method for manufacturing a MOS transistor.