JPH1126755A - Mos transistor, semiconductor device and manufacture of mos transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the gate resistance and the wiring resistance to the low levels, by sequentially laminating a silicide layer, the metal layer of a group VIII or a group IB and a wiring layer in this order on the upper surface of an insulating film, and forming a gate electrode. SOLUTION: An insulating film 2 is formed on an Si substrate 1, and a silicide layer 3 is formed on a gate forming region on the film 2. The entire upper surface of the substrate is covered with an insulating film 6. An opening part is formed at one part of the film, and the silicide layer 3 is exposed. After the upper surface of the substrate is flattened, a Cu layer 8 is formed. The upper surface of the substrate is polished until the insulating film 6 appears on the surface. The excessive Cu layer 3 other than the vicinity of the gate- electrode forming part is removed. Then, after an insulating film is formed on the entire upper surface on the substrate, a contact hole for drawing out the wiring is formed. A wiring layer 9 comprising Al and Au is formed in the contact hole, and a gate electrode 10, an drain electrode 11 and a source electrode 12 are completely formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of various electrodes such as a gate electrode formed on a semiconductor substrate, and more particularly to a technique for reducing a resistance value of an electrode portion.

[0002]

2. Description of the Related Art A MOS transistor has a gate electrode of Cu.
When the gate electrode is formed of a high melting point metal such as Mo, the surface may be oxidized and the gate resistance may be increased. is there. For this reason, a gate electrode is formed using polysilicon, or a silicide (for example, WSi ₂ or MoSi
And the like, and an example in which the gate electrode has a double structure using a metal such as tungsten and polysilicon is also proposed.

[0003]

When the gate electrode has such a double structure, the gate resistance can be reduced as compared with the case where the gate electrode is formed only of polysilicon. However, since the conventional double-structured gate electrode contains polysilicon inside, the resistance value is considerably higher than that of a metal such as Cu.

Also, when passive elements such as capacitors and resistors are formed on a semiconductor substrate, high-frequency characteristics are deteriorated unless the resistance value of the electrodes of the passive elements is sufficiently low.
In order to operate a semiconductor device in a high frequency band, it is necessary to reduce the resistance of each electrode portion as much as possible.

The present invention has been made in view of the above points, and has as its object to provide a MOS transistor, a semiconductor device, and a method of manufacturing a MOS transistor which can reduce gate resistance and wiring resistance as much as possible. It is in.

[0006]

According to a first aspect of the present invention, there is provided a MOS transistor having a gate electrode formed on a semiconductor substrate via an insulating film. It comprises a silicide layer formed on the upper surface of the insulating film, a group VIII or IB metal layer formed on the upper surface of the silicide layer, and a wiring layer formed on the upper surface of the metal layer.

According to a second aspect of the present invention, in a MOS transistor having a gate electrode formed on a semiconductor substrate via a first insulating film, the gate electrode is formed on an upper surface of the first insulating film. A silicide layer, a second insulating film formed on the upper surface of the silicide layer, a refractory metal layer formed on the second insulating film and having a lower surface coating an inner wall of a groove reaching the silicide layer; A VIII or IB group metal layer formed inside the groove coated with the high melting point metal layer, and a wiring layer formed on the upper surface of the metal layer.

According to a third aspect of the present invention, there is provided a diffusion layer formed on a semiconductor substrate, a silicide layer formed directly or via an insulating layer on an upper surface of the diffusion layer, and a diffusion layer formed on the upper surface of the silicide layer. A metal layer of Group VIII or Group IB, and a wiring layer formed on the upper surface of the metal layer and serving as an electrode extraction portion of the diffusion layer.

According to a fourth aspect of the present invention, there is provided a diffusion layer formed on a semiconductor substrate, a silicide layer formed directly or via an insulating layer on an upper surface of the diffusion layer, and a diffusion layer formed on the upper surface of the silicide layer. A refractory metal layer formed on the insulating film, the lower surface of which coats the inner wall of the groove reaching the silicide layer; and a refractory metal layer formed inside the groove coated with the refractory metal layer. A metal layer of Group VIII or Group IB, and a wiring layer formed on the upper surface of the metal layer and serving as an electrode extraction portion of the diffusion layer.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a MOS transistor having a gate electrode formed on a semiconductor substrate via an insulating film, wherein a step of forming a first insulating film on the semiconductor substrate is provided. Forming a silicide layer on a part of the upper surface of the first insulating film, forming a second insulating film on the upper surface of the silicide layer, and surrounding the first insulating film; Forming a groove in a part of the insulating film to expose the silicide layer; forming a group VIII or IB metal layer inside the groove to planarize the upper surface of the substrate; Forming a third insulating film on the upper surface of the converted substrate, forming a groove in a part of the third insulating film to expose the metal layer, and forming a wiring for taking out the gate electrode inside the groove. Forming a layer.

According to a sixth aspect of the present invention, in the method for manufacturing a MOS transistor formed on a semiconductor substrate, a step of forming a first insulating film on the semiconductor substrate; Forming a silicide layer in the portion,
Forming a second insulating film on the upper surface of the silicide layer and surrounding the first insulating film; forming a groove in a part of the second insulating film to expose the silicide layer; A step of coating the inner wall of the groove with a high melting point metal, a step of forming a Group VIII or IB group metal layer inside the coated groove to flatten the upper surface of the substrate, and Forming a third insulating film on the upper surface of the substrate; forming a groove in a part of the third insulating film to expose the metal layer; and forming the wiring layer for taking out the gate electrode inside the groove. Forming.

The invention of claim 1 will be described with reference to FIGS. 2 and 3, for example. The "insulating film" corresponds to the SiO ₂ layer 2, the "gate electrode" corresponds to the gate electrode 2, and the "silicide layer" corresponds to the silicide layer. 3, the “metal layer” corresponds to the Cu layer 8, and the “wiring layer” corresponds to the wiring layer 9.

The invention of claim 2 will be described with reference to, for example, FIG. 4. "The first insulating film" is formed on the SiO ₂ layer 2.
The “second insulating film” corresponds to the insulating layer 6, and the “high melting point metal layer” corresponds to the barrier metal layer 21.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a MOS transistor to which the present invention is applied will be specifically described with reference to the drawings.

[First Embodiment] FIG. 1A is a top view of a MOS transistor according to the present invention, and FIG.
FIG. 1A is a sectional view taken along line 1-1 of FIG. 2 and 3 correspond to FIG.
FIG. 7 is a diagram showing a manufacturing process of the MOS transistor shown in FIG. 2 and 3 show a cross-sectional structure taken along line 2-2 in FIG.

Hereinafter, based on the process charts shown in FIGS.
The structure of the MOS transistor according to the embodiment will be described. First, as shown in FIG. 2A, an insulating film (SiO ₂ film) 2 is formed on a Si substrate 1. Next, as shown in FIG. 2B, a silicide layer 3 made of TiSi or the like is formed on the SiO ₂ film 2. Next, as shown in FIG. 2C, the silicide layer 3 on the gate formation region is etched or the like.
Excess silicide layer 3 other than that is removed.

[0017] Next, as shown in FIG. 2 (d), on the entire upper surface of the substrate by ion implantation of P or As, etc. N ^- drain regions 4 and the source region 5 of the N ⁺ of. Next, FIG.
As shown in (1), after covering the entire upper surface of the substrate with the insulating film 6, an opening 7 is formed in a part of the insulating film 6 to expose the silicide layer 3.

Next, as shown in FIG. 3A, the upper surface of the substrate is flattened by etching or the like. Next, as shown in FIG. 3B, a Cu layer 8 is formed on the upper surface of the substrate. Next, as shown in FIG.
olish) or the like to polish the upper surface of the substrate until the insulating film 6 appears on the surface.
Layer 8 is removed.

Next, as shown in FIG. 3D, after an insulating film 12 is formed on the entire upper surface of the substrate, a contact hole for drawing out a wiring is formed.
forming a wiring layer 9 made of l, Au or the like to form a gate electrode 1;
0, the drain electrode 11 and the source electrode 12 are completed.

As described above, in the MOS transistor according to the present embodiment, the gate electrode 10 has a double structure including the silicide layer 3 and the Cu layer 8, so that the gate electrode is formed more than the gate electrode is formed using the polysilicon layer. Resistance can be reduced, and operation in a high frequency band becomes more stable.

[Second Embodiment] In the second embodiment, when a double-layered gate electrode composed of a silicide layer and a Cu layer is formed, the periphery of the Cu layer is covered with a barrier metal layer to form a Cu layer.
This is to prevent abnormal diffusion of the layer.

FIG. 4 is a diagram showing a manufacturing process of the MOS transistor according to the second embodiment. 4A is the same as FIG. 2A to FIG. 2E, and therefore is omitted in FIG. After forming the opening 7 in a part of the insulating film 6,
As shown in FIG. 4A, the inner wall of the opening 7 is formed of a refractory metal layer (for example, a barrier metal layer made of W-Si-N or the like).
Cover with 21. Next, as shown in FIG.
A Cu layer 8 is formed inside and around the substrate. Subsequent steps (FIGS. 4C and 4D) are the same as FIGS. 3C and 3D.

As described above, in the second embodiment, the gate electrode 10a has a double structure including the silicide layer 3 and the Cu layer 8, and the periphery of the Cu layer 8 is formed by the barrier metal layer 21.
Therefore, the abnormal diffusion of the Cu layer 8 can be reliably prevented, the gate resistance can be reduced, and the variation in the electrical characteristics of the MOS transistor can be eliminated.

In the first and second embodiments described above,
Although the example in which the Cu layer 8 is formed on the upper surface of the silicide layer 3 has been described, the Cu layer 8 need not be particularly limited as long as the resistance is low. Cu
Other examples include metals of Group VIII (Ni, Pd, Pt, etc.) or Group IB (Ag, Au, etc.) of the periodic table. The material of the silicide layer 3 and the material of the barrier metal layer 21 are not particularly limited as long as they have low resistance.

The type of the barrier metal layer 21 in the second embodiment is not particularly limited as long as it is a high melting point metal.

[Third Embodiment] The third embodiment is a modification of the first embodiment, in which the upper layer wiring of the gate electrode is formed at the line 1-1 shown in FIG. .

FIG. 5 is a top view of the MOS transistor according to the third embodiment. FIG. 6A is a sectional view taken along line 1-1 of FIG.
FIG. 2B is a sectional view taken along line 2-2 of FIG. 5. As shown in FIGS. 5 and 6, the Cu layer 8 and the wiring layer 9 are joined at a portion taken along line 1-1 in FIG. Since the area of the line 1-1 in FIG. 5 has a larger area than the area of the line 2-2, the gate resistance can be further reduced by adopting the structure as shown in FIGS.

In addition, in the portion along the line 2-2 in FIG. 5, the Cu layer 8 and the wiring layer 9 are separated as shown in FIG. 6B to simplify the structure. Even in such an isolation structure, since the Cu layer 8 and the wiring layer 9 are joined at the line 1-1 in FIG. 5, there is no possibility that the gate resistance will increase.

It should be noted that the Cu layer 8 is taken along the line 2-2 in FIG.
And the wiring layer 9 may be joined, and the cross-sectional structure in this case is as shown in FIG. With the structure as shown in FIG. 6C, the gate resistance can be further reduced.

[Fourth Embodiment] The fourth embodiment is a modification of the third embodiment, in which the wiring layer 9 is formed only in the portion along line 1-1 in FIG.

FIG. 7 is a top view of the MOS transistor according to the fourth embodiment, FIG. 8A is a sectional view taken along line 1-1 of FIG.
FIG. 8B is a sectional view taken along line 2-2 of FIG. 7. As shown in FIGS. 7 and 8, the wiring layer 9 of the gate electrode is formed only in the portion of line 1-1 in FIG. 7, and the Cu layer 8 and the wiring layer 9 are joined at this portion.

With such a structure, the MOS
The structure of the transistor wiring area can be simplified,
Since the size of the MOS transistor can be reduced, the degree of integration can be improved.

Although the structures of the various gate electrodes of the MOS transistor have been described in the first to fourth embodiments, the electrodes of the various passive elements such as resistors and capacitors formed on the semiconductor substrate are used. As in FIG. 1, a double structure composed of silicide and a low-resistance metal may be used, or a low-resistance metal may be covered with a barrier metal layer as shown in FIG.

[0034]

As described above in detail, according to the present invention, since the gate electrode has a double structure composed of a group VIII or IB group metal layer and a silicide layer, the gate electrode is formed of only a silicide layer. Also, the gate resistance can be reduced as compared with a case where a double structure including a polysilicon layer and a metal layer is used.

If the periphery of the metal layer constituting the gate electrode is covered with a barrier metal layer, abnormal diffusion of the metal can be reliably prevented, and the gate resistance can be reduced.
Variations in the electrical characteristics of the MOS transistor can be eliminated.

[Brief description of the drawings]

FIG. 1A is a top view of a MOS transistor according to the present invention, and FIG. 1B is a cross-sectional view taken along line 1-1 of FIG. 1A.

FIG. 2 is a diagram illustrating a manufacturing process of the MOS transistor according to the first embodiment.

FIG. 3 is a diagram following FIG. 2;

FIG. 4 is a view for explaining a manufacturing process of the MOS transistor according to the second embodiment;

FIG. 5 is a top view of a MOS transistor according to a third embodiment.

6A is a sectional view taken along line 1-1 of FIG. 5, and FIG.
FIG. 2C is a sectional view taken along line 2-2 of FIG.

FIG. 7 is a top view of a MOS transistor according to a fourth embodiment.

8A is a sectional view taken along line 1-1 of FIG. 7, and FIG.
2-2 sectional drawing of a line.

[Explanation of symbols]

Reference Signs List 1 Si substrate 2 SiO ₂ film 3 Silicide layer 4 Drain region 5 Source region 6 Insulating layer 7 Opening 8 Cu layer 9, 10, 11 Wiring layer

Claims (6)

[Claims] 1. A MOS transistor having a gate electrode formed on a semiconductor substrate via an insulating film, wherein the gate electrode is formed on a silicide layer formed on an upper surface of the insulating film, and formed on an upper surface of the silicide layer. A MOS transistor comprising a group VIII or IB group metal layer to be formed and a wiring layer formed on an upper surface of the metal layer. 2. A MOS transistor having a gate electrode formed on a semiconductor substrate via a first insulating film, wherein the gate electrode comprises: a silicide layer formed on an upper surface of the first insulating film; A second insulating film formed on the upper surface of the silicide layer; a refractory metal layer formed on the second insulating film, the lower surface of which coats an inner wall of a groove reaching the silicide layer; A MOS transistor comprising: a Group VIII or IB metal layer formed inside the groove coated with a layer; and a wiring layer formed on an upper surface of the metal layer. 3. A diffusion layer formed on a semiconductor substrate, a silicide layer formed on an upper surface of the diffusion layer via an insulating layer or directly, and a group VIII or IB formed on an upper surface of the silicide layer. A semiconductor device comprising: a group III metal layer; and a wiring layer formed on an upper surface of the metal layer and serving as an electrode extraction portion of the diffusion layer. 4. A diffusion layer formed on a semiconductor substrate, a silicide layer formed directly on an upper surface of the diffusion layer via an insulating layer, or an insulating film formed on an upper surface of the silicide layer. A high melting point metal layer formed on the insulating film, the lower surface of which coats the inner wall of the groove reaching the silicide layer; and a group VIII or IB formed inside the groove coated with the high melting point metal layer. And a wiring layer formed on an upper surface of the metal layer and serving as an electrode extraction portion of the diffusion layer. 5. A method for manufacturing a MOS transistor having a gate electrode formed on a semiconductor substrate with an insulating film interposed therebetween, wherein: a step of forming a first insulating film on the semiconductor substrate; Forming a silicide layer on a portion of the upper surface of the first insulating film, forming a second insulating film on the upper surface of the silicide layer, and surrounding the first insulating film; Forming a groove in a portion to expose the silicide layer; forming a group VIII or IB group metal layer inside the groove to flatten the upper surface of the substrate; Forming a third insulating film; forming a groove in a part of the third insulating film to expose the metal layer; and forming the gate electrode wiring layer inside the groove. An MO comprising:
A method for manufacturing an S transistor. 6. A method of manufacturing a MOS transistor formed on a semiconductor substrate, comprising: forming a first insulating film on the semiconductor substrate; and forming a silicide layer on a part of an upper surface of the first insulating film. Forming, forming a second insulating film on the upper surface of the silicide layer and surrounding the first insulating film, forming a groove in a part of the second insulating film, Exposing a silicide layer; coating the inner wall of the groove with a high-melting metal; and forming a Group VIII or IB metal layer inside the coated groove to planarize the upper surface of the substrate. Forming a third insulating film on the planarized substrate upper surface; forming a groove in a part of the third insulating film to expose the metal layer; and taking out the gate electrode inside the groove Forming a wiring layer for MO, characterized in that to obtain
A method for manufacturing an S transistor.