JPH11266237A - Phase difference monitoring circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase difference monitoring circuit, capable of reducing a circuit scale on condition that the phase difference of a present device frame pulse and a reception frame pulse is not so large. SOLUTION: This phase difference monitoring circuit for receiving a first frame pulse and a second frame pulse, counting the phase difference by the number of clocks and outputting it is provided with a phase difference counter 12 for performing counting only for a phase difference monitoring range and a decoder 13 for decoding the output of the phase difference counter 12 and outputting signals regarding polarity. The output of the phase difference counter 12 is outputted as phase difference signals, and the output of the decoder 13 is outputted as polarity signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference monitoring circuit, and more particularly, to a phase difference monitoring circuit in which the number of clocks counts the phase difference between two frame pulses.

[0002]

2. Description of the Related Art In a serial data transmission system, a communication system is generally used in which a frame pulse indicating the beginning of serial data is transmitted and received at the same time as the serial data, thereby notifying the other party of the beginning of serial data.

In some cases, the user may want to know how many bits the received frame pulse position is apart from a reference inside the apparatus. This is often necessary in device testing and the like, and is often used when quantitatively measuring that the leading position of serial data output from the device falls within the standard.

Conventionally, when the phase difference of a frame pulse with respect to a reference position is counted by the number of bits, a counter that counts the time of one frame with a resolution of a bit unit is required. For example, when the frame interval is 4096 bits, a 12-bit counter capable of counting 4096 is required. If the polarity determination is performed, an up-down counter configuration is required.

Here, the polarity judgment is defined as follows. That is, it is determined whether the position of the frame pulse received with respect to the reference frame pulse inside the own device is before or after the time. Normally, when a frame pulse received before the own device reference comes, the phase is set to minus (-), and when a frame pulse received after the own device reference comes, it is set to plus (+) phase.

FIG. 9 is a block diagram showing a configuration example of a conventional apparatus. In the figure, reference numeral 1 denotes a 12-bit frame counter which receives and counts a frame pulse of the own apparatus.
The output of the frame counter 1 is input to a comparator 2, an operation unit 3, and a selector 4. Comparator 2
The frame counter output is compared with 2048 and 4096
Is compared with the intermediate value of 2048.

When the count value of the frame counter 1 is n, the operation section 3 performs an operation of 4095-n. The output of the comparator 2 determines which of the selectors 4 is output. The selector 4 receives the output of the frame counter 1 as it is and the output of the arithmetic unit 3 after the arithmetic processing. The output of the selector 4 is latched by the first latch 5 and output as a phase difference signal, and the output of the comparator 2 is latched by the second latch 6 and output as a polarity signal (±).
Is output as The operation of the circuit thus configured will be described as follows.

[0008] The phase difference monitoring frame counter 1 is initialized (loaded with 0) with its own phase and counts a clock (not shown). Further, the frame counter 1 generates a flag at the intermediate point of 4096 bits (around 2048 count), and thereafter continues to output the flag until the maximum count of 4095. Specifically, the comparator 2
Outputs this flag. For example, frame counter 1
If the count value is smaller than 2048, "0" is output, and if it exceeds 2048, "1" is output.

When the count value of the frame counter 1 becomes 0, the flag output is released. When a frame pulse is received during a period in which this flag is output (a period of “1”), the polarity display becomes −phase, and the phase difference is obtained by subtracting the frame counter count value n from the maximum count value. This subtraction process is performed by the operation unit 3. In an example, when a frame pulse is received when the count value is 10, the phase difference becomes 10 bits with a positive polarity, and when the frame pulse is received when the count value is 4086, the phase difference becomes 10 bits with a negative polarity.

FIG. 10 is a time chart showing the operation when the polarity is +. (A) is the own apparatus frame pulse, (b) is the count value of the 12-bit frame counter, (c) is the value at point A (the output of the selector 4), (d) is the received frame pulse, and (e) is the phase difference. Indicates the output (polarity).

The own frame pulse and the received frame pulse are synchronized with the input clock and have a pulse width of one clock (positive polarity). First, the 12-bit frame counter 1 is loaded with "0" by its own frame pulse and starts counting. Since one frame (frame pulse interval) is 4096 clock cycles, the count range of this 12-bit counter 1 is from 0 to 4095.

The output of the counter is connected to the comparator 2 to determine whether or not the count value is larger than 2048 (intermediate value). When the count value is 2048 or more, the output of the comparator becomes "1". When the comparator output is “1”, the selector 4 switches the phase difference output and outputs the operation result.

The arithmetic unit 3 has a maximum count value of 409.
5 is subtracted from the current count value n. As described above, when the comparator 2 is "1", the output of the arithmetic unit 3 is selected by the selector 4 and the value of 4095-n is output as the phase difference.

The polarity indication is determined by the output of the comparator 2. When the count value is larger than 2048, the polarity-is output, and when the count value is smaller than 2048, the polarity + is output. That is, the case where the result processed by the arithmetic unit 3 is output becomes the negative polarity.

FIG. 10 shows a case where a received frame pulse is received at a count value of 250. In this case, the latch 5 in the figure holds the value when the received frame pulse is received, so in this case, the phase difference output is 250, and the polarity is “0” when the output of the comparator 2 is “0”. Since the count value is 2048 or less, the polarity is +.

FIG. 11 is a time chart showing the operation when the polarity becomes-. (A) is the value at point A, (b) is the received frame pulse, and (c) is the phase difference output. This example shows a case where the count value of the frame counter 1 is 3890. Since 3896 is larger than 2048, the output of the comparator 2 becomes "1", indicating negative polarity. In this case, the output of the arithmetic unit 3 is 4095−3890 = 205, and the phase difference output is 205 bits of negative polarity.

[0017]

In the above-mentioned conventional system, a counter for counting the number of bits in one frame is required even for detecting a phase difference with a small phase difference (for example, 16 bits) as an upper limit. In addition, if the number of bits in one frame is 4096 bits, a 12-bit counter is required and the circuit scale becomes large.

For example, even when the range of phase difference to be detected is limited (for example, ± 16 bits), a counter (4096 counter) corresponding to one frame is required. Has 4 FFs, but requires 12 FFs of the 4096-bit counter, which increases the hardware for 8 FFs.

The present invention has been made in view of such a problem, and is based on the premise that the phase difference between the own apparatus frame pulse and the received frame pulse is not so large, so that the circuit scale can be reduced. It is intended to provide a phase difference monitoring circuit.

[0020]

(1) FIG. 1 is a block diagram showing the principle of the present invention. In the figure, reference numeral 10 denotes an OR gate for receiving the own apparatus frame pulse and the reception frame pulse, and 1
Reference numeral 1 denotes an AND gate which receives a frame pulse of its own device and a received frame pulse. Reference numeral 12 denotes a phase difference counter (for example, 4 bits) whose count value is initially set to "1" at the rise of the OR gate 10. A decoder 13 receives the output of the phase difference counter 12 and performs decoding. The output of the OR gate 10 is also supplied to the decoder 13.

Reference numeral 14 denotes a latch for latching the output of the phase difference counter 12. A control signal (a control signal when the own frame pulse and the received frame pulse come simultaneously) is given from the AND gate 11, and the control is also performed by the decoder 13. A signal is given.

The output of the decoder 13 is the phase difference counter 1
2 is fed back to the enable terminal EN.
Reference numeral 15 denotes a polarity determination circuit that receives the output of the decoder 13 and outputs ± polarity.

According to the configuration of the present invention, the phase difference counter 12 is initialized to "1" by the OR of the own frame pulse and the received frame pulse, and thereafter, the clock signal is changed until the output of the next OR gate becomes "1". Continue counting. When the output of the next OR gate becomes "1", the latch 14 latches the output of the phase difference counter 12 at that time as a phase difference signal. The decoder 13 is an OR gate 10
And the output of the phase difference counter 12 to supply a control signal (latch pulse) to the latch 14 and generate a polarity signal. The polarity determination circuit 15 obtains a polarity signal from the output of the decoder 13.

According to the present invention, the counter for counting the phase difference between the own apparatus frame pulse and the received frame pulse is provided, and the counter for counting the difference need only be the number of bits corresponding to the phase difference range to be detected. Can be provided.

(2) In this case, two AND gates having the output of the decoder as a common input and the first and second frame pulses as respective inputs, and a JK flip-flop receiving the outputs of these AND gates And a polarity signal is obtained from the output of the JK flip-flop.

According to the structure of the present invention, a polarity signal can be obtained by combining an AND gate and a JK flip-flop. (3) A second invention provides a phase difference monitoring circuit that receives a first frame pulse and a second frame pulse, counts and outputs the phase difference by the number of clocks, and counts only the phase difference monitoring range. A phase difference counter, and a decoder that decodes the output of the phase difference counter and outputs a signal related to polarity, and outputs the output of the phase difference counter as a phase difference signal and the output of the decoder as a polarity signal. A phase difference monitoring circuit characterized by the following is built in the phase control type clock generator to quantitatively output a transient phase pull-in phenomenon of the PLL.

According to the configuration of the present invention, it is possible to quantitatively output the phase information at the time of pulling in the phase of the PLL circuit using the phase difference monitoring circuit according to the present invention.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention. The same thing as FIG.
The same reference numerals are given. In the figure, reference numeral 10 denotes an OR gate that receives the own apparatus frame pulse and the received frame pulse, and 11 denotes an AND gate that receives the own apparatus frame pulse and the received frame pulse.

Reference numeral 12 denotes a 4-bit difference counter for loading the initial value "1" with the rising of the OR gate 10 as a load signal, and reference numeral 13 denotes a decoder receiving the output of the difference counter 12. The output of the decoder 13 is fed back to the enable input terminal EN of the difference counter 12.

An OR gate 17 receives the outputs of the AND gates 16a and 16b, and a flip-flop 14 latches the output of the difference counter 12 with the output of the OR gate 17. The output of the flip-flop 14 is a phase difference signal (bit output).

Reference numeral 16a denotes an AND gate that receives the output of the AND gate 11 and the output of the difference counter 12, and 16b denotes an AND gate that receives the output of the decoder 13 and the output of the OR gate 10. Reference numeral 15a denotes an AND gate that receives the frame pulse of the own apparatus and the output of the decoder 13, and 15b denotes an AND gate that receives the received frame pulse and the output of the decoder 13. Reference numeral 15c denotes a JK flip-flop receiving the outputs of the AND gates 15a and 15b. The output of the JK flip-flop 15c indicates the polarity (±).

The OR gate 10 and the difference counter 12 constitute a counter section, the decoder 13 constitutes a decoding section, and the AND gate 11, AND gate 16a, AND gate 16b, AND gate 15a and AND gate 15b. A gate circuit is formed, and an OR gate 17, a flip-flop 14, and a JK flip-flop 15c form a latch unit. The operation of the circuit thus configured will be described as follows.

Operation of Counter Unit The difference counter 12 loads "1" upon arrival of its own frame pulse or received frame pulse. Here, the reason for loading the initial value "1" is as follows. FIG. 3 is an explanatory diagram of the reason why the initial value of the difference counter is set to “1”. The own frame pulse rises to "1" as shown in (a), and the first clock is counted at the fall. The counting of the clock is continued until the reception frame pulse rises as shown in FIG. The count value until the falling of the received frame pulse is 10, as shown in FIG. That is, when the phase difference is 10 apart, the initial value is set to "1" in order to make the counter remember 10.

In this embodiment, since the phase difference range to be detected is determined to be ± 16 bits, the difference is made to have a 4-bit configuration. In this example, the difference counter 12 prohibits the count-up operation when the output count value becomes 15 (all 1), and holds the value. This holding operation is continued until "1" is loaded by the own frame pulse to be received next or the received frame pulse.

Operation of Decoding Unit In the decoding unit, the output of the difference counter 12 is all "1".
"1" is output at the time of. By connecting the "1" output of this decoder to the enable terminal EN of the difference counter 12, the operation of the difference counter is stopped.

Operation of the Gate Circuit The gate circuit is roughly divided into the following three blocks. -1 Generation of Latch Signal of Flip-Flop for Holding Phase Difference Bit Value When the output of the difference counter 12 is other than all “1”, when the own frame pulse or the reception frame pulse is received, the latch signal of the flip-flop 14 is generated. That is, when the phase difference between the own frame pulse and the received frame pulse is within 16 clocks, the latch signal of the flip-flop 14 is generated to hold the number of difference bits.

-2 Detection of simultaneous arrival of own apparatus frame pulse and received frame pulse Simultaneous function of a decoder for setting value of flip-flop 14 to "0" when own apparatus frame pulse and received frame pulse arrive simultaneously. It is. The AND of the own frame pulse and the received frame pulse is taken by the AND gate 11, and when the condition is satisfied, the value of the difference counter 12 is masked (the output of the AND gate 16a becomes "0"), and "0" is given to the flip-flop 14. Is latched.

-3 Polarity decoding unit This is a decoding circuit for determining whether the value of the difference counter is positive or negative. When the output of the difference counter 12 is all “1”, the polarity is determined based on which of the own device frame pulse and the received frame pulse has arrived.

FIG. 4 is a time chart showing the operation when the received frame pulse is later than the own frame pulse by 10 clocks. (A) is its own frame pulse,
(B) is a received frame pulse, (c) is a difference count value, (d) is a phase difference output, and (e) is a polarity.

When the own device frame pulse becomes "1" as shown in (a), the difference counter 12 loads "1" and starts counting from "1" as shown in (c). Here, when the difference counter 12 counts “10”, it is assumed that a reception frame pulse has arrived as shown in FIG. As a result, the difference counter 12 is initialized to “1”, and the value “10” is given to the flip-flop 14 and latched by the output of the OR gate 17. At this time, the output of the decoder 13 is "0", so that the output of the OR gate 10 enters the OR gate 17 via the AND gate 16b, and gives a latch signal to the flip-flop 14.

Before the difference counter is initialized to "1", its value is all "1". When the difference counter 12 becomes all "1", the output of the decoder 13 becomes "1" and the AND gates 15a and 15b are opened. Since the next frame pulse is the own frame pulse, the AND gate 15a sets "1". ", And the output of the JK flip-flop 15c also becomes" 1 ", indicating the polarity +. At this time, the flip-flop 14 outputs a count value “10” corresponding to the phase difference.

FIG. 5 is a time chart showing the operation when the received frame pulse is 10 clocks faster than the own frame pulse. When the received frame pulse becomes "1" as shown in (b), the difference counter 12 loads "1" and starts counting from "1" as shown in (c). Here, when the difference counter 12 counts “10”, it is assumed that the own device frame pulse has arrived as shown in FIG. As a result, the difference counter 12 is initialized to “1”, and the value “10” is given to the flip-flop 14 and latched by the output of the OR gate 17. At this time, the output of the decoder 13 is "0", so that the output of the OR gate 10 enters the OR gate 17 via the AND gate 16b, and gives a latch signal to the flip-flop 14.

Before the difference counter is initialized to "1", its value is all "1". When the difference counter 12 becomes all "1", the output of the decoder 13 becomes "1" and the AND gates 15a and 15b are opened. At this time, since the next frame pulse is a received frame pulse, the AND gate 15b sets "1". And JK flip-flop 1
The output of 5c becomes "0", indicating the polarity-.
At this time, the flip-flop 14 outputs a count value “10” corresponding to the phase difference.

According to the embodiment described above, the circuit scale can be reduced on the premise that the phase difference between the own apparatus frame pulse and the received frame pulse is not so large.

FIG. 6 is a time chart showing the operation in the case where the received frame pulse is later than the own frame pulse by 20 clocks. As shown in (a), assuming that the own apparatus frame pulse first arrives, the difference counter 12 starts counting from the initial value "1". This difference counter 1
2 can only be counted up to ± 16, and all counts above it are all “1”. Therefore, as shown in (c), the output of the difference counter 12 is all "1" before the next reception frame pulse comes.

Here, the difference counter 12 is all "1".
In this state, it is assumed that a reception frame pulse has arrived as shown in FIG. As a result, the difference counter 12 is initialized to “1”. On the other hand, since the latch pulse does not reach the flip-flop 14, the flip-flop 14 keeps holding the previous value, and the value becomes indefinite.

Before the difference counter is initialized to "1", its value is all "1". When the difference counter 12 becomes all "1", the output of the decoder 13 becomes "1" and the AND gates 15a and 15b are opened. Since the next frame pulse is the own frame pulse, the AND gate 15a sets "1". ", And the output of the JK flip-flop 15c becomes" 1 ", indicating the polarity +. At this time, the flip-flop 14 outputs a saturated count value “15”.

FIG. 7 is a time chart showing the operation when the received frame pulse is 20 clocks faster than the own frame pulse. As shown in (a), when a received frame pulse comes first, the difference counter 12 starts counting from an initial value "1". This difference counter 12
Can only count up to ± 16, and all counts beyond that are all “1”. Therefore, as shown in (c), the output of the difference counter 12 is all "1" before the next own device frame pulse comes.

Here, the difference counter 12 is all "1".
In this state, it is assumed that the own apparatus frame pulse has arrived as shown in FIG. As a result, the difference counter 12 is initialized to “1”. On the other hand, since the latch pulse does not reach the flip-flop 14, the flip-flop 14 keeps holding the previous value, and the value becomes indefinite.

Before the difference counter is initialized to "1", its value is all "1". When the difference counter 12 becomes all "1", the output of the decoder 13 becomes "1" and the AND gates 15a and 15b are opened. At this time, since the next frame pulse is a received frame pulse, the AND gate 15b sets "1". And JK flip-flop 1
The output of 5c becomes "0", indicating the polarity-.
At this time, the flip-flop 14 outputs a saturated count value “15”.

FIG. 8 is a time chart showing the operation when the phases of the own frame pulse and the received frame pulse are reversed. First, as shown in (b), a reception frame pulse arrives, the difference counter 12 is initialized to "1", and the counter starts counting clocks. Here, it is assumed that the own device frame pulse has arrived as shown in FIG.

At this time, the difference counter 12 is initialized to “1”, and the count value “10” at that time is set to the OR gate 17.
Is latched by the flip-flop 14. On the other hand, the initial output of the difference counter 12 is "1", the AND gates 15a and 15b open, the AND gate 15b into which the received frame pulse enters becomes "1", and the output of the JK flip-flop 15c becomes "0". And latch the polarity-. Therefore, in this case, the count value "10" is output from the flip-flop 14 as a phase difference, and the polarity-is output from the JK flip-flop 15c.

Next, until the frame pulse comes, the difference counter 12 holds the full count value "15". At this time, as shown in (a), when the own device frame pulse comes, the difference counter 12 is initialized to “1”,
Clock counting is started from "1". When the difference counter 12 counts “10”, it is assumed that a reception frame pulse has arrived as shown in FIG. At this time,
The difference counter 12 is initialized to "1" and starts counting clocks again.

Here, assuming that a reception frame pulse has arrived as shown in (b) when the difference counter 12 has counted "10", the difference counter 12 is initialized to "1" and the clock count is counted. Start. At this time, the value “10” of the difference counter 12 is latched by the flip-flop 14 at the output of the OR gate 17.

At this time, since the initial output of the decoder 13 is "1", the outputs of the AND gates 15a and 15b are opened. At this time, since the own frame pulse comes, the output of the AND gate 15a becomes "1", the output of the JK flip-flop 15c becomes "1", and the polarity + is output. The count value “10” is output from the flip-flop 14 as a difference signal.

In the above embodiment, the difference counter 1
The case where the count value of 2 is 4 bits and 15 is taken as an example, but the present invention is not limited to this, and it is possible to take any other value (for example, 31 with 5 bits).

The present invention can be applied to a PLL circuit. For example, by incorporating the phase difference monitoring circuit according to the present invention in a phase control type clock generator, it is possible to quantitatively output the phase information when the phase of the PLL circuit is pulled in.

[0058]

As described above in detail, according to the first aspect, (1) receiving the first frame pulse and the second frame pulse, counting the phase difference by the number of clocks. A phase difference monitoring circuit that counts the phase difference monitoring range, and a decoder that decodes the output of the phase difference counter and outputs a signal related to the polarity. By providing a phase difference signal and outputting the output of the decoder as a polarity signal, a counter for counting the phase difference between the own apparatus frame pulse and the received frame pulse is provided, and the counter for counting the difference corresponds to the phase difference range to be detected. Since only the number of bits is sufficient, it is possible to provide a phase difference monitoring circuit capable of reducing the circuit scale.

(2) In this case, two AND gates having the output of the decoder as a common input and the first and second frame pulses as respective inputs, and a JK flip-flop receiving the outputs of these AND gates By obtaining a polarity signal from the output of the JK flip-flop, a polarity signal can be obtained by combining the AND gate and the JK flip-flop.

According to the second aspect of the present invention, (3) a phase difference monitoring circuit which receives a first frame pulse and a second frame pulse, counts the phase difference by the number of clocks, and outputs the counted number. A phase difference counter that counts for the monitoring range; and a decoder that decodes the output of the phase difference counter and outputs a signal related to polarity. The output of the phase difference counter is a phase difference signal, and the output of the decoder is polarity. A phase difference monitoring circuit according to the present invention is provided by incorporating a phase difference monitoring circuit characterized in that it is output as a signal into a phase control type clock generator and quantitatively outputting a transient phase pull-in phenomenon of a PLL. By utilizing this, it is possible to quantitatively output the phase information at the time of pulling in the phase of the PLL circuit.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a reason for setting an initial value of a difference counter to “1”;

FIG. 4 is a time chart showing an operation in a case where a received frame pulse is later than the own apparatus frame pulse by 10 clocks.

FIG. 5 is a time chart showing an operation when a received frame pulse is earlier by 10 clocks than its own frame pulse.

FIG. 6 is a time chart showing an operation when a received frame pulse is delayed by 20 clocks from its own frame pulse.

FIG. 7 is a time chart showing an operation when a received frame pulse is faster by 20 clocks than its own frame pulse.

FIG. 8 is a time chart showing an operation in a case where the phases of the own apparatus frame pulse and the received frame pulse are reversed.

FIG. 9 is a block diagram illustrating a configuration example of a conventional device.

FIG. 10 is a time chart showing the operation when the polarity is +.

FIG. 11 is a time chart showing the operation when the polarity is negative.

[Explanation of symbols]

 Reference Signs List 10 OR gate 11 AND gate 12 Difference counter 13 Decoder 14 Latch 15 Polarity judgment circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Jotaro Koshikawa 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Fujitsu Digital Technology Limited In-house

Claims (3)

[Claims] 1. A phase difference monitoring circuit which receives a first frame pulse and a second frame pulse, counts the phase difference by the number of clocks, and outputs the phase difference. When,
A decoder that decodes the output of the phase difference counter and outputs a signal related to polarity, and outputs the output of the phase difference counter as a phase difference signal and the output of the decoder as a polarity signal. Monitoring circuit. 2. An output of the decoder as a common input and first and second frame pulses as respective inputs.
2. The phase difference monitoring circuit according to claim 1, further comprising: two AND gates; and a JK flip-flop receiving outputs of the AND gates, and obtaining a polarity signal from an output of the JK flip-flop. 3. A phase difference monitoring circuit for receiving a first frame pulse and a second frame pulse, counting and outputting the phase difference by the number of clocks, and counting the phase difference monitoring range. When,
A decoder that decodes the output of the phase difference counter and outputs a signal related to polarity, and outputs the output of the phase difference counter as a phase difference signal and the output of the decoder as a polarity signal. The monitoring circuit is built in the phase control type clock generator,
A phase difference monitoring circuit for quantitatively outputting a transient phase pull-in phenomenon of L.