JP2000188526A - Data latch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data latch circuit that can latch correct input data at a high speed while avoiding a sudden or steady noise in the input data. SOLUTION: An inverter circuit 8, delay circuits 9, 10 and selection circuits 3, 4, 5 receive an input clock to generate a plurality of window signals thereby detecting any change point (such as a noise) in input data among them. Then a latch circuit 11 latches input data for the window signal period from which no change point is found out and outputs the latched data as output data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit, and more particularly to a data latch circuit for latching or sampling digital data in synchronization with a clock.

[0002]

2. Description of the Related Art A digital circuit of a general digital device handles a plurality of digital data. However, since the plurality of data arrive via different signal paths or circuits, a phase difference occurs due to a difference in propagation delay or the like. In order to prevent the circuit from generating a malfunction or noise due to a plurality of digital data having such a phase difference, a data latch circuit that samples data according to a clock signal and performs data phase matching is widely used.

[0003] As a conventional example of such a data latch circuit,
For example, there is a "noise removal circuit" disclosed in Japanese Patent Application Laid-Open No. 4-175917. In the conventional example of this data latch circuit, the same data is latched a plurality of times, the results are compared, and if the same result is obtained, it is determined that the latched data does not include noise. A circuit is disclosed. Japanese Patent Application Laid-Open No. Hei 3-210633 discloses a "fuzzy inference device" which discloses a latch circuit which stores data in a memory by a latch adjusted based on fuzzy inference and thereby removes noise.

[0004]

However, the above-mentioned prior art has several problems. First, even if latching is performed a plurality of times, if there is noise in all of the latches, all the latch results are the same, and as a result, the noise is recognized as data. Cannot be identified. That is, it is impossible to determine whether the data is noise or data. Further, writing / reading data to / from the memory causes a delay in the data itself, and further adds a delay due to the fuzzy inference operation, so that high-speed processing cannot be performed.

An object of the present invention is to provide a data latch circuit which can detect sudden noise and stationary noise and can perform high-speed data processing.

[0006]

In order to solve the above-mentioned problems, a data latch circuit according to the present invention employs the following characteristic configuration.

(1) In a data latch circuit for latching input data based on an input clock and obtaining output data, a window generating circuit for dividing the input clock period into a plurality of windows, and the input data in each of the windows A noise detection circuit for detecting the presence or absence of noise
A latch circuit for latching the input data without noise by the noise detection circuit.

(2) The data latch circuit according to (1), wherein the window generation circuit has an inverter circuit, a delay circuit, and a selection circuit.

(3) The data latch circuit according to (1) or (2), wherein the noise detection circuit comprises a counter and a comparator.

(4) The data latch circuit according to (3), wherein a monostable multivibrator is used instead of the counter.

(5) The data latch circuit according to (3), wherein the counter is enabled in the window and the input data is inputted to a clock terminal.

(6) In a data latch circuit for latching input data based on an input clock to obtain output data, a window generating circuit for dividing the input clock into a plurality of mutually overlapping windows; A detection circuit for detecting the presence or absence of a change point such as noise in the input data, determining the window in which a change point such as noise is not detected, latching the input data at a substantially center position of the window, and outputting the output data. And a latch circuit for obtaining data.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of a data latch circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a preferred embodiment of a data latch circuit according to the present invention. This data latch circuit includes counters 1 and 2, selection circuits 3, 4, and 5, latch circuits 6 and 11, a comparator 7, an inverter circuit 8, and delay circuits 9 and 10.

In the counter 1, input data is input to a CK terminal, and a selection output from a Y output terminal of the selection circuit 3 is input to a CTREN terminal. The count value 2 from the Q output terminal of the counter 1 is input to the D input terminal of the latch circuit 6 and one input terminal of the comparator 7. The selection output from the Y output terminal of the selection circuit 4 is input to the CK terminal of the latch circuit 6, and the count value 1 from the Q output terminal is input to the other input terminal of the comparator 7. On the other hand, the comparison result from the comparator 7 is input to the CK input terminal of the counter 2, and the Q output is input to the S terminals of the selection circuits 3, 4, and 5. The same input data as the CK input terminal of the counter 1 is input to the input terminal of the latch circuit 11, the selected output from the Y output terminal of the selection circuit 5 is input to the data latch point, and the output data is output from the output terminal. Is output.

Next, the input clock is input as the clock 3 to the input terminal of the inverter circuit 8, the C terminal of the selection circuit 3, the A terminal of the selection circuit 4, and the input terminal of the delay circuit 10. The output signal of the inverter circuit 8 is
, The input terminal of the delay circuit 9, the C terminal of the selection circuit 4, and the B terminal of the selection circuit 5 as a clock 1.
The clock 2 output from the delay circuit 9 is input to the B terminal of the selection circuit 3 and the C terminal of the selection circuit 5. Further, the clock 4 output from the delay circuit 10 is input to the B terminal of the selection circuit 4 and the A terminal of the selection circuit 5. The data latch circuit of the specific embodiment of the present invention is completed by the above components and connection relationship.

With the above configuration, the counter 1 inputs an output signal from the Y output terminal of the selection circuit 3 (a signal indicating a noise detection area, hereinafter referred to as a window) to a CK (clock) terminal as an enable signal. The input data is counted using the input clock data as a count clock signal. That is, if a trigger is present on the input data while the window is in the enabled state, the counter value of the counter 1 is updated. On the other hand, the counter 2 is always connected to the enable state, and performs a counting operation using the comparison result of the comparator 7 as a count clock signal. The output of the counter 2 is input to the S terminal as a selection signal of the selection circuits 3, 4, and 5 as described above. The counter 2 updates the count value when the comparison result of the comparator 7 changes from L to H level.

As described above, the input clock is phase-converted by the inverter circuit 8 and the delay circuits 9 and 10 to obtain clocks 1 to 4. The delay circuits 9 and 10 have a delay time of 1/4 cycle of the input clock. Thereby, four clocks 1 to 4 having mutually different phases are obtained. The selection circuit 3 receives the clocks 1 to 3 and outputs the output to the counter 1 as a window. The selection circuit 4 receives clocks 1, 3, and 4 as inputs, and its output serves as a latch clock of the latch circuit 6. The selection circuit 5
Receives clocks 1, 2, and 4, and its output becomes a latch clock of the latch circuit 11.

Next, the latch circuit 6 latches the count value 1 from the counter 1 and outputs the count value 1 to the counter 2 via the comparator 7. Latching is performed by the output of the selection circuit 4, and the timing is the same as when the window is enabled. The comparator 7 compares the count values 1 and 2, and when the comparison results do not match,
The comparison result is changed from L to H level. The comparison result is input to the counter 2 as a count clock. That is, if the count value 2 is updated while the window is enabled, the two count values do not match, and as a result, the counter 2
Is updated. The latch circuit 11 is a latch circuit that receives input data as input, and outputs output data using the output of the selection circuit 5 as a latch clock.

Hereinafter, the operation of each part of the data latch circuit of FIG. 1 will be described in detail with reference to the timing chart of FIG. 2, (a) is input data, (b) is an input clock, (c) to (f) are clocks 1 to 4, (g).
Indicates the count value 1, (h) indicates the count value 2, and (i) indicates the comparison result.

FIG. 2 shows an example in which the input data (a) is mixed with noise at H level data. As apparent from FIGS. 2B to 2F, the clock 1 (c)
Is a clock whose input clock (b) is inverted in phase, and a clock 2 (d) is a clock 1 (c) delayed by 1/4 cycle. The clock 3 (e) is the same as the input clock (b), and the clock 4 (f) is obtained by delaying the clock 3 (e) by 周期 cycle. These clocks 1-4, ie, FIGS. 2 (c)-(f), form triggers 1-4 through rising edges. Trigger 3, 4, 1, 2
Occurs in the order of The L-level periods of clocks 1 to 3 (see (c) to (e) of FIG. 2) correspond to windows 1 to 3, respectively. Noise detection of input data is performed for each of these windows 1 to 3.

As described above, since the latch circuit 11 is latched by the clocks 1, 2, and 4 output from the selection circuit 5, the triggers 1, 2, and 4 become the latch clocks, respectively. That is, when performing noise detection in the window 1, the trigger 4 becomes the latch clock. Window 2
In the case of performing the noise detection by using the trigger 1, the trigger 1 becomes the latch clock. When noise is detected in the window 3, the trigger 2 is a latch clock.

A series of operations of the data latch circuit of the present invention will be described as follows. First, in window 1, noise detection of input data (see FIG. 2A) is performed. The window 1 is enabled using the trigger 3 (see FIG. 2E), and at the same time, the count value 1 (see FIG. 2G) is latched. At this point, the count values 1 and 2 (see (g) and (h) in FIG. 2) are the same,
The comparison result of the comparator 7 (see (i) of FIG. 2) is at the L level.

The counter 1 enabled by the window 1 updates the count value 1 when there is noise in the input data. That is, the count value 1 becomes N →
Count up by N + 1 and 1. When the count value 1 changes, the value of the count value 2 does not match, so that the comparison result changes from the L level to the H level. The value of the counter 2 is updated according to the change in the comparison result. In other words, this becomes the window switching point, and switches the window from window 1 to window 2. In the window 2, the count value 2 is updated by the trigger 4 at the same time that the window 2 is enabled. As a result, the count value 1 and the count value 2 match, and the comparison result becomes L level again.

Thereafter, noise detection is performed in the same manner as in the window 1, and the window switching operation is stopped in the window in which the noise is not detected. In the example of FIG. Therefore, the input data is latched by the trigger 1 which is the optimal timing on the window 2 (data latch point). In this way, even if noise is present on the input data, it can be detected and avoided, and the latch operation can be performed at the optimal timing of the input signal data portion without noise.

The above-mentioned clocks 1 to 4 can be obtained by using an inverter circuit 8 of a commercially available integrated circuit (IC) and a delay line. When the input clock is, for example, 8.192 MHz, the data width is 122n.
s, and the delay time of the delay line, which is 1/4 cycle, is about 30 ns. Each window is approximately 61 ns wide, allowing three windows to monitor the entire input data of 122 ns.

The windows 1, 2 and 3 are selected by the selection circuit 3 and input to the counter 1. At counter 1,
The counter operation is enabled only when the window is at the L level. Counter 1 is a commercially available IC
For example, using 74161 or the like, the count value can be updated with a counter clock of several ns or more. That is, when noise having a width of several ns or more is mixed, the counter 1 recognizes the noise as a counter clock and updates the count value 1. This means that the counter 1 can detect noise having a width of several ns or more. The clock 1-4 has a function of latching the count value 1 before performing noise detection as the count value 2, and this value is held until the next latch is performed.

The count value 1 and the count value 2 are constantly compared by the comparator 7. When noise is detected, the count value 1 is updated, so that both count values are different, and the comparison result becomes H level. The comparison result is input to the counter 2, and the count value 2 of the counter 2 is updated at a change point where the comparison result changes from the L level to the H level.

Here, the output of the counter 2 is directly used as a selection signal of the selection circuit 3-5. Updating the count value means switching windows. In other words, a window in which noise is not detected cannot be switched.

The clocks 1, 2 and 4 are supplied to the latch circuit 11
Latch clock. Here, triggers 4, 1
And 2 are the centers of windows 1, 2 and 3, respectively, so it should be noted that the optimum latch clock is selected by the selection circuit 5 so that data can be latched at the center of each window. With such a configuration, data can be latched at a sufficiently safe timing in a window in which noise is not detected.

The configuration and operation of the preferred embodiment of the data latch circuit of the present invention have been described above in detail. However, the present invention should not be limited to only such specific examples, and those skilled in the art can easily understand that various modifications can be made without departing from the paper of the present invention. For example, in the data latch circuit of FIG. 1, noise detection is performed using a counter, but a monostable (monostable) multivibrator may be used instead of the counter.

[0032]

As can be understood from the above description, according to the data latch circuit of the present invention, various practical effects not obtained in the prior art can be obtained. First, noise is recognized as the occurrence of a change point in data, and noise determination is performed. Therefore, it is possible to detect any sudden noise or stationary noise and avoid it. In addition, since data is monitored in real time (immediately) without being stored in a memory or the like, high-speed data processing is possible. Of course, since a memory or the like becomes unnecessary, the circuit configuration can be inexpensive and miniaturized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a data latch circuit of the present invention.

FIG. 2 is a timing chart illustrating an operation of the data latch circuit of FIG. 1;

[Description of Signs] 1, 2 Counter 3, 4, 5 Selection Circuit 6, 11 Latch Circuit 7 Comparator 8 Inverter Circuit 9, 10 Delay Circuit

Claims (6)

[Claims] 1. A data latch circuit for latching input data based on an input clock to obtain output data, comprising: a window generating circuit for dividing the input clock period into a plurality of windows; A data latch circuit, comprising: a noise detection circuit that detects the presence or absence of noise; and a latch circuit that latches the input data without noise by the noise detection circuit. 2. The data latch circuit according to claim 1, wherein said window generation circuit has an inverter circuit, a delay circuit, and a selection circuit. 3. The data latch circuit according to claim 1, wherein said noise detection circuit comprises a counter and a comparator. 4. The apparatus according to claim 3, wherein a monostable multivibrator is used in place of said counter.
3. The data latch circuit according to 1. 5. The data latch circuit according to claim 3, wherein the counter is enabled in the window, and is configured by inputting the input data to a clock terminal. 6. A data latch circuit for latching input data based on an input clock to obtain output data, comprising: a window generating circuit for dividing the input clock into a plurality of mutually overlapping windows; A detection circuit for detecting the presence or absence of a change point such as noise in the input data; determining the window in which the change point of noise or the like is not detected; latching the input data at a substantially central position of the window; A data latch circuit comprising: