JPH11266157A - Feedback circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a feedback circuit which is capable of suppressing the effects due to delays, without giving load upon an element which is included in the circuit and which cannot deal with a fast operation clock. SOLUTION: This feedback circuit includes a switching control signal generation part 10, a double width signal generation part 11 and a switching part 12. A digital signal generated by a high speed operation clock(Cka) is converted into a signal which is equivalent to the original operation clock(Ck). Then, the switching part 12 performs switching of an output, on the basis of this signal. Thus, since the switching part 12 performs the switching of the output by a cycle similar to the operation clock(Ck), a load is not applied on the switching part 12, even if the operation clock(Ck) is made to operate at a high speed so as to suppress the effects due to delay.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a feedback circuit for performing digital signal processing such as audio signal processing using feedback control.

[0002]

2. Description of the Related Art Generally, in a circuit for processing a digital signal or an analog signal, a delay occurring in the circuit becomes a problem as the operation clock becomes faster. This is for the following reasons. That is, signal delay usually occurs each time a signal passes through each element of the circuit. For this reason, even if the delay time generated by one element is short, the entire circuit has a long delay. Therefore, the faster the specified operating clock is, the more
The influence of the delay time increases, and adversely affects signal processing.

For example, in a switching amplifier in which an input signal is an acoustic signal, as the delay time of the entire amplifier increases, the oscillation limit, S / N (signal-to-noise ratio), and D range (dynamic range) decrease. Such a problem arises.

In such a switching amplifier,
The measurement results of the frequency dependence of the quantization noise level are shown in FIGS. These measurements show the delay time of the playback system as 0 seconds (no delay), 6 seconds.
0 ns (60 ns) and 100 ns (100 ns)
s). As shown in these figures, the oscillation limit value of the switching amplifier, S / N (signal-to-noise ratio), and D range (dynamic range)
Decrease as the delay time of the reproduction system increases.

On the other hand, if a 1-bit feedback circuit is used, such a delay can be absorbed. In the one-bit feedback circuit, the effect of the delay can be reduced by increasing the operating clock of the entire circuit.

[0006] The 1-bit feedback circuit is applied to, for example, a switching amplifier that performs audio signal processing. FIG. 15 is a block diagram showing a configuration of such a switching amplifier. As shown in this figure, the switching amplifier includes a switching control signal generation unit 31 and a switching unit 32.

[0007] The switching control signal generator 31 receives an analog signal from an input unit (not shown), converts the analog signal into a digital signal by a predetermined method, and outputs the digital signal.
The switching control signal generator 31 is a 1-bit feedback circuit using delta-sigma modulation or the like.

The switching section 32 converts the digital signal output from the switching control signal generation section 31 into an output signal having a preset voltage value, and outputs the output signal to a speaker or the like (not shown) via a low-pass filter (not shown). Output. Further, the switching unit 32 includes a switching control signal generation unit 3 for feedback control of the switching control signal generation unit 31.
1 also outputs this signal.

[0009] The above-mentioned audio signal processing is
This is a process in which an analog signal reproduced from a storage medium or the like is once converted to a digital signal, then amplified, reconverted to an analog signal, and output.

A switching amplifier for audio signal processing has the following advantages. That is,
An amplifier that amplifies and outputs an analog signal as it is requires a large-capacity capacitor, a large-sized radiating fan or a radiating plate, and has a problem that its volume and power consumption are large. On the other hand, a switching amplifier for audio signal processing generates less heat and can be reduced in volume.

[0011]

However, FIG.
The switching amplifier as described in (1) has the following problems. Normally, in a circuit such as a switching amplifier, all elements in the circuit operate with the same operation clock. Therefore, if the operation clock is made faster, all the elements in the circuit operate at a higher speed. For this reason, in the configuration of FIG. 15, when the operation clock of the switching control signal generation unit 31 is increased to suppress the delay occurring in the circuit, not only the switching control signal generation unit 31 but also a signal of a predetermined level voltage value is output. The switching unit 32 for performing the operation is also operated at high speed. Therefore, the load on the switching unit 32 becomes very large.

The present invention has been made in order to solve the above problems, and an object of the present invention is to include an element in a circuit, such as the switching unit 32, which is difficult to correspond to a fast operation clock. Even so, it is an object of the present invention to provide a feedback circuit that can suppress the influence of the delay without imposing a load on the element.

[0013]

According to a first aspect of the present invention, there is provided a feedback circuit for generating a digital signal by inputting an analog signal from the outside and having a predetermined amplitude. A feedback circuit that converts the signal into an external signal and outputs the signal again as a feedback signal generates a digital signal from an externally input analog signal and a feedback signal based on a first operation clock. A digital signal generating section for converting the input digital signal into a signal having a predetermined amplitude, outputting the converted signal to the outside, and outputting this signal as a feedback signal to the digital signal generating section. When,
A digital signal conversion unit for converting the digital signal output from the digital signal generation unit so that the minimum pulse width is longer than the cycle of the first operation clock, and outputting the converted signal to the switching unit. It is characterized by:

According to the above configuration, the first operation clock is an operation clock for operating the digital signal generator. Further, the operation clock cycle is a sampling cycle for generating a digital signal. That is, the digital signal generator converts an analog signal into a digital signal using the frequency of the first operation clock as a sampling frequency. Also,
The first operation clock is a high-speed clock that can suppress the influence of the delay of the feedback circuit.

When an analog signal is input to the feedback circuit, the digital signal generator generates a digital signal based on the first operation clock and outputs the digital signal to the digital signal converter. When this digital signal is input, the digital signal converter converts the digital signal so that its minimum pulse width is longer than the cycle of the first operation clock, and outputs the digital signal to the switching unit.

Therefore, the switching section switches the output voltage at least in a cycle that is slower than the cycle of the operation clock of the digital signal generation section. Thereby, in order to suppress the delay of the entire feedback circuit,
Even if the first operation clock, that is, the operation clock of the digital signal generation unit is made faster, a large load is not applied to the switching unit. This makes it possible to avoid the influence of the delay in the feedback circuit without placing a burden on the switching unit.

Here, the pulse width is the time during which a voltage of the same level continues in the digital signal, and the minimum pulse width is the shortest pulse width in the digital signal. In many cases, the minimum pulse width is the same as the period of the operation clock in the digital signal generator.

According to a second aspect of the present invention, in the feedback circuit according to the first aspect, the digital signal converter includes a period of the second operation clock in which the minimum pulse width is slower than the first operation clock. The digital signal conversion is performed as described above. In the above configuration, the second operation clock is an operation clock that does not cause an excessive load even if the switching unit switches the voltage in a cycle based on the operation clock, and is referred to as an original operation clock of the feedback circuit. Should be.

In the above configuration, the minimum pulse width of the digital signal input from the digital signal converter to the switching unit is a time longer than the cycle of the second operation clock. Therefore, the switching unit switches the output voltage at a cycle equal to or shorter than the second operation clock which is the original operation clock of the feedback circuit.
As a result, even if the first operation clock is made faster to avoid the influence of the delay in the feedback circuit, it is possible to reliably prevent a large load from being applied to the switching unit.

According to a third aspect of the present invention, in the feedback circuit according to the second aspect, the period of the second operation clock is an integral multiple of the period of the first operation clock. . According to the above configuration, the minimum pulse width of the digital signal input from the digital signal conversion unit to the switching unit is an integer (excluding 1 and 0) times the cycle of the first operation clock. Therefore, the switching unit switches the output voltage at a period that is at least twice as long as the operation clock of the digital signal generation unit.

Thus, even if the first operation clock is made faster in order to avoid the influence of the delay in the feedback circuit, it is possible to more reliably prevent the switching section from being overloaded. Further, a circuit configuration in which the cycle of the second operation clock is an integral multiple of the cycle of the first operation clock is a configuration that can be easily realized. Therefore, the manufacture of the feedback circuit becomes easy, and the manufacturing cost can be reduced.

According to a fourth aspect of the present invention, in the configuration of the first aspect, the digital signal output from the digital signal generation unit is a binary 1-bit signal. According to the above configuration,
The quantizer used for the digital signal generator can be a binary 1-bit quantizer, that is, a comparator.
Therefore, it is easy to realize the feedback circuit according to the first aspect.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. FIG. 1 is a block diagram illustrating a configuration of a switching amplifier according to the present embodiment (hereinafter, referred to as the present switching amplifier). As shown in the figure, the present switching amplifier includes a switching control signal generator 10,
A double-width signal generation unit 11 and a switching unit 12 are provided.

The switching control signal generator (digital signal generator) 10 is a circuit for converting an analog signal into a binary 1-bit digital signal by delta-sigma modulation and outputting the signal. In addition, the switching control signal generator 10 performs sampling with an operation clock Cka (first operation clock) faster than an operation clock Ck (second operation clock) described later.
That is, the sampling frequency of the switching control signal generator 10 is the frequency of the operation clock Cka.

The operation clock Ck is such that the switching section 12 described later can operate normally, and is an original operation clock of the present switching amplifier. FIGS. 2A and 2B show the relationship between the operation clock Ck and the operation clock Cka. FIG. 2A is an explanatory diagram showing a waveform of the operation clock Ck, and FIG. 2B is an explanatory diagram showing the operation clock Cka. As shown in these figures, the cycle of the operation clock Ck is
This is twice the period of ka. That is, the operation clock Ck
a is twice as fast as the operation clock Ck.

FIGS. 3A and 3B are explanatory diagrams showing digital conversion by the switching control signal generator 10. FIG. 3A shows an analog signal input to the switching control signal generator 10. It is an explanatory view for explaining. A in the figure is a comparator threshold (quantization threshold) preset in the switching control signal generator 10. When such an analog signal is input, the switching control signal generation unit 10 sets the level of the input analog signal to the threshold A, as shown in FIG.
If so, a "+1" digital signal is output. On the other hand, when the level of the analog signal is smaller than the threshold value A, a digital signal of "-1" is output.

Double-width signal generator (digital signal converter)
Numeral 11 receives a 1-bit digital signal output from the switching control signal generator 10 and converts this signal into a signal corresponding to the operation clock Ck. That is, the minimum pulse width is set to a value equal to or longer than the period of the operation clock Ck. Is converted and output.

FIGS. 4A, 4B and 4C are explanatory diagrams for explaining a method of converting the pulse width of the digital signal by the double-width signal generator 11. Of these, FIG.
4A is an explanatory diagram illustrating a part of a digital signal output from the switching control signal generation unit 10 and input to the double-width signal generation unit 11, and FIG. FIG. 4 is an explanatory diagram showing a digital signal output by a double-width signal generation unit 11 when the digital signal shown is input.
FIG. 4C is an explanatory diagram showing the operation clock Cka.

Then, the double-width signal generator 11 samples the input signal based on the operation clock Cka and, based on the value of the input signal and the values of the output signal one cycle before and two cycles before, corresponds to the input signal. The output signal value to be determined is determined as follows. That is, when the value of the output signal one cycle before the input signal is different from the value of the output signal two cycles before, the value of the output signal corresponding to the input signal is set to the value of the output signal one cycle before. When the value of the output signal one cycle before the output signal and the value of the output signal two cycles before the input signal are the same, the value of the output signal corresponding to the input signal is set to the value of the input signal.

For example, the value of the input signal at T1 in the figure is "+1" as shown in FIG. 4A, and the value of the output signal at T2 and T3 is as shown in FIG. 4B. Are both "-1". In this case, the value of the output signal at T1 is “+1”. The value of the input signal at T5 is "-1", and the output signals at T6 and T7 are "+1" and "-1", respectively.
In this case, the value of the output signal at T5 is “+1”.

By such a conversion, the digital signal shown in FIG. 4A becomes a digital signal having a doubled minimum pulse width as shown in FIG. 4B. That is, the minimum pulse width of the digital signal shown in FIG. 4A is the same as the cycle of the operation clock Ck.

FIG. 5 is an explanatory diagram showing an example of a logic circuit in the double-width signal generator 11 for performing the above-described conversion.
As shown in this figure, this circuit includes a NOT circuit 25, A
It is composed of ND circuits 26 to 28 and an OR circuit 29. Then, the input signal is input to the point X, the output signal one cycle before is input to the point Y, and the output signal two cycles before is input to the point Z. According to this circuit, FIG.
The input signal shown in FIG. 4A can be converted to an output signal as shown in FIG.

FIGS. 6 to 8 show other examples of conversion by the double-width signal generator 11. FIG. FIG. 6 (a), FIG. 7 (a)
When the digital signal shown in FIG. 8A and the digital signal shown in FIG. 8A are input to the double-width signal generation unit 11, the digital signal shown in FIG.
This is output as the digital signal shown in FIG. 8B and FIG.

The switching section 12 includes the double-width signal generation section 1
1 as a control signal, and using this signal as a control signal, a predetermined voltage value (+ V
Or -V) and outputs the signal to a reproduction system (not shown). That is, the switching unit 12
Is to switch and output a signal of a predetermined positive or negative amplitude in accordance with a change in the value of the digital signal output from the double-width signal generation unit 11. The switching section 12 outputs this signal to the switching control signal generation section 10 as a feedback signal.

The operation of the present switching amplifier will be described below.
A reproduction system to which the present switching amplifier is applied will be described as an example. FIG. 9 is a block diagram showing this reproduction system. As shown in this figure, this playback system
A pair of audio signal sources 21, a switching control signal generator 10, a double width signal generator 11, a low-pass filter (LPF) 22 and a speaker (SP) 23 are provided for each of the left and right channels. And a switching unit 12 for a channel.

The operation of the reproducing system will be described below. In this reproduction system, when analog signals are output from the left and right channel acoustic signal sources 21, 21.
The switching control signal generators 10 and 10 convert the analog signal and the signal fed back from the switching unit 12 into an operation clock C using delta-sigma modulation.
The digital signal is converted into a digital signal based on ka, and is output to the double-width signal generators 11. Then, the double-width signal generator 11
11 converts the digital signal input from the switching control signal generators 10 into a signal corresponding to the operation clock Ck and outputs the signal to the switching unit 12 as a control signal.

The switching section 12 includes the double-width signal generation section 1
A control signal of a digital signal input from 1.1 is converted into a signal of a preset voltage, and this signal is output to the switching control signal generator 10 as a feedback signal. The switching unit 12 outputs this signal from the left and right channel speakers 23 via the low-pass filters 22.

The conversion of the digital signals by the double-width signal generators 11 will be described with reference to FIGS. FIGS. 10A and 10B show the operation clock Ck.
FIG. 4 is a waveform diagram showing an operation clock Cka. Also,
FIG. 10C is a waveform diagram illustrating an example of a digital signal output from the switching control signal generators 10 when the operation is performed by the operation clock Cka. FIG. 10D is a waveform diagram showing a digital signal output from the double-width signal generation units 11 when a digital signal as shown in FIG. 10C is input.

Switching control signal generators 10
Outputs a digital signal as shown in FIG. 10C in response to the operation clock Cka shown in FIG. 10B. Then, the double-width signal generators 11 and 11
A digital signal as shown in FIG.
The signal is converted into a signal corresponding to k, and a digital signal as shown in FIG. This double-width signal generator 11
As a result, the minimum pulse width of the digital signal shown in FIG. 10C becomes the same as the pulse width of the operation clock Ck as shown in FIG. Therefore, the switching unit 1 that inputs this digital signal as a control signal
The output switching cycle in 2 is equivalent to the output switching cycle performed based on the signal digitally converted by the operation clock Ck. The double-width signal generator 11
The conversion of the digital signal at 11 is shown in FIG.
According to the method described with reference to (b).

As described above, in the above reproduction system,
The switching control signal generators 10 are operated with an operation clock Cka twice as fast as the operation clock Ck. Then, the switching control signal generator 1
The output signals from 0.10 are converted to double-width signal generators 11
In the above, the signal is converted into a signal corresponding to the operation clock Ck, and a control signal is sent to the switching unit 12.

Thus, in the reproduction system described above, even if the operation clock Cka of the switching control signal generators 10 and 10 is increased in order to reduce the influence of the system delay, a load is imposed on the switching unit 12. There is nothing.

In the switching amplifier and the reproduction system described above, the switching control signal generator 10
Is a binary 1-bit signal, and based on this signal, the switching unit 12 outputs a signal of a predetermined positive or negative amplitude, but the output of this switching amplifier is limited to this. Not something. For example, the switching unit 12 may be configured to output a multi-level signal of three or more values.

For example, a configuration for outputting a ternary signal can be realized if the switching control signal generator 10 is configured to output two 1-bit signals. FIG.
(A)-(c) is explanatory drawing which shows the output signal of the switching control signal generation part 10 in this structure. When generating a ternary digital signal, the switching control signal generator 10 generates a binary comparator threshold value (quantization threshold value) B · as shown in FIG.
C and generates two digital signals as shown in FIGS. 11 (b) and 11 (c).

That is, the switching control signal generator 1
0 is set to “+1” when the level of the input analog signal is equal to or higher than the threshold B, and to “0” when the level is smaller than the threshold B, to generate a digital signal as shown in FIG. Output. At the same time, when the level of the analog signal is equal to or higher than the threshold value C, the digital signal is generated as shown in FIG. Output. When these digital signals shown in FIGS. 11B and 11C are combined, they become ternary digital signals as shown in FIG. 11D.

The two digital signals shown in FIGS. 11B and 11C have their pulse widths converted by the double-width signal generation unit 11 and are then input to the switching unit 12, where they are synthesized and " −V ”,“ 0 ”and“ + V ”
It is converted into a value signal (V is the magnitude of a predetermined amplitude).

As described above, the switching control signal generator 10 uses two comparator thresholds,
A ternary digital signal can be output as a 2-bit 1-bit signal. The digital signal having a value of “0” remains at 0 even if amplified. Therefore, the switching unit 12 does not need to amplify the signal of “0” among the input ternary digital signals, and as a result, it is possible to suppress power consumption.

That is, when the output signal is a digital signal having three or more values, the switching control signal generator 1
A value of 0 preferably converts an analog signal into a ternary digital signal including “0”. If the digital signal generated by such conversion is used, the switching unit 12 does not need to amplify the digital signal whose value is “0”. Therefore, it is possible to reduce the power consumption of the feedback circuit.

The switching control signal generator 10
However, if three or more digital signals are generated using three or more threshold values and output to the double-width signal generation unit 11, a multi-valued signal of three or more values can be output.

When outputting a multi-valued digital signal of three or more values, the switching control signal generator 10 outputs the digital signal after the synthesis as shown in FIG. Signal width of the pulse width of
May be converted.

In the above-mentioned reproducing system, the operation clock Cka of the switching control signal generators 10 is also used.
Is twice as fast as the operation clock Ck (the operation clock Ck).
Is twice as long as the operation clock Cka), but the value of the operation clock Cka of the switching control signal generators 10 is not limited to this, and any value can be used as long as the influence of the system delay can be avoided. Good. That is, the operation clock Cka of the switching control signal generator 10
May be 1.3 times or 1.76 times the operation clock Ck. The value of the operation clock Ck may be any value as long as the switching unit 12 can operate.

The operation clock Cka is set to an integral multiple (excluding 0 and 1) of the operation clock Ck, that is, the cycle of the operation clock Ck is set to an integral multiple of the cycle of the operation clock Cka. Is preferred. A feedback circuit in which the operation clock Cka is an integer multiple of the speed of the operation clock Ck can be realized with a relatively simple configuration. Therefore, the load on the configuration of the reproduction system or the switching amplifier can be reduced.
A system can be constructed relatively easily.

In the present switching amplifier and the reproducing system, it is preferable that the operation clock Cka of the switching control signal generator 10 is set to an optimum value based on the delay time of the present switching amplifier and the reproducing system. . Since the influence of the delay changes depending on the change in the delay time, the influence of the delay can be effectively suppressed by setting the operation clock Cka to an optimum value based on the delay time. Furthermore, by not setting the high-speed operation clock Cka unnecessarily, it is possible to suppress costs in manufacturing and operating the switching amplifier or the reproduction system.

The switching control signal generator 10
Describes that a digital signal is generated by using delta-sigma modulation, but the method of generating a digital signal by the switching control signal generation unit 10 is not limited to this, and any conversion method may be used. The digital signal output from the switching control signal generator 10 is preferably a 1-bit signal.

The conversion of the digital signal in the double-width signal generator 11 is performed such that the digital signal generated from the analog signal based on the operation clock Cka is generated based on the operation clock Ck. Is preferred. By doing so, the switching unit 1
2 is the same as the output performed based on the signal digitally converted by the operation clock Ck, and includes the switching control signal generator 10 and the double-width signal generator 11.
, It is possible to prevent the occurrence of distortion due to the conversion.

The present switching amplifier is an example of the feedback circuit of the present invention, and the present invention is not limited to this switching amplifier. That is, the feedback circuit of the present invention can be applied to any circuit that performs AD conversion (analog-digital conversion) by feedback control.

The feedback circuit of the present invention generates a digital signal by inputting an analog signal from the outside, converts the signal into a signal having a predetermined amplitude, and outputs the signal to the outside. A digital signal generation unit for generating and outputting a digital signal from an externally input analog signal and a feedback signal based on a first operation clock, and And a switching unit that outputs the signal to the digital signal generation unit as a feedback signal and outputs the digital signal as a feedback signal to the digital signal generation unit. Conversion so as to be longer than the cycle of the first operation clock. A feedback circuit, comprising: a digital signal converter for outputting to the switching unit, wherein the digital signal generator outputs a plurality of binary 1-bit signals; The width signal generation unit converts the pulse widths of the plurality of signals and outputs the converted signals. Further, the switching unit outputs a multi-valued signal of three or more values based on the plurality of signals output from the double width signal generation unit. May be output.

[0057]

As described above, the feedback circuit according to the first aspect of the present invention generates a digital signal by inputting an analog signal from the outside, converts the signal into a signal having a predetermined amplitude, and outputs the signal to the outside. And a feedback circuit for re-inputting the signal as a feedback signal, wherein a digital signal is generated for generating and outputting a digital signal from an externally input analog signal and a feedback signal based on the first operation clock. A switching unit that converts the input digital signal into a signal having a predetermined amplitude and outputs the signal to the outside, and outputs the signal as a feedback signal to the digital signal generation unit; The output digital signal is compared with the minimum pulse width of the first
And a digital signal converter for converting the operation clock to be longer than the period of the operation clock and outputting the converted signal to the switching unit.

According to the above configuration, the switching unit includes:
The switching of the output voltage is performed at least in a cycle that is slower than the cycle of the operation clock of the digital signal generator. Accordingly, even if the first operation clock, that is, the operation clock of the digital signal generation unit is made faster in order to suppress the delay of the entire feedback circuit, a large load is not applied to the switching unit. Therefore, there is an effect that the influence of the delay in the feedback circuit can be avoided without putting a load on the switching unit.

According to a second aspect of the present invention, in the feedback circuit according to the first aspect, the digital signal converter includes a second operation clock cycle whose minimum pulse width is slower than the first operation clock. The configuration is such that the digital signal is converted as described above. According to the above configuration, the switching unit switches the output voltage at a cycle equal to or shorter than the cycle of the second operation clock that is the original operation clock of the feedback circuit. As a result, even if the first operation clock is made faster to avoid the influence of the delay in the feedback circuit, it is possible to reliably prevent a large load from being applied to the switching unit.

A third aspect of the present invention provides the feedback circuit according to the second aspect, wherein the cycle of the second operation clock is an integral multiple of the cycle of the first operation clock. According to the above configuration, the switching unit switches the output voltage at a cycle that is at least twice as long as the operation clock of the digital signal generation unit. As a result, even if the first operation clock is made faster to avoid the influence of the delay in the feedback circuit, it is possible to more reliably prevent a large load from being applied to the switching unit.

Further, since the period of the second operation clock is set to be an integral multiple of the period of the first operation clock, it is relatively easy to construct the feedback circuit. And the production cost can be reduced.

A fourth aspect of the present invention is the feedback circuit according to the first aspect, wherein the digital signal output from the digital signal generation unit is a binary 1-bit signal. According to the above configuration, the quantizer used for the digital signal generator can be a binary 1-bit quantizer, that is, a comparator. Therefore, in addition to the effect of the first aspect, the effect that the feedback circuit of the first aspect can be easily realized is achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a switching amplifier according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an operation clock of a switching control signal generation unit and an operation clock of a switching unit in the switching amplifier shown in FIG.

FIG. 3 is an explanatory diagram showing generation of a digital signal by a switching control signal generation unit in the switching amplifier shown in FIG. 1;

FIG. 4 is an explanatory diagram for explaining a method of converting a pulse width in a digital signal by a double-width signal generation unit in the switching amplifier shown in FIG. 1;

FIG. 5 is an explanatory diagram showing an example of a logic circuit in a double-width signal generation unit in the switching amplifier shown in FIG.

FIG. 6 is an explanatory diagram illustrating an example of a digital signal input to the double-width signal generation unit and a digital signal converted by the double-width signal generation unit.

FIG. 7 is an explanatory diagram showing another example of a digital signal input to the double-width signal generation unit and a digital signal converted by the double-width signal generation unit.

FIG. 8 is an explanatory diagram showing still another example of a digital signal input to the double-width signal generation unit and a digital signal converted by the double-width signal generation unit.

FIG. 9 is a block diagram showing an example of a reproduction system to which the switching amplifier shown in FIG. 1 is applied.

FIG. 10 is an explanatory diagram for explaining conversion of a digital signal by a double-width signal generation unit in the reproduction system shown in FIG. 9;

11 is an explanatory diagram illustrating generation of a digital signal by a switching control signal generation unit when the switching amplifier illustrated in FIG. 1 generates a ternary signal.

FIG. 12 is a graph showing a measurement result of the frequency dependence of a quantization noise level in a switching amplifier that does not use a 1-bit feedback circuit when there is no delay time.

FIG. 13 is a graph showing a measurement result of a frequency dependence of a quantization noise level when a delay time is 60 nanoseconds in a switching amplifier that does not use a 1-bit feedback circuit.

FIG. 14 is a graph showing the measurement results of the frequency dependence of the quantization noise level when the delay time is 100 nanoseconds in a switching amplifier that does not use a 1-bit feedback circuit.

FIG. 15 is a block diagram showing a configuration of a conventional switching amplifier using a 1-bit feedback circuit.

[Explanation of symbols]

Reference Signs List 10 switching control signal generation unit (digital signal generation unit) 11 double width signal generation unit (digital signal conversion unit) 12 switching unit Ck operation clock (second operation clock) Cka operation clock (first operation clock)

Claims (4)

[Claims] 1. A feedback circuit for generating a digital signal by inputting an analog signal from the outside, converting the signal into a signal having a predetermined amplitude, outputting the signal to the outside, and re-inputting the signal as a feedback signal. A digital signal generation unit for generating and outputting a digital signal from an externally input analog signal and a feedback signal based on the operation clock of the input device, and converting the input digital signal into a signal having a predetermined amplitude A switching unit that outputs the digital signal as a feedback signal to the digital signal generation unit; and outputs the digital signal output from the digital signal generation unit to a minimum pulse width of the first operation clock. To convert to be longer than the cycle and output to the switching unit Feedback circuit, characterized in that it comprises a digital signal converter. 2. The digital signal converter according to claim 1, wherein the digital signal converter converts the digital signal so that the minimum pulse width is equal to or longer than a period of a second operation clock that is slower than the first operation clock. Item 2. The feedback circuit according to item 1. 3. The feedback circuit according to claim 2, wherein the cycle of the second operation clock is an integral multiple of the cycle of the first operation clock. 4. The feedback circuit according to claim 1, wherein the digital signal output from the digital signal generator is a binary 1-bit signal.