JP2002237729A - Switching amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching amplifier circuit capable of eliminating the need to change a digital sigma modulation circuit itself at the time of changing a switching element. SOLUTION: This switching amplifier circuit is provided with a digital sigma modulation circuit 39 having a plurality of multipliers for digital sigma- modulating an input signal, and for outputting a quantized signal and a pulse amplifier circuit 34 for switching a switching element based on the quantized signal, and for pulse-amplifying the quantized signal so that the pulse amplifier circuit 34 can be negatively fed back to the digital sigma modulation circuit 39, and that the output of the pulse amplifier circuit 34 can be demodulated through a low pass filter 35. The digital sigma modulation circuit 34 is constituted so that the coefficient of each multiplier can be switched according to the delay time of the switching element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier for an audio signal, and more particularly to a switching amplifier circuit for pulse-amplifying a quantized signal obtained by delta-sigma modulation as a switching control signal.

[0002]

2. Description of the Related Art A 1-bit signal obtained by delta-sigma modulation (.DELTA..SIGMA. Modulation) can be expanded in an effective frequency band or a dynamic range by appropriately setting a coefficient value of an integrator. This makes it possible to set a frequency according to a sound source or the like. For this reason, in the new standard of CD (compact disk) and DVD (digital video disk), this 1-bit signal is adopted and commercialization is about to be performed.

On the other hand, a 1-bit signal obtained by the above-mentioned delta-sigma modulation is not only used for recording an acoustic signal or transmitting it between devices. As a higher-quality audio amplifier than a conventional PWM (pulse width modulation) switching amplifier circuit, a high-speed sampling 1-bit switching amplifier circuit can be adapted to the audio field.

The above-mentioned switching amplifier circuit includes a semiconductor power amplifier element (switching element).
A bit signal is directly input to a semiconductor power amplifying element for switching, and a high-voltage switching pulse obtained is obtained by simply removing a high-frequency component by an LPF (low-pass filter) to obtain a power-amplified demodulated analog acoustic signal. it can.

In addition, the semiconductor power amplifying element is used not in a linear region (unsaturated region) but in a nonlinear region (saturated region) as in a conventional amplifier.
Such a switching amplifier circuit based on a high-speed sampling 1-bit system using delta-sigma modulation has an advantage that power amplification can be performed with extremely high efficiency.

As described above, the above-described switching amplifier circuit based on the high-speed sampling 1-bit method can be adapted to the audio field, but for this purpose, negative feedback is performed from the analog output section to the analog input section. , It is necessary to improve the distortion factor and S / N of the switching amplifier circuit itself.

Here, a switching amplifier circuit using a typical prior art delta-sigma modulation will be described below with reference to FIG.

The switching amplifier circuit shown in FIG. 7 includes an integrator group 11, adders 12 and 18, a quantizer 13, a pulse amplifier circuit 14, a low-pass filter 15, and an attenuator 16.
It is composed of

The delta-sigma modulation circuit 19 includes the integrator group 11, the adders 12 and 18, and the quantizer 13
It is composed of FIG. 8 shows a specific configuration example of the delta-sigma modulation circuit 19.

The delta-sigma modulation circuit 19 converts an analog input signal into a 1-bit signal. For example, as shown in FIG. 8, a cascade-connected 7 for successively integrating the analog signal is used. The next integrator H1
H7. The outputs of the integrators H1 to H6 are input to the integrators H2 to H7 at the next stage after being multiplied by predetermined coefficient values in the multipliers A1 to A6, respectively.

In connection with the integrators H2 and H3, a multiplier A11 and an adder K3 are provided.
Is delayed by a delay unit D1, multiplied by a predetermined coefficient value, and then subtracted from the input to the integrator H2 to form a negative feedback loop FB1. Similarly, the integrator H5
From the output of the integrator H4 to the input of the integrator H4.
2, a negative feedback loop FB2 composed of a multiplier A12 and an adder K4 extends from the output side of the integrator H7 to the input side of the integrator H6 to provide a delay unit D3, a multiplier A13, and an adder K4.
5 are formed respectively.

All the outputs of the integrators H1 to H7 are mutually added and subtracted by an adder 12, and the above-described quantizer 1
After being quantized into a 1-bit signal of “−1” or “+1” in 3, the signal is sent to the pulse amplifier circuit 14 of FIG. 7 as a switching control signal.

In the pulse amplification circuit 14 described above, the switching control signal is power-amplified (switching between + V and -V and power-amplified) using a switching element such as an FET, and an unnecessary signal is After removing the components, the signal is output to the outside via the output terminal.

As shown in FIG. 7, the output of the pulse amplification circuit 14 is negatively fed back to the adder 18 via the attenuator 16 (forming a feedback loop). The power-amplified 1-bit signal is supplied to the attenuator 1
After being attenuated by 6, the signal is fed back to the input side of the first-stage integrator H1, and is subtracted from the analog input signal by the adder 18.

[0015]

However, the conventional switching amplifier has the following problems.

That is, in the above-described conventional switching amplifier circuit, a delay generated from the switching element, for example, when the switching element is an FET, an input-output delay caused by a gate input capacitance of the FET causes a feedback loop. A delay occurs in the feedback signal that is negatively fed back.

That is, the delay time of the switching element affects the feedback loop, and the multipliers A1 to A6 and the multiplier A in the delta-sigma modulation circuit 19
When designing the coefficient values of 11 to A13, it is necessary to determine the coefficient values by assuming a feedback loop including the delay time of the switching element.

As a result, when the coefficient values of the multipliers A1 to A6 and the multipliers A11 to A13 are designed to be C1 to C6 and C11 to C13, respectively, only the feedback loop delay time according to the design values is obtained. I can not cope. Therefore, according to the conventional switching amplifier circuit, the multiplier A1
To A6 and the coefficient values of the multipliers A11 to A13 have a feedback loop delay time of 100 ns and a feedback loop delay time of 2
00 ns or the feedback loop delay time of 300 ns. For example, when the coefficient values of the multipliers A1 to A6 and the multipliers A11 to A13 are designed on the assumption that the feedback loop delay time is 100 ns, the case where the feedback loop delay time is 300 ns is as designed. Is not guaranteed.

Therefore, if a switching element having a feedback loop delay time that was not assumed at the time of design is used in the conventional switching amplifier circuit, the switching element differs from the feedback loop delay time assumed, so that the delta-sigma modulation circuit 19 Algorithms do not work as designed. As a result, the performance such as the oscillation limit value and the S / N cannot be obtained as designed. Therefore, when it is necessary to change to a switching element having a different feedback loop delay time due to design change or performance improvement, not only the switching element but also the delta-sigma modulation circuit 19 must be changed.

[0020]

In order to solve the above-mentioned problems, a switching amplifier circuit according to the present invention has a plurality of multipliers and performs delta-sigma modulation of an input signal to output a quantized signal. A circuit, a pulse amplifier circuit that switches a switching element based on the quantized signal to pulse-amplify the quantized signal, and a negative feedback of the pulse amplifier circuit to the delta-sigma modulation circuit,
The switching amplifier circuit for demodulating the output of the pulse amplifier circuit via a filter is characterized by taking the following measures.

That is, the switching amplifier circuit includes:
The delta-sigma modulation circuit switches a coefficient value of each of the multipliers according to a delay time of the switching element.

According to the above invention, the delta-sigma modulation circuit performs delta-sigma modulation on the input signal and outputs a quantized signal to the pulse amplifier circuit. In the pulse amplifier circuit, the switching element is switched based on the quantized signal, and the quantized signal is pulse-amplified. The output of the pulse amplification circuit is demodulated via a filter and output to the outside as an analog signal.

The output of the pulse amplifier is negatively fed back to the delta-sigma modulator. At this time, a delay occurs in the switching element in the pulse amplification circuit. Along with the occurrence of the delay, a negative feedback signal is delayed when the feedback is performed to the delta-sigma modulation circuit.

That is, the delay time of the switching element affects the feedback loop, and when designing each coefficient value of a plurality of multipliers in the delta-sigma modulation circuit, the delay time of the switching element is included. Assuming a feedback loop, the coefficient value of each multiplier needs to be determined (fixed).

In this case, as a matter of course, the switching amplifier circuit can cope only with this fixed delay time. Therefore, when a delay time different from this occurs (this corresponds to the case where a switching element other than the one assumed at the time of design is used), it differs from the assumed feedback loop delay time, so that delta The algorithm of the sigma modulation circuit does not operate as designed, and the performance such as the oscillation limit value and the S / N cannot be obtained as designed. Therefore, when it is necessary to change to a switching element with a different feedback loop delay time due to a design change, performance improvement, etc., not only the switching element but also the delta-sigma modulation circuit itself must be changed. Invite you.

Therefore, according to the present invention, in order to overcome the above problem, the delta-sigma modulation circuit switches the coefficient value of each of the multipliers according to the delay time of the switching element. That is, the delay time can be selected from a plurality of delay times without being fixed to a specific one. Therefore, even if it is necessary to change to a switching element having a different feedback loop delay time due to a design change or a performance improvement after design, it is possible to appropriately cope with maintaining the desired performance. This makes it unnecessary to change the circuit itself.

The switching of the coefficient value of each of the multipliers includes a delay time detecting circuit for detecting a delay time of the switching element, a switching circuit for outputting a switching signal based on the detected delay time, Preferably, the coefficient value of each multiplier is determined based on a first selection circuit that selects one of a plurality of coefficient values from a plurality of multipliers.

In this case, the delay time of the switching element is detected by the delay time detecting circuit. The switching circuit outputs a switching signal based on the detected delay time. Upon receiving this switching signal, the first selection circuit
One of the coefficient values of the multipliers is selected from a plurality of multipliers. As described above, it is possible to automatically select the optimum coefficient value of each multiplier for each delay time.

The delay time detecting circuit includes a pulse generating circuit for generating a pulse having a period sufficiently shorter than the quantized signal, and starts counting the pulses when the quantized signal is input and outputs the pulse from the pulse amplifying circuit. It is preferable that a pulse count circuit be provided to stop counting of the pulse when a signal is input, and that the switch circuit output the switch signal based on the pulse count of the pulse count circuit.

In this case, a pulse having a period sufficiently shorter than the quantization signal is generated by the pulse generation circuit. This pulse is input to the pulse count circuit. The quantized signal and the output signal of the pulse amplifier circuit are also input to the pulse count circuit. The pulse count circuit starts counting the pulses from the pulse generation circuit when receiving the quantized signal, and stops counting the pulses when receiving the output signal of the pulse amplification circuit. In this way, based on the number of pulses counted by the pulse generation circuit between receiving the quantized signal and receiving the output signal of the pulse amplifier circuit, the switching circuit converts the switching signal to the first signal. Output to the selection circuit. As described above, the switching of the coefficient values of the multipliers can be performed with high accuracy with a simple configuration.

As described above, instead of providing the delay time detecting circuit and automatically performing the coefficient value of the multiplier, the coefficient value of each multiplier is determined from one of a plurality of values based on an external switching signal. A configuration including a second selection circuit for selecting may be used.

In this case, since the coefficient value to be selected is manually instructed from outside, it is possible to omit the interlocking of the delay time detecting means and the multiplier coefficient switching means, and to simplify the circuit.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 1, the switching amplifier circuit of the present invention comprises an integrator group 31, adders 32 and 38, a quantizer 33, a pulse amplifier circuit 34, a low-pass filter 35,
And an attenuator 36.

The delta-sigma modulation circuit 39 includes the integrator group 31, the adders 32 and 38, and the quantizer 33.
It is composed of FIG. 2 shows a specific configuration example of the delta-sigma modulation circuit 39.

The delta-sigma modulation circuit 39 converts an analog input signal into a 1-bit signal. For example, as shown in FIG. 2, a cascade-connected 7 for sequentially integrating the analog signal is used. The next integrator h1
h7. The outputs of the integrators h1 to h6 are respectively multiplied by predetermined coefficient values in multipliers a1 to a6, and then input to the integrators h2 to h7 at the next stage.
The output of the integrator h1 is input to the multiplier a1 via the adder k6.

In connection with the integrators h2 and h3, a multiplier a11 and an adder k3 are provided.
Is delayed by a delay unit d1, multiplied by a predetermined coefficient value, and then subtracted from the input to the integrator h2 to form a negative feedback loop fb1. Similarly, the integrator h5
From the output side of the integrator h4 to the input side of the integrator h4,
2, a negative feedback loop fb2 including a multiplier a12 and an adder k4 is formed. Further, from the output side of the integrator h7 to the input side of the integrator h6, a delay unit d3 and a multiplier a
13, and a negative feedback loop fb3 including an adder k5 is formed.

The outputs of the integrators h1 to h7 are mutually added and subtracted by an adder 32, quantized by the quantizer 33 into a 1-bit signal of "-1" or "+1". The switching control signal is sent to the pulse amplifier circuit 34 in FIG.

In the pulse amplifying circuit 34, the switching control signal is power-amplified (switching between + V and -V and power-amplified) using a switching element (not shown) such as an FET, and a low-pass filter 35. After the unnecessary signal components are removed in step (1), the signal is output to the outside via an output terminal.

As shown in FIG. 1, the output of the pulse amplification circuit 34 is negatively fed back to the adder 38 via the attenuator 36 (a feedback loop 37 is formed). After the power-amplified 1-bit signal is attenuated by the attenuator 36, it is fed back to the input side of the first-stage integrator h1 and is subtracted from the analog input signal by the adder 38. , Are input to the integrator h1.

In the switching amplifier circuit of the present invention, the multipliers a1 to a6 and the multipliers a11 to a1
Each of the coefficient values 3 includes a switching signal ks from the multiplier coefficient switching circuit 30 (for the sake of convenience, the multipliers a1 to a6, and the switching signals ks1 to ks6 for the multipliers a11 to a13 and ks11 to ks13). ks). For example, FIG. 3 shows a configuration example in which the multiplier a1 can switch the coefficient value in three stages based on the switching signal ks1 from the multiplier coefficient switching circuit 30.

In this case, as shown in FIG. 3, the multiplier a1 outputs the output of the adder k6 via a switch SW1.
One end of one of the resistors R1-1, R1-2, and R1-3 is connected, and the other ends are connected to each other and to the inverting input terminal of the differential amplifier Dif1. This inverting input terminal and the output of the differential amplifier Dif1 are connected via a capacitor c1.
The output of if1 is connected to the adder k3. The non-inverting input terminal of the differential amplifier Dif1 is connected to the ground.

In the above configuration, the multiplier coefficient switching circuit 3
When receiving the switching signal ks1 from 0, the switch SW1
Selects its connection destination to be one of the three resistors. Thus, the coefficient value of the multiplier a1 can be changed in three stages.

For convenience of explanation, the multiplier a1 has been described as an example. However, the multipliers a2 to a6 and the multipliers a11 to a13 also have SW2 to SW6 and SW
The connection destinations of 11 to SW13 (none are shown) are shown in FIG.
, And the operation of the multiplier itself is the same as that of the multiplier a1, and the description is omitted here. Further, the switches SW1 to SW6 and SW
11 to SW13 are collectively referred to as switches S for convenience of explanation.
Called W.

As shown in FIG. 4, when the multiplier g1 and the integrator f1 are connected in series (for example, as shown in FIG.
Corresponds to a series connection of the multiplier a2 and the integrator h3, a series connection of the multiplier a4 and the integrator h5, and a series connection of the multiplier a6 and the integrator h7. ), A circuit can be realized with a configuration as shown in FIG. FIG. 5 includes a resistor R, a capacitor C, and a differential amplifier Dif. In this case, the coefficient value of the multiplier is represented by 1 / (fs × C × R) where fs is a sampling frequency. .

Here, the signal input to the integrator group 31 changes according to the delay time of the feedback signal, and as a result, the output of the quantizer 33 also changes. The relationship between the coefficient values will be described.

As is clear from FIGS. 1 and 2, the feedback signal which is negatively fed back by the feedback loop 37 is subtracted from the input signal by the adder 38 and then input to the integrator group 31. Although the coefficient values of the multipliers in the integrator group 31 are the same, but considering the operation of the system α and the system β having different delay times of the feedback signal, both the system α and the system β have the same input signal, The feedback signal is different between system α and system β. As a result, the value of the signal input to the integrator group 31 differs between the system α and the system β. Therefore, the signals input to the quantizer 33 are also different between the system α and the system β, so that the system α and the system β have different output signals.

Normally, as for the coefficient value of the multiplier, the delay time of the feedback signal is assumed in accordance with the delay value of the switching element to be used, and the output signal is adjusted by narrowing down the coefficient value. In order to obtain an output signal as designed with the designed coefficient value of the multiplier, it is necessary to operate with the delay time of the feedback signal assumed at the time of design. If the operation is performed with the delay time of the feedback signal which is not assumed at the time of design, the output signal differs from that at the time of design for the above-described reason, so that the performance such as the oscillation limit value and S / N cannot be obtained as designed. turn into.

The delay time of the switching element is detected by a delay time detecting circuit 40. The multiplier coefficient switching circuit 30 generates the switching signal ks based on the delay time detected by the delay time detection circuit 40 so as to switch to a preset coefficient value of each multiplier, and performs each multiplication. Output to the container.

For example, the feedback loop delay time is 100n
In the case of s, the coefficient values of the multipliers in the case of 200 ns and the case of 300 ns are designed respectively, and when the delay time detecting circuit 40 detects a delay time of about 100 ns, the multiplier coefficient switching circuit 30 is 100
The switching signal for switching to the coefficient value in the case of ns is 200n
When a delay time of s is detected, the multiplier coefficient switching circuit 30 switches a switching signal for switching to a coefficient value in the case of 200 ns. When a delay time of 300 ns is detected, the multiplier coefficient switching circuit 30 outputs a switching signal of 300 ns. A switching signal for switching to the coefficient value in the case is generated and output.

Here, a specific example of the delay time detection circuit 40 will be described in detail with reference to FIG.

The delay time detection circuit 40 is provided, for example, in FIG.
As shown in the figure, the pulse generator 41 and the pulse counter 4
2 mainly. The above pulse generator 4
Reference numeral 1 denotes an input signal to a switching element in the pulse amplification circuit 34 (that is, a 1-bit signal (quantized signal) output from the quantizer 33 in the delta-sigma modulation circuit 19).
, A pulse having a sufficiently short cycle is generated, and this pulse is sent to the pulse counter 42. The delay time detection circuit 40 monitors the input and output of the switching element and detects a delay time between the input and output of the switching element.

The pulse counter 42 receives an input signal to the switching element (that is, the one-bit signal) and an output signal of the switching element (that is, the output signal of the pulse amplification circuit 34). Is entered. The pulse counter 42 starts counting the pulses sent from the pulse generator 41 at the timing when the 1-bit signal is input, and starts counting the pulses at the timing when the output signal of the pulse amplifier circuit 34 is input. Stop counting. Thereby, the delay time of the switching element can be determined based on the counted number of pulses.

More specifically, for example, the pulse counter 42 may generate the switching signal ks according to the range of the counted number of pulses. As described above, the pulse counter 42 outputs a signal that changes according to the counted number of pulses (that is, the delay time) to the switch SW in each of the multipliers as the switching signal ks.

The pulse counter 42 can be realized by, for example, a binary counter with an enable input terminal.
In this case, the pulse of the pulse generator 41 is input to the clock input terminal, the 1-bit signal is input to the enable input terminal, and the pulse amplifier circuit 3 is input to the reset input terminal.
4 may be input.

In this case, the multiplier coefficient switching circuit 30
Can be constituted by, for example, a decoder that decodes the output from the pulse counter 42, and outputs the decoding result to the switch SW as the switching signal ks. The switch SW itself may have a decoding function. In this case, the switch SW has the function of the multiplier coefficient switching circuit 30, and the configuration is simplified.

Here, the operation in the case of the multiplier a1 shown in FIG. 3 (when the coefficient value is switched to three stages) will be described. Note that the present invention is not limited to the case where the coefficient value is switched to three levels, but can be applied to the case where the coefficient value is switched to a plurality of levels. Further, other multipliers a2
-A6 and the multipliers a11-a13 operate in the same manner, and a detailed description thereof will be omitted.

In the multiplier a1 shown in FIG.
It is assumed that the delay time of -1, the resistor R1-2, and the resistor R1-3 correspond to 100 ns, 200 ns, and 300 ns, respectively. It is to be noted that these delay times have been listed for convenience of explanation, and the present invention is not limited to these delay times.

In this case, for example, the pulse generator 41
Is assumed to correspond to 100 ns, and if less than 150 pulses are counted by the pulse counter 42 (delay time is less than 150 ns), the switching for selecting a coefficient value for 100 ns is performed. The signal ks1 is output to the switch SW1, and 150
The pulse counter 4
2 (the delay time is 150 ns
(Less than 250 ns), a switching signal ks1 for selecting a coefficient value for 200 ns is output to the switch SW1, and
When 50 or more pulses (delay time is 250 ns or more) are counted by the pulse counter 42, it is assumed that a switching signal ks1 for selecting a coefficient value for 300 ns is output to the switch SW1.

In this case, the pulse counter 42
A signal that changes in accordance with the number of counted pulses (that is, the delay time) is referred to as the switching signal ks1 and the switch S
W1 and the switch SW1 outputs the switching signal k
In accordance with s1, the coefficient value of the multiplier a1 can be switched in three stages.

For example, when less than 150 pulses are counted by the pulse counter 42 (delay time is less than 150 ns), the resistor R1-1 is selected by the switch SW. When 150 to less than 250 pulses are counted by the pulse counter 42 (the delay time is 150 ns to 250 ns)
), The resistor R1-2 is selected by the switch SW. In addition, 250 or more (delay time 25
When a pulse of 0 ns or more is counted by the pulse counter 42, the resistor R1-3 is selected by the switch SW. Note that the present invention is not limited to such a selection, and any configuration may be used as long as an appropriate selection can be made for each applicable case.

In the above, an example has been described in which the delay time detecting circuit 40 is used to optimally select the coefficient value of the multiplier. However, the present invention is not limited to this. Instead of providing 40, a configuration may be used in which a coefficient value to be manually selected is externally designated via a dip switch or the like. In this case, the configuration can be simplified.

As described above, the switching amplifier circuit of the present invention is a switching amplifier circuit that generates a pulse-amplified switching signal by switching a constant voltage application based on the delta-sigma modulated signal as a switching control signal. There is provided a multiplier coefficient switching means for instructing the switching of the multiplier coefficient according to the delay time of the switching element to be used.

According to the switching amplifier circuit, the multiplier coefficient switching means selects an optimum coefficient value for each multiplier in accordance with the delay time generated in the switching element. The device can be used.

By providing means for switching the coefficient value of each multiplier of the delta-sigma modulation section in accordance with the delay time of the switching element, performance such as the oscillation limit value and S / N can be provided to a plurality of switching elements having different delay times. It is possible to respond while maintaining. Therefore, even when it is necessary to change to a switching element having a different delay time due to a design change, performance improvement, or the like, it is sufficient to change only the switching element without changing the delta-sigma modulation unit.
It is possible to reduce costs and the like.

In the above switching amplifier circuit, it is preferable that delay time detecting means for detecting a delay time of the switching element is provided. In this case, the optimal selection of the coefficient value is automatically performed in conjunction with the delay time detecting means and the multiplication coefficient switching means.

A delay time detecting means and a multiplier are provided by externally issuing a coefficient switching instruction for switching to a multiplier coefficient optimum for the delay time according to the delay time generated in the switching element, for example, via a dip switch. The interlocking of the coefficient switching means can be omitted, and the circuit can be simplified.

[0068]

The switching amplifier circuit according to the present invention has
As described above, a delta-sigma modulation circuit having a plurality of multipliers and outputting a quantized signal by performing delta-sigma modulation on an input signal, and switching a switching element based on the quantized signal to convert the quantized signal A pulse amplifier circuit for pulse amplification, and a switching amplifier circuit for negatively feeding back the pulse amplifier circuit to the delta sigma modulation circuit and demodulating an output of the pulse amplifier circuit through a filter, wherein the delta sigma modulation circuit is It is characterized in that the coefficient value of each multiplier is switched according to the delay time of the switching element.

According to the above invention, the delta-sigma modulation circuit performs delta-sigma modulation on the input signal and outputs a quantized signal to the pulse amplifier circuit. In the pulse amplifier circuit, the switching element is switched based on the quantized signal, and the quantized signal is pulse-amplified. The output of the pulse amplification circuit is demodulated via a filter and output to the outside as an analog signal.

The output of the pulse amplification circuit is negatively fed back to the delta-sigma modulation circuit. At this time, a delay occurs in the switching element in the pulse amplification circuit. Along with the occurrence of the delay, a negative feedback signal is delayed when the feedback is performed to the delta-sigma modulation circuit.

That is, the delay time of the switching element affects the feedback loop. When designing each coefficient value of a plurality of multipliers in the delta-sigma modulation circuit, the delay time of the switching element is included. Assuming a feedback loop, the coefficient value of each multiplier needs to be determined (fixed).

In this case, as a matter of course, the switching amplifier circuit can cope only with this fixed delay time. Therefore, if a delay time different from this occurs (this corresponds to the case where a switching element other than the one assumed at the time of design is used), it differs from the assumed feedback loop delay time, The algorithm of the sigma modulation circuit does not operate as designed, and performance such as the oscillation limit value and S / N cannot be obtained as designed.

Therefore, according to the present invention, the delta-sigma modulation circuit switches the coefficient value of each of the multipliers according to the delay time of the switching element. That is,
The delay time can be selected from a plurality of delay times without being fixed to a specific one. Therefore, even if it is necessary to change to a switching element having a different feedback loop delay time due to a design change or performance improvement after design, it is possible to appropriately cope with maintaining the desired performance. This also has the effect of making it unnecessary to change the circuit itself.

The switching of the coefficient value of each multiplier is performed by a delay time detecting circuit for detecting a delay time of the switching element, a switching circuit for outputting a switching signal based on the detected delay time, Preferably, the coefficient value of each multiplier is determined based on a first selection circuit that selects one of a plurality of coefficient values from a plurality of multipliers.

In this case, the delay time of the switching element is detected by the delay time detecting circuit. The switching circuit outputs a switching signal based on the detected delay time. Upon receiving this switching signal, the first selection circuit
One of the coefficient values of the multipliers is selected from a plurality of multipliers. As described above, the effect that it is possible to automatically select the optimum coefficient value of each multiplier for each delay time is also provided.

The delay time detecting circuit includes a pulse generating circuit for generating a pulse having a period sufficiently shorter than the quantized signal, and starts counting the pulses when the quantized signal is input and outputs the pulse from the pulse amplifying circuit. It is preferable that a pulse count circuit be provided to stop counting of the pulse when a signal is input, and that the switch circuit output the switch signal based on the pulse count of the pulse count circuit.

In this case, a pulse having a sufficiently shorter period than the above-mentioned quantized signal is generated by the pulse generation circuit. This pulse is input to the pulse count circuit. The quantized signal and the output signal of the pulse amplifier circuit are also input to the pulse count circuit. The pulse count circuit starts counting the pulses from the pulse generation circuit when receiving the quantized signal, and stops counting the pulses when receiving the output signal of the pulse amplification circuit. In this way, the switching circuit converts the switching signal to the first signal based on the number of count pulses counted by the pulse generation circuit from when the quantization signal is received to when the output signal of the pulse amplification circuit is received. Output to the selection circuit. As described above, the effect that the switching of the coefficient value of each of the multipliers can be performed with high accuracy with a simple configuration is also exhibited.

As described above, instead of providing the delay time detecting circuit and automatically performing the coefficient value of the multiplier, the coefficient value of each multiplier is determined from one of a plurality of values based on a switching signal from the outside. A configuration including a second selection circuit for selecting may be used.

In this case, since the coefficient value to be selected is manually instructed from the outside, the interlocking of the delay time detecting means and the multiplier coefficient switching means can be omitted and the circuit can be simplified. Is played together.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a switching amplifier circuit of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration example of the delta-sigma modulation circuit of FIG.

FIG. 3 is a circuit diagram showing a configuration example for switching a coefficient value of a multiplier of the switching amplifier circuit.

FIG. 4 is a circuit diagram showing a place where a multiplier and an integrator are connected in series in a delta-sigma modulation circuit.

FIG. 5 is a circuit diagram showing a configuration example of FIG. 4;

FIG. 6 is a block diagram illustrating a configuration example of a delay time detection circuit in the switching amplifier circuit.

FIG. 7 is a block diagram showing an example of a switching amplifier circuit provided with a conventional typical delta-sigma modulation circuit.

8 is a circuit diagram showing a specific configuration example of the delta-sigma modulation circuit of FIG.

[Explanation of symbols]

 Reference Signs List 30 multiplier coefficient switching circuit 31 integrator group 32 adder 33 quantizer 34 pulse amplifier circuit 35 low-pass filter 36 attenuator 39 delta-sigma modulation circuit 40 delay time detection circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5J064 BA03 BA13 BB12 BC05 BC08 BC10 BC11 BC16 BC19 BC24 BC25 BD03 5J091 AA01 AA24 AA27 AA41 AA51 AA66 CA26 CA88 CA92 FA08 FA17 FA19 FA20 HA25 HA29 HA38 KA01 KA15 KA31 KA25 KA53 MA11 SA05 TA01 UW01 UW04

Claims (4)

[Claims] A delta-sigma modulation circuit having a plurality of multipliers and outputting a quantized signal by delta-sigma modulating an input signal, and switching a switching element based on the quantized signal to convert the quantized signal A pulse amplifier circuit for pulse amplification, and a switching amplifier circuit for negatively feeding back the pulse amplifier circuit to the delta-sigma modulation circuit and demodulating an output of the pulse amplifier circuit through a filter, wherein the delta-sigma modulation circuit is A switching amplifier circuit, wherein a coefficient value of each of the multipliers is switched according to a delay time of a switching element. 2. A delay time detection circuit for detecting a delay time of the switching element, a switching circuit for outputting a switching signal based on the detected delay time, and a switch for each of the multipliers based on the switching signal. The switching amplifier circuit according to claim 1, further comprising a first selection circuit that selects one of a plurality of numerical values. 3. A delay time detecting circuit comprising: a pulse generating circuit for generating a pulse having a sufficiently shorter period than the quantized signal; and a pulse amplifying circuit which starts counting the pulses when the quantized signal is inputted. And a pulse counting circuit that stops counting the pulses when the output signal is input, wherein the switching circuit outputs the switching signal based on the pulse count of the pulse counting circuit. 3. The switching amplifier circuit according to 2. 4. A switching amplifier according to claim 1, further comprising a second selection circuit for selecting one of a plurality of coefficient values of said multipliers based on an external switching signal. circuit.