JP4818900B2 - Digital amplifier and switching frequency control method - Google Patents

Description

  The present invention relates to a digital amplifier including a switching circuit of a digital amplifier and a switching frequency control circuit for controlling the switching frequency, and a switching frequency control method in the digital amplifier.

  In recent years, switching amplifiers employing a digital / analog conversion method, called digital amplifiers or 1-bit amplifiers, are widely used because of their excellent conversion efficiency and feasibility in integrated circuits.

  In the 1-bit amplifier, a method is used in which a digital signal is generated by delta-sigma modulation of an analog audio signal or a digital audio signal, and the digital signal is amplified to a predetermined amplitude by a switching circuit.

Here, a switching amplifier using delta-sigma modulation will be described with reference to FIG.
FIG. 7 is a block diagram illustrating an example of a configuration of a delta-sigma modulation circuit and a switching amplifier.

  As shown in the figure, the 1-bit amplifier 100 includes a ΔΣ modulation circuit 110, a switching circuit 120, and an LPF 130 (Low Pass Filter). Further, the ΔΣ modulation circuit 110 includes a ΔΣ A modulation 1-bit signal generation circuit 111 and a quantizer 112 are included.

  Hereinafter, control in the 1-bit amplifier 100 will be described. An input signal which is an analog audio signal or a digital audio signal from an input unit (not shown) is input to the ΔΣ modulation circuit 110. The input signal input to the ΔΣ modulation circuit 110 is sampled by the ΔΣ modulation 1-bit signal generation circuit 111, and the quantizer 112 quantizes the sampled data to generate a 1-bit digital signal. Next, the 1-bit digital signal generated by the ΔΣ modulation circuit 110 is amplified to a predetermined amplitude by the switching circuit 120, passes through the LPF 130, and is output to an output unit (not shown) such as a speaker.

  Here, the ΔΣ modulation 1-bit signal generation circuit 111 and the quantizer 112 shown in FIG. 7 operate based on a clock signal from a clock generation circuit (not shown). Therefore, by increasing the clock frequency of the reference clock signal, the time resolution of sampling in the ΔΣ modulation circuit 110 is increased, and as a result, the audio performance is improved.

  However, by increasing the clock frequency, the frequency of the digital signal input to the switching circuit 120 is also increased. As a result, the switching frequency in the switching circuit 120 is increased. Here, as the switching frequency of the switching circuit 120 increases, the heat and unnecessary radiation generated in the switching circuit 120 become a problem, contrary to the improvement in audio performance.

  First, regarding the heat generated in the switching circuit 120, the heat generation amount increases, and this heat affects other components and the switching circuit 120 itself, thereby reducing the audio performance. Therefore, in order to take measures against this heat, it is necessary to change to a part with a high temperature guarantee or to add a new part such as a heat radiating fan to the audio equipment, resulting in an increase in cost.

  Furthermore, as another adverse effect of an increase in switching frequency, there is a problem that electromagnetic noise such as unnecessary radiation that causes EMI (Electromagnetic Interference) increases. The electromagnetic noise such as unnecessary radiation is determined to be suppressed to a certain level by an international standard. Therefore, in order to prevent electromagnetic noise such as unnecessary radiation, new parts and the like are required for the audio equipment, resulting in a problem of further cost increase.

  In order to solve the above problem, in Patent Document 1, in order to suppress the switching frequency in the switching circuit, the digital signal output from the ΔΣ modulation circuit is converted into a digital signal having a certain pulse width or more. Here, ON and OFF of the switches in the switching circuit are controlled by the digital signal. Therefore, the number of times of switching in the switching circuit can be controlled without lowering the sampling frequency in the ΔΣ modulation circuit by setting the digital signal input to the switching circuit to a certain pulse width or more.

Hereinafter, a method of converting the pulse width of the digital signal from the ΔΣ modulation circuit 110 and controlling to reduce the number of switching will be described with reference to FIG.
FIG. 8 is a block diagram of a 1-bit amplifier 200 including a switching frequency control circuit 210 (described as a digital signal conversion unit in Patent Document 1) that controls a switching frequency.

  As shown in the figure, the 1-bit amplifier 200 includes a switching frequency control circuit 210 that controls the digital signal output from the quantizer 112 so that the pulse width of the digital signal is equal to or greater than a certain value. ing. The switching frequency control circuit 210 converts the digital signal from the quantizer 112 so as to have a certain pulse width or more, and outputs it to the switching circuit 120.

  The switching frequency control circuit 210 controls the pulse width of the digital signal input from the quantizer 112 in synchronization with the operation clock of the ΔΣ modulation circuit 110, and outputs the controlled digital signal to the switching circuit 120. ing.

  As an example, the operation of the switching frequency control circuit 210 when the 1-bit amplifier 200 is designed so as to limit the pulse width of the digital signal output to the switching circuit 120 to twice or more the operation clock period will be described.

  The switching number control circuit 210 first outputs the value of the output signal from the switching number control signal 210 one cycle before the operation clock and the output signal from the switching number control circuit 210 two cycles before the operation clock. Compare the value. When the value of the output signal one cycle before and the value of the output signal two cycles before are the same, the switching number control circuit 210 outputs the value of the input signal from the quantizer 112. On the other hand, when the value of the output signal for the previous cycle is different from the value of the output signal for the previous cycle, the output of the previous cycle is output regardless of the value of the signal input from the quantizer 112. Outputs the same value as the signal value. In this way, the switching frequency control circuit 210 controls the output signal so that the same value is output for two cycles of the operation clock.

Hereinafter, an example of the switching frequency control method for converting the pulse width in Patent Document 1 will be described with reference to FIGS.
9A is an explanatory diagram illustrating a digital signal input to the switching frequency control circuit 210, and FIG. 9B is an explanatory diagram illustrating a digital signal output from the switching frequency control circuit 210. FIG. 9C is an explanatory diagram showing operation clock signals of the ΔΣ modulation circuit 110 and the switching frequency control circuit 210.
Note that the values of the input signal to the switching frequency control circuit 210 and the output signal from the switching frequency control circuit 210 are two values, “+1” and “−1”.

  For example, as shown in FIG. 9B, the output signals at T1 and T2 in the figure are output signals having the same value of “−1”, and the input signal at T3 is shown in FIG. 9A. Thus, “+1”. Therefore, the output signal at T3 is “+1”, which is the value of the input signal at T3.

  On the other hand, the output signal of T2 is “−1” and the output signal of T3 is “+1”, which is a different output signal value. Therefore, the input signal at T4 is “−1”, but the output signal at T4 outputs “+1”, which is the output signal at T3 one cycle before.

  As described above, the switching frequency control circuit 210 controls the pulse width of the input signal from the quantizer 112 and outputs it to the switching circuit 120, so that the switching frequency in the switching circuit 120, that is, the switching frequency is reduced. You are in control.

  Up to this point, description has been given of a binary 1-bit amplifier in which an audio signal from an input unit (not shown) is converted and expressed as a binary signal by the ΔΣ modulation circuit 110, the switching frequency control circuit 210, and the switching circuit 120. is there.

  However, in recent years, instead of the binary 1-bit amplifier, a ternary 1-bit amplifier that represents an audio signal with a ternary signal has begun to be used.

  In the case of a binary 1-bit amplifier, one threshold is provided in the quantizer 112 (see FIG. 8), and the signal from the ΔΣ modulation 1-bit signal generation circuit 111 (see FIG. 8) is controlled by the threshold of the quantizer 112. Separately, a binary signal is generated. Specifically, the quantizer 112 outputs a “+1” signal if the input signal exceeds the threshold value, and outputs a “−1” signal if the input signal does not exceed the threshold value. The signal that becomes “+1” or “−1” is amplified by the switching circuit 120 (see FIG. 8) to “+ V” and “−V”, which are power supply voltages of the switching circuit. Therefore, in the switching circuit 120, a voltage of “+ V” or “−V” is always applied to the LPF 130 and the speaker serving as a load.

  On the other hand, in the case of a ternary 1-bit amplifier, two threshold values are provided in the quantizer, and the signal from the ΔΣ modulation 1-bit signal generation circuit is discriminated by the two threshold values of the quantizer. Is generated. Specifically, if the two threshold values in the quantizer are a threshold value A and a threshold value B, the quantizer is “+1” if the signal from the ΔΣ modulation 1-bit generation circuit exceeds the threshold value A and the threshold value B. A signal is output. If the value does not exceed the threshold A and exceeds the threshold B, “0” is output, and if the value does not exceed the threshold A and the threshold B, a signal “−1” is output. Note that the values of the ternary signals output from the quantizer, “+1”, “0”, “−1”, are represented by two digital signals.

  Thus, in the ternary 1-bit amplifier, a signal having a value of “0” can be output by providing two threshold values in the quantizer. At this time, even if the signal having the value “0” is amplified in the switching circuit, the output remains the value “0”. Therefore, the switching circuit 320 does not need to amplify the “0” signal among the input ternary signals, and as a result, power consumption can be suppressed.

Here, in Patent Document 1, in a binary 1-bit amplifier, a switching frequency control circuit that converts the pulse width of a digital signal from a quantizer and controls the switching frequency is a ternary 1-bit amplifier. It is also applicable to.
JP 11-266157 A (published September 28, 1999)

  However, a specific technique when the switching frequency control circuit described in Patent Document 1 is applied to a ternary 1-bit amplifier is not disclosed in Patent Document 1.

Here, considering the case where the conventional switching frequency control circuit is applied to the ternary 1-bit amplifier, the switching frequency control in the conventional example reduces the fidelity to the ternary signal from the modulation circuit. As a result, there is a problem that audio performance is degraded. Hereinafter, the reason will be described. First, the configuration of a ternary 1-bit amplifier provided with a switching frequency control circuit, which can be considered with reference to Patent Document 1, will be described.
FIG. 10 is a block diagram illustrating a configuration of a ternary 1-bit amplifier including the switching frequency control circuit 410.

  As shown in the figure, the 1-bit amplifier 300 includes a ΔΣ modulation circuit 310, a switching circuit 320, an LPF 330, and a switching frequency control circuit 410. Further, the ΔΣ modulation circuit 310 includes ΔΣ modulation 1 bit. A signal generation circuit 311 and a quantizer 312 are included. Further, the switching number control circuit 410 includes a conversion unit 411.

  Hereinafter, control in the ternary 1-bit amplifier 300 will be described. An input signal that is an analog audio signal or a digital audio signal from an input unit (not shown) is input to the ΔΣ modulation circuit 310. The input signal input to the ΔΣ modulation circuit 310 is sampled by the ΔΣ modulation 1-bit signal generation circuit 311, and the quantizer 312 quantizes the sampled data to generate a ternary signal. Here, the ternary signal output from the quantizer 312 is expressed by two digital signals.

  Next, the switching number control circuit 410 detects the value of the ternary signal expressed by the two digital signals from the ΔΣ modulation circuit 310. The ternary signal is converted by the conversion unit 411 in the switching number control circuit 410 so that the time for holding the same value is N times or more of the clock cycle. Specifically, the conversion unit 411 compares whether its own output signal is the same ternary signal value from N cycles to 1 cycle before the operation clock. Here, when the value of the ternary signal output from N cycles before to 1 cycle before is the same value, the value of the ternary signal input from the quantizer 312 is not converted. Output. On the other hand, if the value of the ternary signal output from N cycles before to 1 cycle before is different, the same value as the value of the ternary signal output before 1 cycle is output. Note that the conversion unit 411 outputs the output ternary signal to the switching circuit 320 as two digital signals.

  The switching circuit 320 amplifies the ternary signal from the control circuit 411 to a predetermined amplitude, and outputs the amplified signal to an output unit (not shown) such as a speaker via the LPF 330.

Next, the configuration of the switching circuit 320 in the ternary 1-bit amplifier 300 will be described.
FIG. 11 is an explanatory diagram showing the configuration of the switching circuit 320.

  As shown in the figure, the switching circuit 320 includes switches 350a to 350d, the switch 350a is a switch that connects the power supply voltage + V of the switching circuit 320 and the + side of the load 360, and the switch 350b is The switch 350 c is a switch that connects the power supply voltage + V of the switching circuit 320 and the − side of the load 360, the switch 350 c is a switch that connects the + side of the load 360 and GND, and the switch 350 d is connected to the − side of the load 360. GND is a connection switch. The load 360 is an output unit (not shown) such as the LPF 330 and a speaker in FIG.

  The switching circuit 320 switches ON / OFF of the switch in the switching circuit 320 based on the input ternary signal, and sets the potential difference of “+ V”, “0”, or “−V” to the + side of the load 360. By giving to the two signal lines connected to the negative side, the ternary signal from the switching number control circuit 410 is amplified.

  The ternary signal input to the switching circuit 320 is expressed by two digital signals from the switching number control circuit 410. The + side input shown in FIG. Of the two digital signals, one digital signal is input, and the other digital signal of the two digital signals from the switching frequency control circuit 410 is input to the negative side input.

Hereinafter, problems that occur when the conventional switching frequency control circuit 410 is used in the ternary 1-bit amplifier 300 will be described using a specific example.
FIG. 12 is an explanatory diagram showing an input signal from the quantizer 312 and an output signal to the switching circuit 320 when the conventional switching number control circuit 410 is used in the ternary 1-bit amplifier 300. is there.

  In the figure, each of the times T1 to T14 is a time in units of operation clock cycles of the ΔΣ modulation circuit 310 and the switching frequency control circuit 410. Note that the pulse width of the output signal output from the switching frequency control circuit 410 is limited to be twice or more the operation clock cycle.

  Further, the output signal from the conversion unit 411 expresses a ternary signal by two digital signals. Therefore, in the figure, one of the two digital signals from the conversion unit 411 is a digital signal A and the other is a digital signal B. The correspondence relationship between “+1”, “0”, “−1” as the values of the ternary signal and “H” / “L” as the values of the digital signals A and B is as follows. .

  The value “+1” of the ternary signal is expressed as “H” for the digital signal A and “L” for the digital signal B, and the value “0” for the ternary signal is “L” for the digital signal A. The signal B is expressed as “L”, and the value “−1” of the ternary signal is expressed as “L” for the digital signal A and “H” for the digital signal B.

  As shown at time T4 in the figure, the output signal subjected to switching frequency control has a value of “0”. This is because the switching frequency control circuit 410 outputs the value of the output signal at time T3 because the value of the output signal subjected to switching frequency control is different at times T2 and T3.

  Here, when the purpose of the switching frequency control is confirmed again, the purpose is to limit the switching frequency of each switch in the switching circuit 320. Furthermore, each switch in the switching circuit 320 is switched based on two digital signals representing a ternary signal input to the + side input and the − side input, as shown in FIG. 11.

Therefore, looking at the value of the digital signal from T2 to T4, the value of the digital signal A is L at T2 and L at T3.
The value of the digital signal B is H at T2 and L at T3. Therefore, the value of the digital signal B at T4 needs to be limited to L while maintaining the state of T3. On the other hand, the value of the digital signal A is the same at T2 and T3, in other words, the same value for two cycles of the operation clock, so the value of the digital signal A at T4 does not need to be converted. .

  However, as shown at T4 in the figure, the value of the digital signal A when the switching frequency control is performed is limited to L with respect to the value H when the switching frequency control is not performed. In other words, the output value of T4 is converted to L by the switching frequency control even though it is not necessary to convert from H to L.

  As a result, as shown at T4 in FIG. 9, the value of the output ternary signal is “0” with respect to the value “+1” of the ternary signal input from the quantizer 312. The signal value is converted.

  As described above, when the switching frequency limiting circuit used in the binary 1-bit amplifier is applied to the ternary 1-bit amplifier, the switching frequency control circuit 410 outputs the ternary signal output from the quantizer 312. Therefore, the value of the ternary signal input from the modulation circuit is converted more than necessary. That is, the ternary signal output from the control circuit is less faithful to the value of the ternary signal input from the modulation circuit. As a result, the switching frequency control in the conventional example has a problem in that the audio performance is deteriorated because the fidelity to the ternary signal from the modulation circuit is reduced.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to control the number of times of switching of a switching circuit in a ternary 1-bit amplifier, and then to output a ternary value output from the control circuit. An object of the present invention is to provide a digital amplifier and a switching frequency control method capable of improving the fidelity of a signal to a ternary signal from a modulation circuit.

In order to solve the above problems, a digital amplifier according to the present invention provides:
A modulation circuit that modulates an external electric signal into a ternary signal based on an operation clock, expresses the ternary signal by two first digital signals, and outputs the two first digital signals; A control circuit for setting the values of the two first digital signals from the modulation circuit based on a predetermined rule, and outputting the two second digital signals after the setting, and two values set by the control circuit A plurality of switches for switching ON / OFF based on the second digital signal are provided, and a voltage corresponding to the ternary signal expressed by the two second digital signals from the control circuit is amplified and output as a differential signal. A switching circuit, and the predetermined rule is one cycle from N cycles before the operation clock (N is an integer of 2 or more) with respect to the output of the second digital signal from the control circuit. If the values of the second digital signal from the control circuit are all the same until the output, the control circuit sets the value of the first digital signal from the modulation circuit as the value of the second digital signal at the time of the output. And the value of the second digital signal from the control circuit from one cycle before the operation clock to one cycle before the output of the second digital signal from the control circuit is any one. If there is a difference, the control circuit is determined to set and output the value of the second digital signal from the control circuit one cycle before the operation clock as the value of the second digital signal at the time of the output. The control circuit sets the values of these second digital signals independently for each of the two first digital signals input from the modulation circuit to the control circuit. The features.

Furthermore, the switching frequency control method according to the present invention includes:
A modulation circuit that modulates an external electric signal into a ternary signal based on an operation clock, expresses the ternary signal by two first digital signals, and outputs the two first digital signals; A control circuit for setting the values of the two first digital signals from the modulation circuit based on a predetermined rule, and outputting the two second digital signals after the setting, and two values set by the control circuit A plurality of switches for switching ON / OFF based on the second digital signal are provided, and a voltage corresponding to the ternary signal expressed by the two second digital signals from the control circuit is amplified and output as a differential signal. In the method for controlling the number of switching times in a switching amplifier having a switching circuit, the predetermined rule is based on the output of the second digital signal from the control circuit. When the values of the second digital signals from the control circuit from N cycles before (N is an integer of 2 or more) to 1 cycle before the operation clock are all the same, The value of the first digital signal from the modulation circuit is set and output as the value of the second digital signal, and 1 N from the previous N cycles of the operation clock with respect to the output of the second digital signal from the control circuit. If any one of the values of the second digital signal from the control circuit before the cycle is different, the control circuit outputs the second digital signal from the control circuit one cycle before the operation clock at the time of output. The signal value is set to be output as the value of the second digital signal, and the control circuit sets the value of the second digital signal from the modulation circuit to the control circuit. And performing independently for the each two first digital signal to be inputted to.

  In the above configuration, an external electric signal input to the digital amplifier is sampled and quantized in units of operation clock cycles by a modulation circuit in the digital amplifier, and a ternary signal (hereinafter abbreviated as a ternary signal). ) Is modulated. This modulation circuit expresses the ternary signal as two first digital signals and outputs them.

  Next, the two first digital signals from the modulation circuit are input to the control circuit. Here, in order to control the number of times of switching in the switching circuit, the control circuit inputs 2 so that the ON period or OFF period of the switch in the switching circuit is N times or more of the operation clock cycle of the modulation circuit. The value of one first digital signal is controlled independently for each first digital signal. The two controlled second digital signals are input from the control circuit to the switching circuit.

  Here, the switches in the switching circuit are switched ON / OFF based on the two second digital signals from the control circuit. That is, “H” or “L” which is the value of these two second digital signals corresponds to the ON or OFF of the switch, and the ON / OFF of the switch is changed when the value of the second digital signal is switched. Also switches.

  Therefore, the control circuit controls the values of the two first digital signals input from the modulation circuit, and outputs the two second digital signals after the control, thereby controlling the ON period or the OFF period of the switch. It will be.

  Here, in controlling the value of the first digital signal from the modulation circuit and outputting the second digital signal after the control, the control circuit outputs itself from N cycles to 1 cycle before the operation clock cycle. The value of the second digital signal thus detected is detected. If the values of the second digital signal from N cycles before to 1 cycle are all the same, the ON period or OFF period of the switch is N times or more of the operation clock period. The circuit outputs the value of the first digital signal input from the modulation circuit as it is.

  On the other hand, if any one of the values of the second digital signal output by itself from the previous N period to the previous one period is different, the ON period or OFF period of the switch is less than N times the operation clock period. Therefore, regardless of the value of the first digital signal input from the modulation circuit, the control circuit outputs the value of the second digital signal output by itself one cycle before.

  As described above, when the control circuit outputs the second digital signal, the control circuit determines the value of the second digital signal from the previous N period to the previous one period and outputs the second digital signal. The value is determined. As a result, the value of the second digital signal output from the control circuit continues to be the same value for at least N times the operation clock period, and the number of switching operations can be controlled.

  Here, in the conventional example, the control circuit is configured so that the same value continues for N times or more of the operation clock period with respect to the value of the ternary signal expressed by the two first digital signals from the modulation circuit. The ternary signal is controlled, and the number of times of switching in the switching circuit is controlled according to the values of the two second digital signals generated based on the control result.

  On the other hand, in the present invention, the control circuit is provided for each of the two first digital signals so that the same value continues for N times or more of the operation clock period with respect to the values of the two first digital signals from the modulation circuit. Independently, the number of switching of the switching circuit is controlled by controlling the value of the first digital signal and outputting the two second digital signals after the control.

  Thus, in the conventional switching frequency control, the value of the ternary signal output from the control circuit always continues the same value for N times or more of the operation clock cycle.

  On the other hand, in the switching frequency control according to the present invention, if the values of the two second digital signals output from the control circuit are N times or more of the operation clock cycle, the value of the ternary signal is changed to the operation clock cycle. It is not necessary that the same value continues for N times or more.

  A specific example will be described as follows. Here, the control circuit assumes that the switching frequency control is twice the operation clock cycle.

Further, when one of the two second digital signals is the second digital signal A and the other is the second digital signal B, the correspondence between the ternary signal value and the two second digital signal values Is
If the value of the ternary signal is “+1”, the second digital signal A is “H”, and the second digital signal B is “L”.
If the value of the ternary signal is “0”, the second digital signal A is “L”, and the second digital signal B is “L”.
If the value of the ternary signal is “−1”, the second digital signal A is “L” and the second digital signal B is “H”.

  For example, the value of the ternary signal input from the modulation circuit to the control circuit is “−1” for two cycles before, “0” for one cycle before, and “+1” for the current cycle. The value of the two second digital signals and the value of the ternary signal output from the control circuit when the current value “+1” from the modulation circuit is input are compared between the conventional example and the present invention.

  In the conventional example and the present invention, the values of the ternary signal two cycles before and one cycle before output from the control circuit are the values of the ternary signal input from the modulation circuit. ”And“ 0 ”are output as they are.

  First, in the conventional example, the value of the ternary signal output from the control circuit two cycles before is “−1”, and the value of the ternary signal output from the control circuit one cycle before is “0”. Yes, two cycles before and one cycle before, since different values are output, the control circuit outputs “0”, which is the value one cycle before.

  Next, in the present invention, when switching frequency control is performed, the above control is performed independently for each of the two first digital signals from the modulation circuit.

  First, looking at the second digital signal A, the value of the second digital signal A output from the control circuit two cycles before is “L”, and the value of the second digital signal A output from the control circuit one cycle before is shown. Is also “L”. Therefore, in the second digital signal A, since the value of the output second digital signal A two cycles before and one cycle before is the same, “H” corresponding to the value “+1” input from the modulation circuit is set. Output.

  On the other hand, when looking at the second digital signal B, the value of the second digital signal B output from the control circuit two cycles before is “H”, and the value of the second digital signal B output from the control circuit one cycle before is shown. Is “L”, the value of the second digital signal B output from the control circuit next is “L”. Here, when the values of the second digital signals A and B after the control are viewed, the second digital signal A is “H” and the second digital signal B is “L”. This is expressed as “+1”.

  Here, when the value of the ternary signal output from the control circuit in the conventional example and the present invention is compared, the value “+1” input from the modulation circuit is converted to “0” in the conventional example. In the present invention, the same value as “+1” input from the modulation circuit can be output.

  As described above, in the present invention, the switching number control is performed independently for each of the two first digital signals from the modulation circuit, so that in the conventional example, the value of the ternary signal from the modulation circuit is required. It is possible to prevent the above conversion.

  As a result, the control circuit controls the switching frequency of the switching circuit and improves the fidelity of the ternary signal to be output to the value of the ternary signal input from the modulation circuit. There is an effect of suppressing the decrease.

Furthermore, the digital amplifier according to the present invention is:
The differential signal output from the switching circuit is fed back to the modulation circuit.

  With the above configuration, a signal including noise generated in the modulation circuit, the control circuit, and the switching circuit is fed back to the modulation circuit.

  Here, the modulation circuit can extract a noise component included in the fed back signal from the signal fed back from the switching circuit, and can output the signal in the form of canceling out the noise component. This produces an effect of reducing noise in the output signal.

In the digital amplifier according to the present invention,
It is preferable to include a recording unit that records the values of the two digital signals output from the control circuit.

Furthermore, the digital amplifier according to the present invention is:
The switching circuit includes two signal lines for outputting the differential signal, and each switch in the switching circuit switches the two signal lines for outputting the differential signal to each other's signal line. Either the power supply voltage of the circuit is connected, or the GND of the switching circuit is connected to each signal line, and the value of the differential signal is set to zero.

  Here, when the power supply voltage of the switching circuit is connected to each other signal line and the GND of the switching circuit is connected to the two signal lines that output a differential signal, the switch in the switching circuit is turned ON. -The OFF state will be different.

  Therefore, by providing the above configuration, when the value of the differential signal to be output is “0”, the digital amplifier can select the switch state from one of two types. It is possible to select a switch state in which switch switching is reduced and output a differential signal value of “0”.

  As described above, the digital amplifier and the switching frequency control method according to the present invention include a control circuit that controls the value of the digital signal from the modulation circuit in the digital amplifier. For two digital signals, the value of the digital signal input from the modulation circuit is controlled independently for each digital signal, and the two digital signals whose values are controlled are output to the switching circuit. The switch in the switching circuit is connected to two digital signals output from the control circuit, and is switched on and off based on the digital signals. This makes it possible to prevent the ternary signal value from the modulation circuit from being converted more than necessary compared to the conventional switching frequency control.

  As a result, it is possible to control the number of times of switching in the switching circuit and to prevent the ternary signal value from the modulation circuit from being converted more than necessary.

  Embodiments according to the present invention will be described below with reference to the drawings.

(Configuration of ternary 1-bit amplifier)
First, the essence of the ternary 1-bit amplifier 1 according to the present embodiment will be described with reference to FIG.
FIG. 1 is a block diagram showing a configuration of a ternary 1-bit amplifier including a switching frequency control circuit according to the present embodiment.

  As shown in the figure, a ternary 1-bit amplifier 1 includes a ΔΣ modulation circuit 10, a switching circuit 20, an LPF 30, and a switching frequency control circuit 40 (corresponding to the control circuit described in the claims). Further, the ΔΣ modulation circuit 10 includes a ΔΣ modulation 1-bit signal generation circuit 11 and a quantizer 12. Furthermore, the switching frequency control circuit 40 includes a conversion unit 41a and a conversion unit 41b.

(Control operation of ternary 1-bit amplifier)
Hereinafter, control in the ternary 1-bit amplifier 1 will be described. An electrical signal from an input unit (not shown) is input to the ΔΣ modulation circuit 10. The input signal input to the ΔΣ modulation circuit 10 is sampled by the ΔΣ modulation 1-bit signal generation circuit 11 in units of operation clock periods, and the quantizer 12 quantizes the sampled data to generate a ternary signal. . Here, the ternary signal output from the quantizer 12 is expressed by two digital signals (corresponding to the first digital signal described in the claims).

  The electrical signal from the input unit (not shown) input to the ternary 1-bit amplifier 1 may be either an analog signal or a digital signal (PCM signal). When an analog signal is input by the ternary 1-bit amplifier 1, the analog signal input by the ΔΣ modulation circuit 10 is converted into a ternary signal, and when a digital signal is input by the ternary 1-bit amplifier 1, The PCM signal which is a digital signal input by the ΔΣ modulation circuit 10 is converted into a ternary signal.

  Next, in the switching number control circuit 40, the two digital signals representing the ternary signal from the quantizer 12 are individually input to the conversion units 41a and 41b. Each of the conversion units 41a and 41b controls the value of the digital signal from the quantizer 12 to be the same value by N times or more of the operation clock period (N is an integer of 2 or more). A detailed description of digital signal control in the conversion units 41a and 41b will be given later.

  Two digital signals (corresponding to the second digital signal described in the claims) controlled by the converters 41 a and 41 b are input to the switching circuit 20. The switching circuit 20 switches each of the switches 21a to 21d (see FIG. 2) in the switching circuit 20 on and off based on the two digital signals output from the conversion units 41a and 41b. By switching the switches 21a to 21d (see FIG. 2), the switching circuit 20 amplifies a voltage corresponding to the ternary signal expressed by the two digital signals and outputs it as a differential signal. In addition, since the signal output from the switching circuit 20 is a differential signal, it is output to LPF which is an output destination by two signal lines with which the switching circuit is provided.

  Further, the ternary 1-bit amplifier 1 in the present embodiment fades back the output signal from the switching circuit 20 to the ΔΣ modulation 1-bit signal generation circuit 11.

  As described above, by feeding back the signal from the switching circuit to the ΔΣ modulation 1-bit signal generation circuit 11, a signal including noise generated in the ΔΣ modulation circuit 10, the switching frequency control circuit 40, and the switching circuit 20 is converted into ΔΣ This is fed back to the modulation 1-bit signal generation circuit 11.

  Here, the ΔΣ modulation 1-bit signal generation circuit 11 extracts a noise component included in the fed-back signal from the fed-back signal from the switching circuit 20, and a 1-bit signal is quantized by canceling the noise component. In addition, the quantizer 12 can reduce noise in the output signal from the switching circuit 20 by outputting to the switching circuit 20 via the switching frequency control circuit 40.

(Configuration of switching circuit)
The configuration of the switching circuit 20 in the ternary 1-bit amplifier will be described below.
FIG. 2 is a schematic diagram showing the configuration of the switching circuit 20.

  As shown in the figure, the switching circuit 20 includes switches 21a to 21d. The switch 21a is a switch that connects the power supply voltage + V of the switching circuit 20 and the + side of the load 50, and the switch 21b The switch 21c is a switch for connecting the power supply voltage + V of the switching circuit 20 and the negative side of the load 50, the switch 21c is a switch for connecting the positive side of the load 50 and GND, and the switch 21d is connected to the negative side of the load 50. GND is a connection switch. The load 50 is an output unit (not shown) such as the LPF 30 and a speaker in FIG.

  The switching circuit 20 switches ON / OFF of the switch in the switching circuit 20 based on the two digital signals representing the ternary signal from the switching frequency control circuit 40, and “+ V” or “0” or “−” By applying the potential difference of “V” to two signal lines connected to the + side and the − side of the load 50, the ternary signal from the switching frequency control circuit 40 is amplified.

  The ternary signal input to the switching circuit 20 is expressed by two digital signals from the conversion units 41a and 41b in the switching frequency control circuit 40. The + side input shown in FIG. The digital signal from the unit 41a is input, and the digital signal from the conversion unit 41b is input to the negative side input.

  Further, since the switches 21a and 21c perform the ON and OFF operations of the switch based on the signals whose logics are inverted, when the switch 21a is ON, the switch 21c is OFF and the switch 21a is OFF. In this case, the switch 21c is turned on. Similarly, since the switches 21b and 21d perform the ON and OFF operations of the switches according to the signals whose logics are inverted, when the switch 21b is ON, the switch 21d is OFF and the switch 21b is OFF. The switch 21d is turned on.

Next, the states of the switches 21a to 21d in each of “+1”, “0”, and “−1”, which are the values of the ternary signals from the switching number control circuit 40, are shown in FIGS. ).
FIG. 3A is an explanatory diagram showing the states of the switches 21a to 21d when the output value from the switching number control circuit 40 is “+1”, and FIG. FIG. 3C is an explanatory diagram showing the states of the switches 21a to 21d when the output value from “1” is “−1”. FIGS. 3C and 3D show the output value from the switching frequency control circuit 40 being “0”. It is explanatory drawing which shows the state of switch 21a-21d at the time of becoming.

(Switch state at “+1”)
As shown in FIG. 3A, when the ternary signal from the switching frequency control circuit 40 is “+1”, in other words, the “H” signal is input to the + side input and the “L” signal is input to the − side input. Is inputted, the switch 21a is turned on, the switch 21c is turned off, the switch 21b is turned off, and the switch 21d is turned on. As a result, + V, which is the power supply voltage of the switching circuit, is connected to the + side of the load 50, and GND is connected to the − side of the load 50. That is, in the load 50, the potential on the + side has a potential difference of + V with respect to the potential on the − side.

(Switch status at "-1")
Further, as shown in FIG. 3B, when the ternary signal from the switching frequency control circuit 40 is “−1”, in other words, “L” for the + side input and “H” for the − side input. ”Is input, the switch 21a is turned OFF, the switch 21c is turned ON, the switch 21b is turned ON, and the switch 21d is turned OFF. As a result, + V, which is the power supply voltage of the switching amplifier circuit 20, is connected to the − side of the load 50, and GND is connected to the + side of the load 50. That is, in the load 50, the potential on the + side becomes a potential difference of −V with respect to the potential on the − side.

  Next, the states of the switches 21a to 21d when the output signal from the switching number control circuit 40 is “0” will be described.

  In the present embodiment, when the output signal from the switching frequency control circuit 40 is “0”, the two digital signals from the switching frequency limit circuit 40 representing “0” are both “L”. It is preferable to express either one of the case where the value is “H” or the case where both are “H”.

(Switch status at “0”)
In FIG. 3C, the ternary signal from the switching frequency control circuit 40 is “0”, and the values of the two digital signals from the switching frequency control circuit 40 representing this “0” are both “ In the case of “L”, the respective switches 21a to 21d are turned on and off.

  When two digital signals from the converters 41a and 41b are input as "L" to the + side input and the-side input, as shown in the figure, the switch 21a is turned OFF and the switch 21c is turned ON. 21b is turned OFF and the switch 21d is turned ON. As a result, both the + side and the − side of the load are connected to GND, and the potential difference between the + side and the − side of the load becomes zero.

  In FIG. 3D, the ternary signal from the switching frequency control circuit 40 is “0”, and the values of the two digital signals from the switching frequency control circuit 40 representing this “0” are both “ In the case of “H”, the ON / OFF states of the switches 21a to 21d are shown.

  When two digital signals from the converters 41a and 41b are input as "H" to the + side input and the-side input, as shown in the figure, the switch 21a is turned on and the switch 21c is turned off. 21b is turned on and the switch 21d is turned off. As a result, both the + side and the − side of the load are connected to + V, and the potential difference between the + side and the − side of the load becomes zero.

  As described above, based on the values “H” and “L” of the two digital signals from the conversion units 41a and 41b, the switches 21a to 21b are switched ON / OFF, and the switching circuit 20 outputs a ternary signal. Amplifying.

  In the switching circuit 20, the switches 21a to 21d, the power supply voltage, and the GND are connected by a single power supply voltage + V and GND shown in FIGS. 2 and 3A to 3D. 50 is preferably a balanced connection called a full bridge type or a BTL type, which is a connection method in which a voltage of + V to −V is applied. This balanced connection requires only one type of power supply voltage + V, and has an effect that the voltage use efficiency is good.

  The switches 21a to 21d may generally be power MOSFETs (power MOS field effect transistors), and are not limited to this as long as the devices match the switching speed of the switches.

(Configuration and operation of switching frequency control circuit 40)
Next, the configuration of the switching frequency control circuit 40 will be described with reference to FIG.
FIG. 4 is a block diagram showing the configuration of the switching frequency control circuit 40.

  As shown in the figure, the switching frequency control circuit 40 receives a digital signal from the quantizer 12 and outputs a signal to the switching circuit 20, and a conversion unit 41a and a conversion unit 41b. Are provided with a memory 42a and a memory 42b (corresponding to a recording unit described in the claims).

  Here, the conversion unit 41a and the conversion unit 41b are configured so that the ON period or the OFF period of each of the switches 21a to 21d is equal to or more than N times the operation clock period with respect to the two digital signals from the quantizer 12. In other words, the value of the digital signal is controlled independently for each digital signal so that the ON or OFF state of each switch 21a to 21d is maintained at least N times the operation clock cycle, and the switching circuit 20 Output to.

  As an example, the operation of the switching frequency control circuit 40 when the pulse width of the digital signal output to the switching circuit 20 is limited to at least twice the operation clock period will be described. In addition, in order to perform the same operation | movement with the conversion part 41a and the conversion part 41b, the conversion part 41a is demonstrated in the following example.

  The conversion unit 41a compares the value of the output signal from the conversion unit 41a one cycle before the operation clock with the value of the output signal from the conversion unit 41a two cycles before the operation clock. At this time, the value of the output signal one cycle before and the value of the output signal two cycles before are recorded in the memory 42a in FIG.

  Next, when the value of the output signal one cycle before and the value of the output signal two cycles before are the same, the conversion unit 41a outputs the value of the input signal from the quantizer 12. On the other hand, when the value of the output signal for the previous cycle is different from the value of the output signal for the previous cycle, the conversion unit 41a performs the above operation 1 regardless of the value of the signal input from the quantizer 12. The same value as the value of the output signal before the period is output. In this way, the switching frequency control circuit 40 controls the output signal so that the same value is output for two cycles of the operation clock.

Hereinafter, control of the value of the digital signal in the conversion unit 41a and the conversion unit 41b will be described using a specific example.
FIG. 5 is an explanatory diagram showing the relationship between the input signal from the quantizer 12 before control and the output signal to the switching circuit 20 after control in the converter 41a and the converter 41b.

In the figure, each of the times T1 to T14 is an operation clock cycle in the ΔΣ modulation circuit 10 and the switching frequency limit circuit 40. Note that the pulse width of the output signals output from the converters 41a and 41b is controlled to be at least twice the operation clock cycle. Further, since the input signal and the output signal are digital signals, the values of the input signal and the output signal are represented by “H” or “L” in FIG. Furthermore, the correspondence between the values “H” and “L” of the input signal and the output signal and the values “−1”, “0” and “+1” of the ternary signal expressed by two digital signals is as follows. It is as follows.
If the value of the ternary signal is “+1”, the digital signal corresponding to the conversion unit 41a is “H”, and the digital signal corresponding to the conversion unit 41b is “L”.
If the value of the ternary signal is “0”, the digital signal corresponding to the conversion unit 41a is “L”, and the digital signal corresponding to the conversion unit 41b is “L”.
If the value of the ternary signal is “−1”, the digital signal corresponding to the conversion unit 41a is “L”, and the digital signal corresponding to the conversion unit 41b is “H”.

  Referring to times T7 to T9 in the figure, the output value of the conversion unit 41b is “L” at T7 and “H” at T8. Therefore, although the input value of the conversion unit 41b is “L” at T9, the output value at one cycle before the operation clock is different from the output value two cycles before, so the conversion unit 41b changes the output value at T9. The output value is converted to the output value one cycle before, in other words, converted to “H”, which is the output value at T 8, and output to the switching circuit 20.

  On the other hand, in the conversion unit 41a, since the values of the output signals at T6 and T7 are both “L”, the conversion unit 41a does not need to control the value of the output signal at T9. Therefore, the conversion unit 41a outputs the value of the output signal from the conversion unit 41a to the switching circuit 20 as “L” which is the input signal of T9. As a result, at T9, the output of the conversion unit 41a is “L”, and the output of the conversion unit 41b is “H”. Therefore, the ternary value to be output with respect to the value “0” of the input ternary signal The value of the signal is converted to “−1”.

  Further, referring to times T2 to T4 in the figure, the output value of the conversion unit 41b is “H” at T2 and “L” at T3. Therefore, at T4, since the output value one cycle before the operation clock is different from the output value two cycles before, the conversion unit 41b sets the output value at T9 as “L”, which is the output value one cycle before, It is output to the switching circuit 20.

  In the conversion unit 41a, the values of the output signals at T2 and T3 are both “L”, so the conversion unit 41a does not need to control the value of the output signal at T9. Therefore, the conversion unit 41a outputs the value of the output signal from the conversion unit 41a to the switching circuit 20 as “H” which is the input signal of T9.

  What should be noted here is the value of the ternary signal of the output signal at T2 to T3. The value of the ternary signal at T2 is “−1”, the value of the ternary signal at T3 is “0”, and the value of the ternary signal at T4 is “+1”. . In the present embodiment, since the conversion unit 41a and the conversion unit 41b control the pulse width independently for each of the two digital signals from the quantizer 12, three values two cycles before (T2) are used. Even if the value of the signal of 3 is different from the value of the ternary signal of 1 cycle before (T3), the switching frequency control is performed with a value different from the value of the 3 values of signal of 1 cycle before (T3). The circuit 40 can output. As a result, as indicated by T4 in the figure, it is possible to output the same ternary signal value as the input signal while controlling the number of times of switching.

  Further, in the present embodiment, when the value of the ternary signal to be output is “0”, the output values of the conversion unit 41a and the conversion unit 41b can both be “H”.

  Referring to T12 to T14 in the figure, the output value of the conversion unit 41b is “L” at T12 and “H” at T13. Therefore, at T14, the input value of the conversion unit 41b is “L”, but since the output value of one cycle before the operation clock (T13) and the output value of two cycles before (T12) are different, the conversion unit 41b , The output value at T14 is converted into an output value one cycle before, in other words, converted to “H”, which is the output value at T13, and output to the switching circuit 20.

  On the other hand, in the conversion unit 41a, since the values of the output signals at T6 and T7 are both “L”, the conversion unit 41a does not need to control the value of the output signal at T9. Here, when “L”, which is the value of the input signal at T14, is output, the output value of the conversion unit 41b at T14 is “H”, so the value of the ternary signal output at T14 is “−”. 1 ”.

  Therefore, the conversion unit 41a outputs “H” based on the information of the input ternary signal value “0” and the output value “H” of the conversion unit 41b. Thereby, in T14, since both the conversion unit 41a and the conversion unit 41b output “H”, the switching number control circuit 20 converts the output value of the ternary signal into the input ternary signal. It is output as “0” which is the same as the value of.

(Comparison with conventional example)
Hereinafter, referring to FIG. 6, the switching number control of the conventional example and the switching number control of the present embodiment will be compared.
FIG. 6 shows a signal input to the switching circuit 40, an output signal to the switching circuit 20 of the conventional example, and an output signal to the switching circuit of the present embodiment at times T1 to T14 for each operation clock cycle. It is explanatory drawing which shows a relationship.

  In the figure, an example in which the number of times of switching is controlled so that the ON period or the OFF period of the switches 21a to 21d in the switching circuit 20 is twice or more the operation clock cycle.

  In the figure, the shaded portions include the values of the ternary signal input to the switching frequency control circuit 40 and the ternary signal output to the switching circuit 20 including the case of the conventional example and the present embodiment. Compared with the value of, the part which becomes a different value is shown.

  In the conventional example, the switching frequency control is performed based on a ternary signal. That is, the switching frequency control circuit 410 (see FIG. 10) performs switching frequency control so that the value of the input ternary signal is twice or more the operation clock cycle.

  Therefore, as shown in T2 to T3 in the figure, in the conventional example, the output value of the ternary signal at T2 is “−1”, and the output value of the ternary signal at T3 is “0”. Yes, the output value of the ternary signal at T4 is “0”. This is because the output value of the previous cycle (T3) is different from the output value of the previous cycle (T2), so the output value of the ternary signal at T4 is the output of the previous cycle (T3). The value is “0”. Therefore, by performing the switching frequency control, the value of the input ternary signal at T4 and the value of the output ternary signal are different.

  Furthermore, as shown in the figure, in the conventional example, when the value of the input ternary signal is compared with the value of the output ternary signal, the values at three locations T4, T8, and T14 are: It is converted into a different value by the switching number control circuit 410.

  On the other hand, in the present embodiment, when the value of the input ternary signal is compared with the value of the output ternary signal, the value at one location of T8 is changed to a different value depending on the switching frequency control circuit. It has been converted.

  As described above, the switching frequency control circuit 40 according to the present embodiment controls the pulse width of the digital signal independently for each of the two digital signals from the quantizer 12, thereby controlling the switching frequency. While performing the control, the number of times of converting and outputting the value of the ternary signal input from the quantizer 12 is reduced as compared with the conventional example.

  Thus, in the present invention, the ternary value from the quantizer 312 (see FIG. 10) in the conventional example is controlled by controlling the number of times of switching independently for every two digital signals from the quantizer 12. It is possible to prevent the conversion of the signal value of more than necessary.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  In the ternary 1-bit amplifier, the value of the digital signal is controlled independently for each of the two digital signals output from the modulation circuit. The present invention provides a digital amplifier that can prevent the value of a signal from being controlled more than necessary, and is used particularly in an audio device equipped with a digital amplifier and a device that outputs sound such as a mobile phone. It is possible.

FIG. 3 is a block diagram showing a configuration of a ternary 1-bit amplifier in the present embodiment. It is explanatory drawing which shows the structure of the switching circuit in this Embodiment. (A)-(d) is explanatory drawing which shows the state of the switch in a switching circuit with respect to the value of the input signal to a switching circuit in this Embodiment. It is a block diagram which shows the structure of the switching frequency control circuit in this Embodiment. It is explanatory drawing which shows the value of the input signal and output signal of a switching frequency control circuit in this Embodiment. It is explanatory drawing which shows the value of the output signal in a prior art example with respect to the value of the input signal of a switching frequency control circuit, and the value of the output signal in this Embodiment. It is a block diagram which shows the structure of 1 bit amplifier in a prior art example. It is a block diagram which shows the structure of 1 bit amplifier provided with the switching frequency control circuit in a prior art example. (A) is explanatory drawing which shows the input signal to the switching frequency control circuit in a prior art example, (b) is explanatory drawing which shows the output signal from the switching frequency control circuit in a prior art example, (c ) Is an explanatory diagram showing an operation clock signal. It is a block diagram which shows the structure of a ternary 1 bit amplifier provided with the switching frequency control circuit in a prior art example. It is explanatory drawing which shows the structure of the switching circuit in a prior art example. It is explanatory drawing which shows the ternary signal from a quantizer, the output signal from a switching frequency control circuit, and the state of the switch in a switching circuit in a prior art example.

Explanation of symbols

1 3-value 1-bit amplifier (digital amplifier)
10 ΔΣ modulation circuit (modulation circuit)
20 switching circuit 21a switch 21b switch 21c switch 21d switch 40 switching frequency control circuit (control circuit)
41a conversion unit 41b conversion unit 42a memory (recording unit)
42b Memory (recording unit)

Claims (6)

A modulation circuit that modulates an external electric signal into a ternary signal based on an operation clock, expresses the ternary signal by two first digital signals, and outputs the two first digital signals;
A control circuit for setting the values of the two first digital signals from the modulation circuit based on a predetermined rule, and outputting the two second digital signals after the setting;
Based on the two second digital signals whose values are set by the control circuit, a plurality of switches for switching between ON and OFF are provided, corresponding to a ternary signal expressed by the two second digital signals from the control circuit. A switching circuit that amplifies the voltage and outputs it as a differential signal,
The predetermined rule is that the second rule from the control circuit is N cycles before (N is an integer of 2 or more) to one cycle before the operation clock when the second digital signal is output from the control circuit. When all the values of the digital signals are the same, the control circuit sets and outputs the value of the first digital signal from the modulation circuit as the value of the second digital signal at the time of the output, and
When any one of the values of the second digital signal from the control circuit is different from N cycles to 1 cycle before the operation clock with respect to the output of the second digital signal from the control circuit, The control circuit is determined to set and output the value of the second digital signal from the control circuit one cycle before the operation clock as the value of the second digital signal at the time of the output,
The digital amplifier, wherein the control circuit sets the value of the second digital signal independently for each of the two first digital signals input from the modulation circuit to the control circuit.   The digital amplifier according to claim 1, wherein the differential signal output from the switching circuit is fed back to the modulation circuit.   3. The digital amplifier according to claim 1, further comprising a recording unit in which values of two digital signals output from the control circuit are recorded. The switching circuit includes two signal lines for outputting the differential signal,
With respect to the two signal lines that output the differential signal by each switch in the switching circuit,
Connect the power supply voltage of the switching circuit to the two signal lines, or
4. The digital amplifier according to claim 1, wherein a value of the differential signal is set to zero by connecting a GND of a switching circuit to the two signal lines. 5. A modulation circuit that modulates an external electric signal into a ternary signal based on an operation clock, expresses the ternary signal by two first digital signals, and outputs the two first digital signals;
A control circuit for setting the values of the two first digital signals from the modulation circuit based on a predetermined rule, and outputting the two second digital signals after the setting;
Based on the two second digital signals whose values are set by the control circuit, a plurality of switches for switching between ON and OFF are provided, corresponding to a ternary signal expressed by the two second digital signals from the control circuit. In a switching number control method in a switching amplifier provided with a switching circuit that amplifies a voltage and outputs it as a differential signal,
The predetermined rule is that the second rule from the control circuit is N cycles before (N is an integer of 2 or more) to one cycle before the operation clock when the second digital signal is output from the control circuit. When all the values of the digital signals are the same, the control circuit sets and outputs the value of the first digital signal from the modulation circuit as the value of the second digital signal at the time of the output, and
When any one of the values of the second digital signal from the control circuit is different from N cycles to 1 cycle before the operation clock with respect to the output of the second digital signal from the control circuit, The control circuit is determined to set and output the value of the second digital signal from the control circuit one cycle before the operation clock as the value of the second digital signal at the time of the output,
The control circuit sets the value of the second digital signal independently for each of the two first digital signals input from the modulation circuit to the control circuit. Method.   The predetermined rule is that the values of the second digital signal from the control circuit are the same from two cycles to one cycle before the operation clock when the second digital signal is output from the control circuit. In some cases, the control circuit sets and outputs the value of the first digital signal from the modulation circuit as the value of the second digital signal at the time of the output, and
  When any one of the values of the second digital signal from the control circuit is different from two cycles to one cycle before the operation clock with respect to the output of the second digital signal from the control circuit, The control circuit is configured to set and output the value of the second digital signal from the control circuit one cycle before the operation clock as the value of the second digital signal at the time of the output. The digital amplifier according to any one of claims 1 to 4.

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