JP3445177B2 - Switching amplifier using ΔΣ modulation - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching amplifier which is preferably implemented in connection with an acoustic signal and which uses .DELTA..SIGMA. Modulation capable of amplifying the acoustic signal and the like with high efficiency.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing an electrical configuration of a typical conventional switching amplifier 1 using ΔΣ modulation. An analog input voice signal from the analog signal source 2 is input to the switching amplifier 1 and first, Δ
The Σ modulation circuit 3 converts into a 1-bit digital signal.

The ΔΣ modulation circuit 3 is shown in FIG.
As shown in FIG. 5, an integration configured by a cascade-connected high-order integrator that sequentially integrates the input audio signal, and an adder that adds outputs from each integrator to each other. An adder / adder group 4, and a quantizer 5 for quantizing the output from the adder of the integrator / adder group 4 into a 1-bit signal,
A delay device 6 for delaying the 1-bit signal from the quantizer 5 by 1 bit, and a digital / analog converter 7 for digital / analog converting the 1-bit signal from the delay device 6.
And an adder 8 for subtracting an audio signal fed back from the digital / analog converter 7 from an input audio signal from the analog signal source 2. Thus, feedback control is realized so that the 1-bit signal from the quantizer 5 corresponds to the input analog voice signal.

The 1-bit signal from the quantizer 5 is given to a constant voltage switch 9, and a pulse signal of a predetermined constant voltage corresponding to the created 1-bit signal is converted into an analog audio signal by a low-pass filter 10. After being demodulated, it is output and is sonicated by the speaker 11.

The switching amplifier 1 configured as described above does not use the linear region (unsaturation region) of the semiconductor power amplifying element unlike the conventional amplifier, but uses the semiconductor power used for the constant voltage switch 9. Since the amplifying element is used in the non-linear region (saturation region), it has an advantage that power can be amplified with extremely high efficiency.

[0006]

On the other hand, the 1-bit signal obtained by the ΔΣ modulation has an effective frequency band by appropriately selecting the coefficients of the integrator and the adder in the integrator / adder group 4. It has an excellent feature that the frequency characteristic can be set according to the sound source, such as widening or widening the dynamic range. Therefore, CD (compact disc) and DVD
In the new standard of (digital video disc), this 1
Bit signals have been adopted, and commercialization is about to begin from next year.

Therefore, the above switching amplifier 1
It is desired to input a 1-bit signal directly to the
Even if the analog converter 7 is deleted and the 1-bit signal is simply fed back to the adder 8, the rising or falling timing of the fed-back 1-bit signal,
There is a problem that the rising or falling timing of the input audio signal from the signal source and the sampling timing of the integrator / adder group 4 do not match each other, and normal operation cannot be performed.

An object of the present invention is to provide a switching amplifier using ΔΣ modulation which can perform a normal operation with respect to a 1-bit signal input.

[0009]

Means for Solving the Problems Δ according to the invention of claim 1
In a switching amplifier using Σ modulation, a ΔΣ modulation circuit performs ΔΣ modulation on an input signal, the switching circuit switches a predetermined constant voltage from a power supply in response to the modulation signal, and the switching output is converted to analog by a low pass filter. In the switching amplifier using the ΔΣ modulation for outputting as a 1-bit signal, the Δ signal is output in response to a clock signal from the input signal source.
A timing control circuit that generates a timing signal that defines the operation timing of the Σ modulation circuit and the switching circuit, a feedback loop that feeds back the output signal of the switching circuit to an adder at the input stage of the ΔΣ modulation circuit, and the ΔΣ modulation circuit. Input 1 intervening on the front side
A matching circuit for inputting a unit pulse, whose time axis is defined by the timing signal, to the ΔΣ modulation circuit corresponding to the bit signal is included.

According to the above configuration, the switching amplifier receives a 1-bit signal as an input signal to be ΔΣ-modulated such as a voice signal, and is provided with a clock input terminal in accordance with the 1-bit signal. The clock signal from the source is input to the timing control circuit from this clock input terminal. The timing signal generated by the timing control circuit regulates the sampling timing of the integrator / adder group and the quantizer in the ΔΣ modulation circuit, and also turns ON / O the switching circuit.
FF timing is defined. By this, the ΔΣ
From the output side of the quantizer to the adder at the input stage of the modulation circuit,
Alternatively, the timing of the feedback signal given from the output side of the switching circuit via the attenuator is also defined.

On the other hand, the input 1-bit signal is also generated by the matching circuit into an accurate unit pulse whose time axis is defined in response to the timing signal. The timing of the feedback signal is the same as that of the feedback signal, and a normal operation as a switching amplifier can be realized for a 1-bit signal input.

A switching amplifier using ΔΣ modulation according to a second aspect of the present invention comprises noise level detecting means for detecting a quantization noise level of the input 1-bit signal,
A quantization noise level by the ΔΣ modulation circuit is stored in advance for each combination of a plurality of types of coefficients in the ΔΣ modulation circuit, and within a desired dynamic range in response to the detection result of the noise level detection means. And a coefficient selecting means for selecting a combination of coefficients in the ΔΣ modulation circuit so that the quantization noise level of the ΔΣ modulation circuit becomes lower than the quantization noise level of the input 1-bit signal. .

According to the above configuration, as described in claim 1, by making the input signal a 1-bit signal, each of the input 1-bit signal and the switching amplifier has a quantization noise characteristic. It will be. As described above, it is possible to change this quantization noise characteristic by changing the coefficient of the integrator and the adder in the ΔΣ modulation circuit, and the coefficient selecting means can change the coefficient within the desired dynamic range. The combination of the coefficients is selected so that the quantization noise level on the switching amplifier side becomes lower than the quantization noise level of the input 1-bit signal.

That is, when the frequency at which the quantization noise level has a peak value, for example, V1 up to a desired frequency band of the input 1-bit signal is F1, for example, the dynamic range is a level defined by the peak value V1. When a peak value of the quantization noise level, for example, V2, appears at a frequency outside the desired frequency band of the input 1-bit signal, for example, F2, even if the peak value V2 is exceeded on the switching amplifier side, The combination of the coefficients is selected so as not to exceed the level defined by the peak value V1 within the desired frequency band.

Therefore, within the desired dynamic range, the quantization noise level on the switching amplifier side does not exceed the quantization noise level of the input 1-bit signal,
At least, the dynamic range of the input 1-bit signal can be secured.

Furthermore, in a switching amplifier using ΔΣ modulation according to the invention of claim 3, the matching circuit includes a capacitor, as shown in FIG. 3, for example.
A constant voltage source, a first switch that connects the capacitor to the constant voltage source in the first half cycle of the input 1-bit signal, and a positive and negative sign of the capacitor in the latter half cycle of the input 1-bit signal. A second switch connecting terminals to respective positive and negative output lines, and selectively driven in response to the input 1-bit signal, the positive and negative output lines serving as a pair of output terminals, one polarity or the other polarity. And a third switch connected with the unit switch, the integral value of the unit pulse is an oscillation limit with respect to the integral value of the feedback value by the feedback loop that is subtracted in the adder of the input stage in the ΔΣ modulation circuit. It is characterized in that it is smaller by a predetermined ratio determined by.

According to the above configuration, the capacitor is accurately charged to the predetermined voltage by the constant voltage source in the first half cycle of the input 1-bit signal, and this voltage is the second half cycle. In addition, one polarity or the other polarity is output between the pair of output terminals. That is, for example, when the voltage of the constant voltage source is + 5V, + 5V or -5V is output to the output terminal. Therefore, the accurate unit pulse is output from the output terminal.

The integral value of the unit pulse is adjusted by an attenuator or the like interposed in the feedback loop so that it becomes smaller by a predetermined ratio with respect to the integral value of the feedback value. Therefore, the integrator in the ΔΣ modulation circuit is adjusted. -It is possible to prevent oscillation due to excessive input to the adder group.

Further, in the switching amplifier using the ΔΣ modulation according to the invention of claim 4, the timing control circuit receives the clock signal from the input signal source and removes a jitter component, and the PLL circuit. PL
The clock signal includes a multiplier that forms an L loop and that makes the frequency of the output signal of the PLL circuit a predetermined integer multiple, and a phase adjuster that regulates the switching timing of the output from the multiplier. It is characterized by generating a timing signal having a frequency that is an integral multiple of.

According to the above arrangement, the PLL circuit first removes the jitter component from the clock signal. The P
The multiplier oscillates a signal of a predetermined integer multiple with respect to the output signal of the LL circuit, and the PLL circuit has a frequency divider corresponding to the reciprocal of the multiplier, and the PLL thus formed. From the loop, a signal having a constant wavelength and an integral multiple of the clock signal is output. The timing of this signal is adjusted by the phase adjuster, and the signal is output as the timing signal. Thus
Oversampling can be realized on the ΔΣ modulation circuit side without impairing the accuracy of the input 1-bit signal, and a band wider than the transmission band of the input 1-bit signal can be secured.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing an electrical configuration of a switching amplifier 21 according to an embodiment of the present invention.
The switching amplifier 21 of the present invention includes a 1-bit signal source 2
The 1-bit signal from 2 can be directly input. Therefore, the 1-bit signal source 22 outputs the 1-bit signal and the clock signal used to generate the 1-bit signal. It In this switching amplifier 21, the ΔΣ modulation circuit 23 comprises a constant voltage switch 24, and in response to the 1-bit signal obtained by the quantizer 35, the constant voltage switch 2
7 is similar to the switching amplifier 1 shown in FIG. 7 described above in that a predetermined constant voltage from the power source 4 is switched, the switching output is converted into an analog audio signal by the low-pass filter 25, and the converted sound is output from the speaker 26. .

The clock signal is input to the timing control circuit 31, which will be described later.
By this, a timing signal is generated which is a predetermined integer multiple of the clock signal and is stabilized in a constant cycle. On the other hand, the 1-bit signal is input to the matching circuit 32. In the matching circuit 32, the time axis is defined by the timing signal as described later,
The input 1-bit signal is converted into the unit pulse of the predetermined integer multiple corresponding to the high level or the low level, and ΔΣ
It is given to the modulation circuit 23.

In the ΔΣ modulation circuit 23, the unit pulse is applied to an integrator / adder group 34 after a feedback signal, which will be described later, is subtracted in the adder 33. The integrator / adder group 34 is composed of, for example, an integrator and an adder using a switched capacitor as disclosed in Japanese Patent Application No. 9-266981 previously proposed by the applicant of the present application. Is added to the quantizer 35.
Is quantized by 1 bit at. The operation timing of the switches in the integrator / adder group 34, that is, the sampling timing and the sampling timing of the quantizer 35 are defined by the timing signal.

A predetermined small amplitude from the quantizer 35, for example, a 1-bit signal changing between 0V and 5V is input to the constant voltage switch 24, and a high voltage from the power source, for example, 100V, causes a large amplitude signal. Is converted to the low-pass filter 25. The constant voltage switch 24
Is also provided as a feedback signal to the adder 33 via an attenuator 36.

FIG. 2 is a block diagram showing an example of the structure of the timing control circuit 31. The timing control circuit 31 includes a PLL circuit 41, a frequency doubler 42, and a phase adjuster 43. The PLL circuit 41 and the frequency multiplier 42 form a PLL loop, and the frequency multiplier 42 is P
In response to the control voltage from the LL circuit 41, a signal having a frequency that is a predetermined integral multiple of the clock signal from the 1-bit signal source 22 is oscillated. This oscillation signal is fed back to the PLL circuit 41, divided by a frequency divider in the PLL circuit 41, and phase-compared with the clock signal.

Therefore, the oscillation signal of the frequency divider 42 becomes a signal in which the jitter component is removed from the clock signal and which is the predetermined integral multiple of the clock signal. This frequency divider 42
The oscillating signal is subjected to phase adjustment in the phase adjuster 43, and the matching circuit 32,
It is given to the integrator / adder group 34, the quantizer 35, and the constant voltage switch 24. Therefore, the timing signal becomes a clock signal from the 1-bit signal source, that is, a signal of a predetermined integral multiple of the 1-bit signal without impairing the accuracy of the 1-bit signal. Will be sampled,
A wider transmission band is ensured in the switching amplifier 21 than the transmission band of the bit signal.

FIG. 3 is a block diagram showing an example of the configuration of the matching circuit 32. This matching circuit 32
Is realized by a switched capacitor, and both terminals of the capacitor C are connected to the first switches S11, S12.
Are connected to input terminals P11 and P12, respectively. A predetermined voltage, for example, 5V is applied from the constant voltage source 44 to the input terminals P11 and P12. Both terminals of the capacitor C also have a second switch S2
Positive and negative output lines φ via 1 and S22, respectively
1 and φ2.

The high-level output line φ1 is selectively connected to the output terminals P21 and P22 via the third switches S311 and S321, respectively. Similarly, the output line φ2 on the low level side is connected to the third switch S32.
2, S312 through output terminals P21 and P2, respectively.
2 is selectively connected.

The switches S11, S12 and the switches S21, S22 are operated in opposite phase with respect to the timing signal by the inverter B1.
The operation pattern is shown in FIG. 3 as “1”,
It is indicated by "2". In addition, switches S311 and S312,
With respect to the switches S321 and S322, the inverter B2 operates in opposite phase with respect to the 1-bit signal, and the operation patterns thereof are shown by "H" and "L".

FIG. 4 is a timing chart for explaining the operation of the matching circuit 32 configured as described above. In FIG. 4, for simplification of description,
Although the timing signal is assumed to have a frequency equal to that of the clock signal from the 1-bit signal source 22, the above-mentioned oversampling actually causes the switches S11, S12; S21, S22 within the cycle of the 1-bit signal.
Will perform the ON / OFF operation of the predetermined integral multiple.

As shown in FIG. 4, when the timing signal and the clock signal have the same frequency,
In the first half cycle of the input 1-bit signal, for example, the switches S11 and S12 are turned on and the switches S21 and S22 are turned on.
Is turned off, and in the latter half cycle, the switch S11,
S12 turns off, and switches S21 and S22 turn on.

On the other hand, when the input 1-bit signal is at high level, the switches S311 and S312 are turned on, the switches S321 and S322 are turned off, and the output terminal P21.
Is connected to the output line φ1 on the high level side, and the output terminal P22 is connected to the output line φ2 on the low level side.
On the other hand, when the input 1-bit signal is at the low level, the switches S311 and S312 are turned off, the switches S321 and S322 are turned on, the output terminal P21 is connected to the output line φ2 on the low level side, and the output terminal P2.
2 is connected to the output line φ1 on the high level side.

Therefore, in the first half cycle of the input 1-bit signal, the switches S11 and S12 are turned on, and the capacitor C is charged to 5V by the constant voltage source 44. At this time, the switches S21 and S22 are turned off.
The output voltage Vout between the output terminals P21 and P22 is 0V due to FF.

On the other hand, in the latter half cycle of the input 1-bit signal, when the input 1-bit signal is at the high level, the output voltage Vout becomes + 5V,
-5V when the input 1-bit signal is low level
Becomes In this way, from the matching circuit 32,
In synchronism with the timing signal, the unit pulse whose integrated value of the crest value and the pulse width is constant is a 1-bit signal output V
It is output as out.

The feedback signal is subtracted from the output Vout in the adder 33.
Here, with respect to the output Vout having an amplitude of ± 5 V, the output from the constant voltage switch 24 having an amplitude of ± 100 V is attenuated by the attenuator 36 to be the feedback signal. As for the attenuation rate of the attenuator 36, the peak value and integrated value of the pulse width in the feedback signal are
It is selected to be larger than the peak value and the integrated value of the pulse width of the output Vout at a predetermined ratio, and the ratio is determined by the oscillation limit of the integrator / adder group 34. In this way, the integrated value of the feedback signal becomes larger than the integrated value of the output Vout of the 1-bit signal from the matching circuit 32, so that the oscillation is suppressed.

Referring to FIG. 1, the 1-bit signal and clock signal from 1-bit signal source 22 are also applied to noise level detection circuit 37. On the other hand, a preset coefficient unit 38 is provided in association with the integrator / adder group 34, and a plurality of types of coefficient groups a of each integrator and adder stored in the preset coefficient unit 38 are provided. , B, c are selectively set to corresponding integrators and adders in the integrator / adder group 34 via the switch 39 in response to the switching signal from the noise level detection circuit 37. .

Each coefficient group a, b, c has an oscillation limit value, that is, a value that defines the upper limit value of the level in the transmission area, noise, that is, a value that defines the lower limit value of the level in the transmission area, and the effective frequency. It is predetermined and stored in the preset coefficient unit 38 depending on how much weight is assigned to which parameter among the respective parameters of the band, that is, the frequency band in which transmission is possible.

FIG. 5 is a block diagram showing an example of the configuration of the noise level detection circuit 37. The input 1-bit signal is sampled in the latch unit 45 in synchronization with the clock signal, and in the frequency analysis unit 46, the sampled binary data is subjected to a frequency spectrum in real time by, for example, FFT (Fast Fourier Transform). Is extracted.

The minimum value holding unit 47 separates the changing transmission signal component and the unchanged quantization noise component by holding the minimum value. That is, the minimum value in each held spectrum is determined as the quantization noise floor component.

The noise distribution judging unit 48 judges the quantization noise distribution from the hold value of the minimum value holding unit 47,
The noise level in the transmission area, that is, the dynamic range and the effective frequency band are estimated. On the other hand, in the noise distribution determination unit 48, the quantization noise distribution on the switching amplifier 21 side when the coefficient groups a, b, and c preset in the preset coefficient unit 38 are set in advance. The coefficient is set so that the noise floor on the switching amplifier 21 side does not protrude within the dynamic range on the input 1-bit signal side.

That is, the coefficient group that has been set in the integrator / adder group 34 up to that point, for example, a is the coefficient group with emphasis on the effective frequency band, and the quantization noise level of the switching amplifier 21 is as shown in FIG. 6 (a). As shown, when the effective frequency band F1 = 20 kHz and the dynamic range D1 = −90 dB in the effective frequency band F1,
If the quantization noise level of the input 1-bit signal is, for example, a setting that emphasizes the dynamic range, and the effective frequency band F2 = 15 kHz and the dynamic range D2 = 100 dB as shown in FIG. Quantization noise floor of signal and switching amplifier 21
, And the higher value of both becomes the quantization noise distribution of the output acoustic signal, and as shown in FIG. 6C, both the effective frequency band and the dynamic range are impaired. Will end up.

On the other hand, by switching the coefficient group to, for example, b, the effective frequency band F3 and the dynamic range D3 are respectively changed to the effective frequency band F1 and the dynamic range D as shown in FIG. 6 (d).
It is ensured to be equal to 1 and is changed so that the quantization noise is distributed in the remaining area.

As described above, in the switching amplifier 21 according to the present invention, first, the clock signal is taken in from the 1-bit signal source 22 in response to converting the input signal into 1-bit signal,
Since the sampling timings of the matching circuit 32, the integrator / adder group 34, and the quantizer 35 are defined based on the timing signal created by the timing control circuit 31, and the switching operation of the constant voltage switch 24 is controlled, It is possible to directly input a 1-bit signal reproduced from a CD, a DVD, or the like to perform ΔΣ modulation.

Further, the timing control circuit 31 generates a timing signal having a frequency of a predetermined integral multiple synchronized with the clock signal, so that the input 1
Implements oversampling of bit signals and
A sufficient margin can be provided for the effective frequency band and the dynamic range on the switching amplifier 21 side with respect to the transmission frequency band and the dynamic range of the bit signal.

Furthermore, the integral value of the feedback signal from the attenuator 36 is increased by a predetermined ratio with respect to the integral value of the output Vout of the unit pulse created by the matching circuit 32, and the feedback subtraction value is made larger than the input signal. Since the size is increased, it is possible to prevent oscillation due to excessive input to the integrator / adder group 34.

Furthermore, the noise level detection circuit 37 detects the quantization noise floor of the input 1-bit signal, and the integrator / adder group 34 is arranged so that the noise floor on the switching amplifier 21 side does not protrude within the dynamic range. Since the coefficients are switched in (1), the dynamic range of the input 1-bit signal can be secured even when the above-mentioned oversampling is not performed.

[0048]

As described above, in the switching amplifier using the ΔΣ modulation according to the present invention, the ΔΣ modulation circuit switches the constant voltage by the modulated signal obtained by the ΔΣ modulation of the input signal, and the switching is performed. In a switching amplifier using ΔΣ modulation in which an output is converted into an analog signal by a low-pass filter and then output, in order to convert the input signal into a 1-bit signal, a clock signal used for generating the 1-bit signal is taken in. In response to the timing signal generated based on the clock signal, the matching circuit generates an accurate unit pulse whose time axis is defined from the input 1-bit signal, and ΔΣ in response to the unit pulse in response to the timing signal. Adds the feedback signals obtained by operating the integrator / adder group and the quantizer in the modulation circuit

Therefore, the timing of the unit pulse and the timing of the feedback signal match, and a normal operation as a switching amplifier can be realized for a 1-bit signal input.

Further, as described above, the switching amplifier using the ΔΣ modulation according to the invention of claim 2 detects the quantization noise level of the input 1-bit signal, and within the desired dynamic range, the switching amplifier side The combination of the coefficients of the integrator and the adder in the ΔΣ modulation circuit is selected so that the quantization noise level becomes lower than the quantization noise level of the input 1-bit signal.

Therefore, within the desired dynamic range, the quantization noise level on the switching amplifier side does not exceed the quantization noise level of the input 1-bit signal, and at least the dynamic range of the input 1-bit signal is secured. You can

Further, in the switching amplifier using the ΔΣ modulation according to the third aspect of the present invention, as described above, for example, the matching circuit, the capacitor, the constant voltage source, and the first half of the input 1-bit signal are used. A first switch that connects the capacitor to the constant voltage source in a cycle, and a second switch that connects the positive and negative terminals of the capacitor to the positive and negative output lines in the latter half cycle of the input 1-bit signal. , Selectively driven in response to the input 1-bit signal, the positive and negative output lines to a pair of output terminals,
A third switch that is connected with one polarity or the other polarity is provided so that an accurate unit pulse is output, and the integrated value of the unit pulse is used as the integrated value of the input stage of the ΔΣ modulation circuit. The integrated value of the feedback value subtracted in the adder is reduced by a predetermined ratio determined by the oscillation limit.

Therefore, oscillation due to excessive input to the integrator / adder group in the ΔΣ modulation circuit can be prevented.

Further, in the switching amplifier using the ΔΣ modulation according to the invention of claim 4, as described above, the timing control circuit is a PLL circuit which takes in a clock signal from the input signal source and removes a jitter component. , PL
An L circuit and a PLL loop, and a multiplier that makes the frequency of the output signal of the PLL circuit a predetermined integer multiple; and a phase adjuster that defines the switching timing of the output from the multiplier, A timing signal having a frequency that is an integral multiple of the clock signal is generated.

Therefore, oversampling can be realized on the ΔΣ modulation circuit side without impairing the accuracy of the input 1-bit signal, and a band wider than the transmission band of the input 1-bit signal can be secured.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a switching amplifier using ΔΣ modulation according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a timing control circuit in the switching amplifier shown in FIG.

FIG. 3 is a block diagram showing a configuration example of a matching circuit in the switching amplifier shown in FIG.

FIG. 4 is a timing chart for explaining the operation of the matching circuit shown in FIG.

5 is a block diagram showing a configuration example of a noise level detection circuit in the switching amplifier shown in FIG.

6 is a waveform diagram for explaining the operation of the noise level detection circuit shown in FIG.

FIG. 7 is a block diagram showing an electrical configuration of a typical conventional switching amplifier using ΔΣ modulation.

[Explanation of symbols]

21 switching amplifier 22 1-bit signal source 23 ΔΣ modulation circuit 24 constant voltage switch (switching circuit) 25 low-pass filter 26 speaker 31 timing control circuit 32 matching circuit 33 adder 34 integrator / adder group 35 quantizer 36 attenuator (feedback) Loop) 37 Noise level detection circuit (noise level detection means) 38 Preset coefficient unit (coefficient selection means) 39 Switch (coefficient selection means) 41 PLL circuit 42 Frequency multiplier 43 Phase adjuster 44 Constant voltage source 45 Latch unit 46 Frequency analysis Part 47 Minimum value hold part 48 Noise distribution determination part C Capacitor S11, S12 Switch (first switch) S21, S22 switch (second switch) S311, S312; S321, S322 switch (third switch) φ1, φ2 Power line

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03F 3/217 H03M 3/02

Claims (4)

(57) [Claims] 1. A .DELTA..SIGMA. Modulation circuit .DELTA..SIGMA. Modulates an input signal, and in response to the modulation signal, a switching circuit switches a predetermined constant voltage from a power supply, and the switching output is analog-converted by a low-pass filter and output. In a switching amplifier using ΔΣ modulation, the input signal is a 1-bit signal, and a timing control circuit that responds to a clock signal from an input signal source and generates a timing signal that defines the operation timing of the ΔΣ modulation circuit and the switching circuit. A feedback loop for feeding back the output signal of the switching circuit to an adder at the input stage of the ΔΣ modulation circuit; and a feedback loop interposed in front of the ΔΣ modulation circuit and corresponding to the input 1-bit signal by the timing signal. Input a unit pulse whose axis is specified to the ΔΣ modulation circuit A switching amplifier using delta-sigma modulation, which comprises: 2. A noise level detecting means for detecting a quantization noise level of the input 1-bit signal, and a quantization noise level by the ΔΣ modulation circuit is previously set for each combination of plural kinds of coefficients in the ΔΣ modulation circuit. In response to the detection result of the noise level detecting means, the quantization noise level by the ΔΣ modulation circuit circuit becomes smaller than the quantization noise level of the input 1-bit signal within a desired dynamic range. And the Δ
The Δ according to claim 1, further comprising a coefficient selecting unit that selects a combination of coefficients in the Σ modulation circuit.
Switching amplifier using Σ modulation. 3. The integral value of the unit pulse is smaller than the integral value of the feedback value by the feedback loop subtracted in the adder at the input stage of the ΔΣ modulation circuit by a predetermined ratio determined by the oscillation limit. A switching amplifier using the ΔΣ modulation according to claim 1 or 2. 4. The timing control circuit forms a PLL loop that takes in a clock signal from the input signal source and removes a jitter component, forms a PLL loop with the PLL circuit, and presets the frequency of the output signal of the PLL circuit. And a phase adjuster that defines the switching timing of the output from the multiplier, and generates a timing signal having a frequency that is an integral multiple of the clock signal. A switching amplifier using the ΔΣ modulation according to claim 1.