JPH11261843A - Display controller and control method for display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display controller capable of displaying appropriate images at a display device from video signals in which the waveform of synchronizing signals is disturbed by special reproduction or the like. SOLUTION: A VCO part 12 generates internal clock signals from horizontal synchronizing signals H inputted through a PLL part 11 and supplies them to a horizontal counter 15. A horizontal decoder 14 generates control signals and internal horizontal synchronizing signals corresponding to the counted number of the horizontal counter 15. A reset control part 22 matches synchronization with composite synchronizing signals CSY and supplies reset signals to the horizontal counter 15 at the time of detecting the step-out of the composite synchronizing signals CSY inputted through a noise filter and the internal horizontal synchronizing signals supplied from the horizontal decoder 14. The horizontal decoder 14 generates the control signals synchronized with the composite synchronizing signals CSY after the horizontal counter 15 is reset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device and a display control method capable of displaying an appropriate image on a display device from a video signal whose waveform of a synchronization signal is disturbed by special reproduction or the like.

[0002]

2. Description of the Related Art A conventional LC for monitoring a video camera or the like.
When a D (liquid crystal display) controller displays an image reproduced by the video reproduction unit on the LCD, the R
The control signal is generated by processing the synchronization signal supplied from the GB decoder or the like, and is supplied to the LCD drive unit. Conventional LCD
The manner in which an image is displayed on the LCD in the controller and its peripheral circuits will be described below.

[0003] A video reproducing section reads video information recorded on a video tape via a video head, reproduces a video signal from the video information, and supplies the video signal to an RGB decoder.
The RGB decoder receives the video signal reproduced by the video reproduction unit, and separates the video signal into a color signal and a composite synchronization signal. The RGB decoder generates an RGB signal from the separated color signal and supplies it to the inverting amplifier, generates a horizontal synchronization signal and a vertical synchronization signal from the composite synchronization signal, and supplies them to the LCD controller.

As shown in FIG. 7, an LCD controller includes a PLL (Phase Locked Loop) unit 101 and a VCO
(Voltage Controlled Oscillator) Unit 102 and Horizontal Decoder 103
, Horizontal counter 104, dot clock generator 10
5, a synchronization control unit 106, a vertical decoder 107, a vertical counter 108, and an FRP (frame pulse signal) generating unit 109.

The PLL section 101 receives a horizontal synchronizing signal H from the RGB decoder, and receives an internal horizontal pulse PH from the horizontal decoder 103. The PLL unit 101 supplies the received internal horizontal pulse PH to the VCO unit 102 in phase with the horizontal synchronization signal H. The VCO unit 102
An internal clock signal is generated from the received internal horizontal pulse PH and supplied to the horizontal counter 104 and the dot clock generation unit 105.

The horizontal counter 104 counts the number of clocks of the received internal clock signal, and
The count number is supplied to 3. The horizontal decoder 103 generates a horizontal control signal and a vertical control signal according to the count number of the horizontal counter 104. Dot clock generator 1
05 generates a horizontal control signal according to the internal clock signal received from the VCO unit 102.

The horizontal decoder 103 generates an internal horizontal synchronizing signal (line clock) in accordance with the count number of the horizontal counter 104,
It is supplied to the P generator 109. The vertical counter 108 counts the number of clocks of the received internal horizontal synchronization signal (line clock), and supplies the counted number to the vertical decoder 107. The vertical decoder 107 generates a vertical control signal according to the count number of the vertical counter 108.

The vertical decoder 107 generates a decode signal according to the count number of the vertical counter 108 and supplies it to the synchronization control unit 106. Synchronization control unit 106
Is a vertical synchronization signal V supplied from the RGB decoder,
An internal vertical synchronization signal is generated from the decode signal supplied from the vertical decoder 107 and the vertical counter 108 and F
It is supplied to the RP generator 109. The FRP generation unit 109
A frame pulse signal is generated from the internal horizontal synchronization signal supplied from the horizontal decoder 103 and the internal vertical synchronization signal supplied from the synchronization control unit 106.

The horizontal decoder 103 and the vertical decoder 107
The dot clock generator 105 supplies the generated horizontal control signal and vertical control signal to the LCD driver. The LCD driver controls the LC according to the horizontal control signal and the vertical control signal supplied from the LCD controller.
By charging a capacitor (pixel capacitor C _LC ) formed of the pixel electrode D, the common electrode, and the liquid crystal of D, the orientation of the liquid crystal is controlled to display an image.

[0010]

The video signal reproduced by the image reproducing unit has a part of a waveform when the image reproducing unit performs special reproduction such as "fast forward reproduction" and "rewind still reproduction". It will be disturbed. At this time, the composite sync signal C separated from the video signal by the RGB decoder
As shown in FIG. 8 (b), the waveform of the SY around the vertical synchronizing signal (V Sync) is more distorted than the normal composite synchronizing signal CSY shown in FIG. 8 (a). FIG.
The PLL unit 101 to which the horizontal synchronizing signal H generated from the composite synchronizing signal CSY whose waveform is disturbed as shown in FIG. 2B takes several H periods (several scanning line periods) until the phase is adjusted to the horizontal synchronizing signal H. Becomes Therefore, LC
In particular, the D controller generates a vertical control signal and a horizontal control signal which are shifted in timing in the first part of the display area and supplies them to the signal driver. As a result, the LCD displayed an image in which the upper part of the screen was displaced (bent).

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a display control device and a display device control method capable of displaying an appropriate image from a video signal whose waveform of a synchronization signal is disturbed by special reproduction or the like. The purpose is to provide.

[0012]

In order to achieve the above object, a display control apparatus according to a first aspect of the present invention comprises: a synchronizing signal input means for inputting a synchronizing signal included in an image signal; Reference signal generating means for generating a reference signal whose phase is adjusted to the synchronization signal input by the means,
A control signal generation unit for generating a control signal for controlling a display device according to the reference signal generated by the reference signal generation unit; and a control signal generated by the control signal generation unit and an input by the synchronization signal input unit. A signal synchronization monitoring unit that detects a synchronization deviation with the synchronized signal, and a control signal generated by the control signal generation unit when the signal synchronization monitoring unit detects a synchronization deviation that is equal to or greater than a predetermined range. Control signal correction means for correcting so as to synchronize with the synchronization signal input by the synchronization signal input means,
Control signal output means for outputting a control signal generated by the control signal generation means to a display device.

According to the present invention, the control signal generating means includes:
According to the reference signal generated by the reference signal generation means,
A control signal for controlling the display device is generated. The control signal correction unit synchronizes the control signal generated by the control signal generation unit with the synchronization signal input by the synchronization signal input unit when the signal synchronization monitoring unit detects a synchronization shift exceeding a predetermined range. Correction as follows. As a result, an appropriate image can be displayed on the display device from the video signal in which the waveform of the synchronization signal is disturbed due to special reproduction or the like.

The control signal generation means generates a control signal including at least an internal synchronization signal, and the signal synchronization monitoring means receives the internal synchronization signal generated by the control signal generation means and the synchronization signal input means. The control signal correction means corrects the internal synchronization signal generated by the control signal generation means so as to synchronize with the synchronization signal input by the synchronization signal input means. Is also good. As a result, an appropriate image can be displayed on the display device from the video signal in which the waveform of the synchronization signal is disturbed due to special reproduction or the like.

The control signal correction means supplies a reset signal for resetting a timing at which an internal synchronization signal is generated to the control signal generation means, and transmits the internal synchronization signal generated by the control signal generation means to the synchronization signal input signal. The correction may be made so as to synchronize with the synchronization signal input by the means.
As a result, an appropriate image can be displayed on the display device from the video signal in which the waveform of the synchronization signal is disturbed due to special reproduction or the like.

In order to achieve the above object, a display control device according to a second aspect of the present invention comprises a synchronizing signal input means for inputting a synchronizing signal included in an image, and a synchronizing signal input by the synchronizing signal input means. Reference signal generation means for generating a reference signal having the same phase, internal clock generation means for generating an internal clock according to the reference signal generated by the reference signal generation means, and an internal clock generated by the internal clock generation means Counting means for counting the number of clocks, decoding means for generating a control signal for controlling a display device according to the count number of the internal clock counted by the counting means, and a control signal generated by the decoding means. A signal synchronization monitor for detecting a synchronization deviation from a synchronization signal input by the synchronization signal input means. Means for synchronizing a control signal generated by the decoding means with a synchronization signal input by the synchronization signal input means when the signal synchronization monitoring means detects a synchronization deviation equal to or greater than a predetermined range. It is characterized by comprising control signal correction means for correcting, and control signal output means for outputting the control signal generated by the decoding means to a display device.

According to the present invention, the counting means counts the number of internal clocks generated by the internal clock generating means. The decoding means generates a control signal for controlling the display device according to the count number of the internal clock counted by the counting means. The control signal correction unit corrects the control signal generated by the decoding unit so as to be synchronized with the synchronization signal input by the synchronization signal input unit when the signal synchronization monitoring unit detects a synchronization shift exceeding a predetermined range. I do. As a result, an appropriate image can be displayed on the display device from the video signal in which the waveform of the synchronization signal is disturbed due to special reproduction or the like.

The decoding means generates a control signal including at least an internal synchronization signal, and the signal synchronization monitoring means generates a control signal including the internal synchronization signal generated by the decoding means and the synchronization signal input by the synchronization signal input means. And the control signal correction means may correct the internal synchronization signal generated by the decoding means so as to be synchronized with the synchronization signal input by the synchronization signal input means. As a result, an appropriate image can be displayed on the display device from the video signal in which the waveform of the synchronization signal is disturbed due to special reproduction or the like.

The control signal correcting means supplies a reset signal for resetting the count number of the internal clock to the counting means, and outputs an internal synchronizing signal generated by the decoding means through the synchronizing signal input means. May be corrected so as to synchronize with. As a result, an appropriate image can be displayed on the display device from the video signal in which the waveform of the synchronization signal is disturbed due to special reproduction or the like.

In order to achieve the above object, a control method of a display device according to a third aspect of the present invention includes a synchronizing signal inputting step of inputting a synchronizing signal included in an image signal, and a synchronizing signal inputting step. A reference signal generating step of generating a reference signal in phase with the synchronization signal; a control signal generating step of generating a control signal for controlling a display device according to the reference signal generated by the reference signal generating step; A signal synchronization monitoring step for detecting a synchronization deviation between the control signal generated in the control signal generation step and the synchronization signal input in the synchronization signal input step, and synchronization not less than a predetermined range in the signal synchronization monitoring step. When a deviation is detected, the control signal generated in the control signal generation step is transmitted to the synchronization signal input step. And a control signal output step of outputting a control signal generated by the control signal generation step to a display device. .

According to the present invention, the control signal generating step generates a control signal for controlling the display device according to the reference signal generated in the reference signal generating step. The control signal correction step includes, when a synchronization deviation exceeding a predetermined range is detected in the signal synchronization monitoring step, converting the control signal generated in the control signal generation step to the synchronization signal input in the signal input step. Correct to synchronize. As a result, an appropriate image can be displayed on the display device from the video signal in which the waveform of the synchronization signal is disturbed due to special reproduction or the like.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A display control device according to an embodiment of the present invention will be described below with reference to the drawings. FIG.
FIG. 1 is a block diagram showing an example of a display control device and peripheral circuits according to an embodiment of the present invention. These circuits are
RGB decoder 1, inverting amplifier 2, scan driver 3
, LCD 4, signal driver 5, amplifier 6, LC
It comprises a D controller 7.

The RGB decoder 1 receives a video signal supplied from a video reproducing unit or the like and separates the video signal into a color signal and a composite synchronization signal CSY. The RGB decoder 1 generates an RGB signal from the separated color signals, and generates a horizontal synchronization signal H and a vertical synchronization signal V from the composite synchronization signal CSY. The RGB decoder 1 supplies the generated RGB signals to the inverting amplifier 2 and converts the horizontal synchronization signal H, the vertical synchronization signal V, and the composite synchronization signal CSY into the LCD controller 7.
To supply.

The inverting amplifier 2 receives signals from the RGB decoder 1
A GB signal is input, and the polarity of the RGB signal is set to 1 for each frame.
An RGB inverted signal that is inverted for each line is generated and supplied to the signal driver 5.

The scanning driver 3 includes an LCD controller 7
The gate lines GL of the LCD 4 are sequentially selected in accordance with the vertical control signal supplied from the
Is applied with a gate pulse. The vertical control signal includes a gate reset signal GRES, a gate pulse clock signal GPCK, a gate start signal GSRT, and the like. Details of each signal will be described later.

The LCD 4 comprises a TFT liquid crystal display element, and pixel electrodes and TFTs (Thin Film Transistors) arranged in a matrix of i columns × j rows (i and j are natural numbers of 2 or more).
istor) and a common electrode opposed to the pixel electrode via the liquid crystal. Each pixel electrode is connected to a corresponding signal line DL via a current path of a corresponding TFT. The gates of the TFTs in each column are connected to a common gate line G.
L. The LCD 4 displays an image by controlling the orientation of the liquid crystal by charging the capacitance (pixel capacitance C _LC ) formed by the pixel electrode, the common electrode, and the liquid crystal through the gate line GL and the signal line DL. .

The signal driver 5 includes an LCD controller 7
And outputs an RGB inversion signal to the signal line DL of the LCD 4 in accordance with the horizontal control signal supplied from. Note that the horizontal control signal includes a dot clock signal DCK, a data line start signal SRT, an output enable signal OE, and the like. Details of each signal will be described later.

The amplifier 6 inverts the polarity of the common voltage signal Vcom for each frame and for each line according to the frame pulse signal FRP supplied from the LCD controller 7 and supplies the same to the LCD 4.

The LCD controller 7 includes a PLL unit 11, a VCO unit 12, and a phase comparison unit 13 as shown in FIG.
, A horizontal decoder 14, a horizontal counter 15, a dot clock generator 16, a synchronization controller 17, a vertical decoder 18, a vertical counter 19, an FRP generator 20, a noise filter 21, and a reset controller 22. Consists of

The PLL (Phase Locked Loop) unit 11
The horizontal synchronization signal H is received from the RGB decoder 1, and
The phase comparison section 13 receives the phase comparison signal PD. PL
The L unit 11 supplies the received phase comparison signal PD to the VCO unit 12 in phase with the horizontal synchronization signal H.

The VCO (voltage controlled oscillation circuit) section 12 generates an internal clock signal in accordance with the received phase comparison signal PD, and generates a horizontal counter 15 and a dot clock generation section 1.
6

The phase comparing section 13 generates a phase comparing signal PD from the internal horizontal pulse PH supplied from the horizontal decoder 14 and the composite synchronizing signal CSY supplied from the RGB decoder 1, and supplies it to the PLL section 11.

The horizontal decoder 14 receives the count number from the horizontal counter 15, generates a data line start signal SRT and an output enable signal OE according to the count number, and supplies them to the signal driver 5. Further, the horizontal decoder 14 generates a gate reset signal GRES and a gate pulse clock signal GPCK and supplies them to the scanning driver 3.

The data line start signal SRT is a signal for the signal driver 5 to start sampling the RGB inversion signal supplied from the inversion amplifier 2. The output enable signal OE is a signal for outputting the RGB inversion signal sampled by the signal driver 5 to the signal line DL in parallel in units of one line (one horizontal scanning period). The gate reset signal GRES is a signal for the scanning driver 3 to thin out a video signal during a horizontal scanning period. The gate pulse clock signal GPCK is supplied to the scan driver 3
Is a signal for shifting the gate start signal GSRT.

The horizontal decoder 14 receives the count number from the horizontal counter 15 and generates an internal horizontal synchronizing signal (line clock) and an internal horizontal pulse PH according to the count number. The horizontal decoder 14 converts the generated internal horizontal synchronization signal (line clock) into a vertical counter 19, F
The internal horizontal pulse PH is supplied to the RP generation unit 20 and the reset control unit 22, and the internal horizontal pulse PH is supplied to the phase comparison unit 13.

The horizontal counter 15 receives the internal clock signal generated by the VCO unit 12, counts the number of clocks, and supplies the count value to the horizontal decoder 14. Also,
The horizontal counter 15 is reset when a reset signal is supplied from the reset control unit 22.

The dot clock generator 16 is provided by the VCO 1
The internal clock signal supplied from 2 is frequency-divided by 1 / n (n is a natural number of 1 or more) to generate a dot clock signal DCK, which is supplied to the signal driver 5. Dot clock signal D
CK is one line (during one horizontal scanning period) from the RGB inversion signal supplied from the inversion amplifier 2 by the signal driver 5.
Is a signal for sampling each dot.

The synchronization control unit 17 generates an internal vertical synchronization signal according to the vertical synchronization signal V supplied from the RGB decoder 1 and the decode signal supplied from the vertical decoder 18. The synchronization control unit 17 supplies the generated internal vertical synchronization signal to the vertical counter 19 and the FRP generation unit 20.

The vertical decoder 18 receives the count number from the vertical counter 19, generates a gate start signal GSRT according to the count number, and supplies it to the scan driver 3. Further, the vertical decoder 18 generates a decode signal and supplies it to the synchronization control unit 17. Gate start signal GS
RT is a signal for the scan driver 3 to start applying a gate pulse to the gate line GL.

The vertical counter 19 receives an internal horizontal synchronizing signal (line clock signal) from the horizontal decoder 14,
The number of clocks is counted and supplied to the vertical decoder 18. The vertical counter 19 is reset when an internal vertical synchronization signal is supplied from the synchronization control unit 17.

The FRP (frame pulse) generating section 20
In accordance with the internal horizontal synchronization signal supplied from the horizontal decoder 14 and the internal vertical synchronization signal supplied from the synchronization control unit 17, a frame pulse signal FRP is generated and supplied to the inverting amplifier 2 and the amplifier 6.

The noise filter 21 is an RGB decoder 1
And removes the noise component included in the composite synchronization signal CSY supplied from the controller, and supplies the composite synchronization signal CSY from which the noise component has been removed to the reset control unit 22.

The reset control unit 22 includes the noise filter 2
The composite synchronizing signal CSY supplied from 1 is compared with the internal horizontal synchronizing signal supplied from the horizontal decoder 14, and a reset signal is supplied to the horizontal counter 15 when a synchronization shift is detected. Hereinafter, the operation of the reset control unit 22 for detecting a synchronization shift between the composite synchronization signal CSY supplied from the noise filter 21 and the internal horizontal synchronization signal supplied from the horizontal decoder 14 will be described with reference to the drawings.

The reset control unit 22 is provided for the horizontal decoder 14
After detecting the vertical synchronizing signal (V Sync) and the equivalent pulse included in the composite synchronizing signal CSY supplied from, the waveforms of the composite synchronizing signal CSY and the internal horizontal synchronizing signal are compared as shown in FIG. That is, the reset control unit 22 determines the timing T1 of the composite synchronization signal CSY shown in FIG. 3A and the timing T1 shown in FIG. 3B or 3C.
Is compared with the rising timing (timing T2 or timing T3) of the internal horizontal synchronization signal shown in FIG.

The reset controller 22 determines whether the timing T1 and the timing T2 or the timing T1 and the timing T3
If the synchronism with the clock signal is 3 μs or more, a reset signal is supplied to the horizontal counter 15 at a timing T4 shown in FIG.

Further, the reset control unit 22 is provided in FIG.
At timing T4 shown in FIG.
5, the synchronization signal of the next line (scanning line) is changed from the composite synchronization signal CSY shown in FIG.
If no input is made for a period of +10 μsec or more (timing T
5) A reset signal is supplied to the horizontal counter 15 again in order to prevent a synchronization deviation of the internal vertical synchronization signal.

Hereinafter, control operations performed by the display control device according to this embodiment will be described. RGB decoder 1
Receives a video signal read from a video tape by a video playback unit (not shown) via a video head. The video reproduction unit performs Y / C separation (luminance / color separation) on the received video signal to separate it into a composite synchronization signal and a chroma signal. Further, the RGB decoder 1 generates an RGB signal from the separated chroma signal, and generates a horizontal synchronization signal H and a vertical synchronization signal V from the composite synchronization signal. RGB
The decoder 1 supplies the generated RGB signals to the inverting amplifier 2, and supplies the horizontal synchronization signal H, the vertical synchronization signal V, and the composite synchronization signal CSY to the LCD controller 7.

The inverting amplifier 2 receives signals from the RGB decoder 1
A GB signal is input, and the polarity of the RGB signal is set to 1 for each frame.
An RGB inverted signal that is inverted for each line is generated and supplied to the signal driver 5.

The LCD controller 7 processes the input horizontal synchronizing signal H, vertical synchronizing signal V, and composite synchronizing signal CSY to generate a horizontal control signal, a vertical control signal, and the like. At this time, when a video playback unit (not shown) performs special playback such as “fast forward playback” and “rewind still playback”, the LCD controller 7 outputs a waveform around the vertical synchronization signal (V Sync) from the RGB decoder 1. The disturbed composite synchronizing signal CSY and the horizontal synchronizing signal H are input.

The input of the horizontal synchronizing signal H having a distorted waveform
The LL unit 11 takes several H periods (several scanning line periods) to adjust the phase of the phase comparison signal PD received from the phase comparison unit 13 to the horizontal synchronizing signal H whose waveform is disturbed.
A phase comparison signal PD out of phase is supplied to the O section 12.
The VCO unit 12 operates according to the received phase comparison signal PD.
An internal clock signal out of synchronization is generated and supplied to the horizontal counter 15. The horizontal decoder 14 includes a horizontal counter 1
The count number is input from 5 and an internal horizontal synchronization signal (line clock) out of synchronization is generated according to the count number.

The reset control unit 22 includes a noise filter 2
When the synchronizing deviation between the composite synchronizing signal CSY input through the H.1 and the internal horizontal synchronizing signal (line clock) supplied from the horizontal decoder 14 becomes 3 μs or more as shown in FIG. To synchronize with the composite synchronizing signal CSY.

Hereinafter, the operation of generating the horizontal control signal and the vertical control signal performed by the LCD controller 7 while synchronizing with the composite synchronizing signal CSY will be described. First, the dot clock signal DCK and the data line start signal SR
The generation operation of T and the output enable signal OE will be described.
The PLL unit 11 receives the horizontal synchronization signal H from the RGB decoder 1.
And the phase comparison signal PD from the phase comparison unit 13
To receive. The PLL unit 11 receives the phase comparison signal P
D is supplied to the VCO unit 12 in phase with the frequency of the horizontal synchronization signal H.

The VCO (voltage controlled oscillation circuit) section 12 generates an internal clock signal in accordance with the received phase comparison signal PD, and generates a horizontal counter 15 and a dot clock generation section 1.
6

The dot clock generator 16 generates a dot clock signal DCK by dividing the horizontal internal clock signal by 1 / n (n is a natural number of 1 or more). Horizontal counter 15
Receives an internal clock signal from the VCO unit 12, counts the number of clocks, and supplies the counted number to the horizontal decoder 14.

The horizontal decoder 14 generates an internal horizontal synchronizing signal shown in FIG. 5C according to the count number of the horizontal counter 15 and supplies it to the vertical counter 19, the FRP generator 20 and the reset controller 22. Also, the horizontal decoder 1
4 corresponds to the count number of the horizontal counter 15 in FIG.
The data line start signal SRT shown in FIG.
An output enable signal OE shown in (f) is generated.

The noise filter 21 supplies the composite synchronization signal CSY shown in FIG.

The reset control unit 22 compares the rising edge of the composite synchronizing signal CSY shown in FIG. 5B (timing T6) with the rising edge of the internal horizontal synchronizing signal shown in FIG. 5C (timing T7). When the synchronization deviation between the timing T6 and the timing T7 is equal to or longer than 3 μs, the reset control unit 22 sets the timing shown in FIG. 5D at the next rising edge of the composite synchronization signal CSY (timing T8).
The reset signal is set to the high level as shown in FIG.

The horizontal counter 15 is reset when the reset signal shown in FIG. 5D goes high.
When the horizontal counter 15 is reset, the horizontal decoder 14 outputs the output enable signal OE as shown in FIG.
At a low level (timing T8). After the horizontal counter 15 is reset, the horizontal decoder 14
As shown in (e), when the count number of the horizontal counter 14 reaches a predetermined value (timing T9), the data line start signal SRT is set to a high level.

As a result, data line start signal SR
T and the output enable signal OE are output from the reset control unit 22.
As a result, the horizontal counter 15 is reset in accordance with the rising edge of the composite synchronization signal CSY, so that the horizontal counter 15 is corrected in synchronization with the composite synchronization signal CSY.

Note that the reset control unit 22 is provided in FIG.
The reset signal shown at the timing T8 of FIG.
5, when the next rising edge of the composite synchronizing signal CSY is not detected for more than 1H period (one scanning line period) +10 μsec, the reset signal is sent to the horizontal counter 15 again to eliminate the synchronization deviation of the internal vertical synchronizing signal. Supply.

The LCD controller 7 sequentially supplies the dot clock signal DCK, the data line start signal SRT and the output enable signal OE thus generated to the signal driver 5.

Next, the reset control unit 22 sets the timing T
8, the gate reset signal GRES and the gate pulse clock signal G in a state where the reset signal is at a high level.
The operation of generating the PCK and the gate start signal GSRT will be described. At timing T8 shown in FIG. 6D, when the reset signal goes high, the horizontal counter 15 is reset. The horizontal decoder 14 includes a horizontal counter 15
Is reset, the gate reset signal GRES is set to the low level as shown in FIG.
8). After the horizontal counter 15 is reset, the horizontal decoder 14 outputs the horizontal counter 15 as shown in FIG.
When the count number of the clock signal reaches a predetermined value (timing T10), the gate start signal GSRT and the gate pulse clock signal GPCK are set to the high level.

As a result, the gate start signal GSRT,
The gate pulse clock signal GPCK and the gate reset signal GRES are reset by the reset control unit 22 to reset the horizontal counter 15 at the rising edge of the composite synchronization signal CSY.
It is corrected in synchronization with Y.

The LCD controller 7 sequentially outputs the gate reset signal GRE of the vertical control signal thus generated.
S, the gate pulse clock signal GPCK and the gate start signal GSRT are supplied to the scan driver 3.

The scanning driver 3 includes an LCD controller 7
Start signal GSRT, gate pulse clock signal GPCK and gate reset signal G supplied from
The gate lines GL of the RESLCD 4 are sequentially selected, and a gate pulse is applied to the selected gate line GL. Further, the signal driver 5 responds to the dot clock signal DCK, the data line start signal SRT, and the output enable signal OE supplied from the LCD controller 7,
The inverted GB signal is output to the signal line DL of the LCD 4.
Accordingly, the image signals are sequentially written to each pixel capacitance C _LC of the LCD 4, is displayed image defined by the video signal.

As described above, L according to this embodiment
The CD controller 7 corrects the vertical control signal and the horizontal control signal by synchronizing with the composite synchronizing signal CSY when detecting the synchronism shift of the internal horizontal synchronizing signal generated by the horizontal decoder 14. Can be displayed.

In the above embodiment, the reset control unit 2
2 supplies a reset signal to the horizontal counter 15 when the synchronization deviation between the composite synchronizing signal CSY and the internal horizontal synchronizing signal becomes 3 μsec or more, but the time within the allowable range of the synchronizing deviation is arbitrary. For example, video system and LCD
According to the relationship with the arrangement of the liquid crystal display elements, the time within the allowable range of the synchronization shift may be determined experimentally. Also,
The reset control unit 22 outputs the reset signal to the horizontal counter 1
After supplying the reset signal to the horizontal counter 15, the reset signal is again supplied to the horizontal counter 15 when the next rise of the composite synchronizing signal CSY is not detected for more than 1H period + 10 μsec.

In the above embodiment, the display control device (L
CD controller) controlled the matrix type LCD, but the display device to be controlled is arbitrary. For example, a matrix-type plasma display may be controlled.

[0069]

As described above, an appropriate image can be displayed on a display device from a video signal whose waveform of a synchronizing signal is disturbed by special reproduction or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a display control device and peripheral circuits according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a display control device according to the embodiment of the present invention;

FIG. 3 is a timing chart showing a generation timing of a reset signal generated by a reset control unit 22;

FIG. 4 is a timing chart showing a generation timing of a reset signal generated by a reset control unit 22;

FIG. 5 is a timing chart illustrating a generation operation of a horizontal control signal generated by the display control device according to the embodiment of the present invention;

FIG. 6 is a timing chart showing an operation of generating a vertical control signal generated by the display control device according to the embodiment of the present invention;

FIG. 7 is a block diagram illustrating a configuration of a conventional display control device.

FIG. 8 is a diagram showing signal waveforms of a composite synchronizing signal CSY during normal reproduction and special reproduction.

[Explanation of symbols]

1 ... RGB decoder, 2 ... inverting amplifier, 3 ... scan driver, 4 ... LCD, 5 ... signal driver, 6 ... amplifier, 7 ... LCD controller, 11 ... .PLL section, 12
... VCO section, 13 ... Phase comparison section, 14 ... Horizontal decoder, 15 ... Horizontal counter, 16 ... Dot clock generation section, 17 ... Synchronization control section, 18 ... Vertical Decoder, 19 ...
・ Vertical counter, 20 ・ ・ ・ FRP generation unit, 21 ・ ・ ・ Noise filter, 22 ・ ・ ・ Reset control unit, 101 ・ ・ ・ PLL
Unit, 102: VCO unit, 103: horizontal decoder, 10
4 ... horizontal counter, 105 ... dot clock generator,
106: synchronization control unit, 107: vertical decoder, 108
... Vertical counter, 109 ... FRP generator

Claims (7)

[Claims] 1. A synchronizing signal input means for inputting a synchronizing signal included in an image signal, a reference signal generating means for generating a reference signal in phase with the synchronizing signal input by the synchronizing signal input means, and the reference signal Control signal generating means for generating a control signal for controlling a display device in accordance with the reference signal generated by the generating means; and a control signal generated by the control signal generating means and a synchronization input by the synchronization signal input means. A signal synchronization monitoring unit that detects a synchronization deviation with a signal; and a control signal generated by the control signal generation unit when the signal synchronization monitoring unit detects a synchronization deviation that is equal to or greater than a predetermined range. A control signal correction unit for correcting the signal to be synchronized with the synchronization signal input by the input unit; and a display device for displaying the control signal generated by the control signal generation unit. Display control device characterized by and a control signal output means for outputting. 2. The control signal generation means generates a control signal including at least an internal synchronization signal. The signal synchronization monitoring means controls the internal synchronization signal generated by the control signal generation means and the synchronization signal input means. The control signal correction unit detects a synchronization shift with the input synchronization signal, and corrects the internal synchronization signal generated by the control signal generation unit so as to be synchronized with the synchronization signal input by the synchronization signal input unit. The display control device according to claim 1, wherein: 3. The control signal correction unit supplies a reset signal for resetting a timing of generating an internal synchronization signal to the control signal generation unit, and transmits the internal synchronization signal generated by the control signal generation unit to the synchronization signal. The display control device according to claim 1, wherein the correction is performed so as to be synchronized with a synchronization signal input by the signal input unit. 4. A synchronizing signal input means for inputting a synchronizing signal included in an image, a reference signal generating means for generating a reference signal in phase with the synchronizing signal input by the synchronizing signal input means, and the reference signal generating means Means for generating an internal clock in accordance with a reference signal generated by the means; counting means for counting the number of clocks of the internal clock generated by the internal clock generating means; and internal clock counted by the counting means. Decoding means for generating a control signal for controlling the display device according to the count number of the signal; and a signal for detecting a synchronization shift between the control signal generated by the decoding means and the synchronization signal input by the synchronization signal input means. Synchronization monitoring means, and the signal synchronization monitoring means does not synchronize more than a predetermined range. A control signal correction unit that corrects the control signal generated by the decoding unit so that the control signal is synchronized with the synchronization signal input by the synchronization signal input unit; and displays the control signal generated by the decoding unit. A display control device, comprising: control signal output means for outputting to a device. 5. The decoding means generates a control signal including at least an internal synchronization signal, and the signal synchronization monitoring means generates an internal synchronization signal generated by the decoding means and a synchronization signal input by the synchronization signal input means. Detecting a synchronization deviation with a signal, wherein the control signal correction unit corrects the internal synchronization signal generated by the decoding unit so as to be synchronized with the synchronization signal input by the synchronization signal input unit. The display control device according to claim 4. 6. The control signal correction means supplies a reset signal for resetting the count number of the internal clock to the counting means, and inputs an internal synchronization signal generated by the decoding means through the synchronization signal input means. The display control device according to claim 4, wherein correction is performed so as to synchronize with the synchronization signal. 7. A synchronizing signal inputting step of inputting a synchronizing signal included in an image signal; a reference signal generating step of generating a reference signal having a phase adjusted to the synchronizing signal input in the synchronizing signal inputting step; A control signal generation step of generating a control signal for controlling a display device according to the reference signal generated by the generation step; and a synchronization signal input by the control signal generation step and the synchronization signal input step. A signal synchronization monitoring step of detecting a synchronization deviation with a signal, and when a synchronization deviation of a predetermined range or more is detected in the signal synchronization monitoring step, a control signal generated by the control signal generation step, A control signal correction step for correcting so as to synchronize with the synchronization signal input in the synchronization signal input step. And a control signal output step of outputting a control signal generated by the control signal generation step to a display device.