JPH11249908A - Interrupt handling method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute emergency processing without waiting for the generation of a timer interrupt request. SOLUTION: When a CPU discriminates it during execution of interrupt handling that emergency processing is necessary (200), it sets a flag indicating this state (201) and queues the emergency processing (202) and causes the I/O to generate a self-feedback interrupt request (203) and supplies it to an interrupt signal control circuit 12. When processing the self-feedback interrupt request, the CPU processes emergency processings on a queue 301 in order. Thus, the emergency processing is processed without waiting for the generation of a timer interrupt request.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an interrupt processing method for processing an interrupt request to a CPU.

[0002]

2. Description of the Related Art As shown in FIG.
An interrupt signal control circuit 12 is used to control the processing order of various interrupts by U10. The interrupt signal control circuit 12 includes a timer interrupt request which is periodically generated by the timer circuit 14 and is generally given the highest priority.
Various interrupt requests are adjusted according to the procedure shown in FIG.
10 is made to perform hardware interrupt processing.

In the procedure shown in FIG. 4, the interrupt signal control circuit 12 first determines whether or not a new interrupt request has occurred (100). When a new interrupt request is generated, the interrupt signal control circuit 12
It is determined whether or not the interrupt request has a higher priority than the interrupt process being executed (102). If it is determined that the interrupt request has a higher priority, the CPU 10 interrupts the process currently being executed and A new interrupt process with a high priority is started (10
4). Also, at the time when step 102 is executed, the CPU
When no interrupt processing is being executed by the interrupt processing unit 10, the interrupt signal control circuit 12 immediately executes step 104, and causes the CPU 10 to execute a new interrupt processing requested this time.

When the interrupt processing being executed is completed (106), the interrupt signal control circuit 12 determines whether there is any interrupt processing or request that is currently interrupted or on standby (108),
When such an interrupt process or request exists, the one having the highest priority is started or restarted by the CPU 10 (110). If it is determined in step 106 that the interrupt processing has not been completed, or if it is determined in step 108 that the interrupt processing does not exist, the process returns to step 100 as in step 110.

When executing the interrupt processing, the CPU 10 usually determines whether or not an emergency processing is necessary as shown in FIG. 5 (200). When urgent processing is necessary, the CPU 10 sets a flag indicating that urgent processing is necessary (201), and queues urgent processing determined to be necessary (202). That is, C
The execution queue 300 provided in the PU 10 or in a memory attached to the PU 10 has a queue 301 for waiting for emergency processing and a queue 302 for waiting for normal processing. Queuing to 301 is performed. Note that the normal process here is a process required in processes other than the interrupt process. The CPU 10 operates in the queue 3 in the normal state.
02 are processed in the order in which they are queued.

When a timer interrupt request to which the highest priority is given occurs, the interrupt signal control circuit 12
According to the procedure of FIG.
U10 interrupts all the processes currently being executed and executes the timer interrupt process shown in FIG. When executing the timer interrupt processing, the CPU 10 first determines whether or not a flag indicating that urgent processing is necessary is set (400). If the flag is not set,
The CPU 10 restarts the normal processing for processing the queued normal processing in the order of the queue. Conversely, when it is determined that the flag is set (40
0), the CPU 10 interrupts the normal process currently being executed (401), and starts execution of the oldest emergency process in the queue 301 (402). CPU 10
As long as there is an urgent process on the queue 301, it is processed in the order of queuing. When there is no more urgent process on the queue 301 (403), the process of the CPU 10 proceeds to step 404, where the normal process is resumed and the above-mentioned flag is reset.

[0007] In this prior art, there is a problem that the execution of the urgent process is particularly delayed. In other words, even if an emergency process is queued in a certain interrupt process, this emergency process is executed at the next time when a timer interrupt request is generated. Only the execution of the emergency processing will be delayed.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to enable an emergency process to be executed without waiting for a timer interrupt request to occur. Another object of the present invention is to provide a CPU
An object of the present invention is to achieve the above object without making a significant change in a processing procedure executed by a peripheral circuit, a CPU, or the like.

In order to achieve such an object, the present invention provides:
When an interrupt request to the CPU is generated, the interrupt signal control circuit selects the highest priority interrupt request from among the interrupt requests currently issued to the CPU,
However, in the interrupt processing method for executing the interrupt processing related to the interrupt request selected by the interrupt signal control circuit, the necessity of the emergency processing is determined, and when it is determined that the emergency processing is necessary, the emergency processing is queued. When queuing the emergency process, the CPU executes a procedure of generating a self-feedback interrupt request, which is an interrupt request for executing the emergency process, during the execution of the interrupt process. It is characterized in that emergency processing on a queue is executed in response to a feedback interrupt request. As described above, in the present invention, since the CPU itself generates the self-feedback interrupt request for executing the emergency processing, the self-feedback interrupt request can be executed without generating the timer interrupt request. Emergency processing is executed at the time (that is, at the time when all interrupt requests having a higher priority than the self-feedback interrupt request have been processed). Therefore, the execution waiting time of the emergency processing is shorter than in the related art.

In practicing the present invention, it is desirable to give the lowest priority to the self-feedback interrupt request.
By doing so, it is possible to prevent interruption processing related to another interrupt request from being interrupted or made to stand by by interruption processing related to the self-feedback interruption request. Also, if the highest priority is given to the timer interrupt request, it is possible to reliably execute the emergency processing when the timer interrupt request occurs, as in the related art.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. The description of the same parts as those of the related art shown in FIGS. 3 to 6 will be omitted, and the corresponding members and functions will be denoted by the same reference numerals and the description thereof will be partially omitted.

FIG. 1 shows a circuit configuration according to an embodiment of the present invention. In the circuit shown in FIG.
Are connected to the interrupt signal control circuit 12, the CPU 10 can input a self-feedback interrupt request having the lowest priority to the interrupt signal control circuit 12 via this I / O.

As shown in FIG. 2, in this embodiment, when the CPU 10 determines that emergency processing is necessary during execution of an interrupt processing (200), it sets a flag to that effect (201). The process is queued on the queue 300 (202), and a self-feedback interrupt request is generated and given to the interrupt signal control circuit 12 via its I / O (2).
03). The interrupt signal control circuit 12 executes the procedure shown in FIG. 4 in response to the self-feedback interrupt request. Since the lowest priority is given to the self-feedback interrupt request, when all other interrupt requests have been processed, the interrupt signal control circuit 12
Causes the CPU 10 to execute an interrupt process related to the self-feedback interrupt request. In the interrupt processing related to the self-feedback interrupt request, the CPU 10 interrupts the normal processing if it is being executed at that time (500 in FIG. 2). The old one is executed (501). When there is no more urgent process on the queue 301 (502), the CPU 10 resumes the normal process interrupted in step 500, and
Reset the flag set in 01 (50
3).

Therefore, according to the present embodiment, it becomes possible for the CPU 10 to execute the emergency processing without waiting for the generation of the timer interrupt request. Furthermore, the modification of the processing procedure and the hardware change required for that are slight, and the implementation cost is low. In addition, since the interrupt processing related to the timer interrupt shown in FIG. 5 can be executed in the same manner as in the related art, there is an opportunity to execute the interrupt processing related to the self-feedback interrupt request before the timer interrupt request occurs. Even if there is no such processing, the CPU 10 can surely cause the CPU 10 to execute the urgent process existing on the queue 300.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a circuit according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing a processing procedure in this embodiment.

FIG. 3 is a block diagram illustrating a configuration of a circuit according to one related art.

FIG. 4 is a flowchart showing an operation procedure of the interrupt signal control circuit.

FIG. 5 is a conceptual diagram showing the operation of a CPU and the configuration of an execution queue in a normal interrupt process.

FIG. 6 is a conceptual diagram showing an operation procedure of a CPU when executing an interrupt process related to a timer interrupt request and a state of an execution waiting queue at that time.

[Explanation of symbols]

10 CPU, 12 interrupt signal control circuit, 14 timer circuit.

Claims (3)

[Claims] When an interrupt request is issued to a CPU, an interrupt signal control circuit selects an interrupt request having the highest priority from interrupt requests currently issued to the CPU. An interrupt processing method for executing an interrupt process related to an interrupt request selected by an interrupt signal control circuit, the CPU determines the necessity of the emergency process, and when it determines that it is necessary, queues the emergency process. The procedure for generating a self-feedback interrupt request, which is an interrupt request for executing this emergency process when queuing the emergency process, is performed by the CPU.
Is executed during execution of an interrupt process, and the CPU executes an emergency process on a queue in response to a self-feedback interrupt request. 2. The interrupt processing method according to claim 1, wherein a lowest priority is given to the self-feedback interrupt request. 3. The interrupt processing method according to claim 1, wherein the highest priority is assigned to a timer interrupt request which is an interrupt request for executing an emergency process on a queue. An interrupt processing method characterized by being provided.