JP2010277422A - Interrupt handler - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interrupt handler which makes an information processing system more properly execute interrupt handling relating to an interrupt request. <P>SOLUTION: Setting data 107 wherein two or more different interrupt request control rules are defined is stored, and an interrupt control part 104 selects interrupt request control rules for respective inputted interrupt requests, from the interrupt request control rules defined in the stored setting data 107 and issues interrupt handling execution instructions I relating to interrupt requests R to an OS 102 in accordance with the selected interrupt request control rules. Thus the interrupt handling execution instructions I relating to interrupt requests R are issued in accordance with different interrupt request control rules, so that interrupt handling relating to the interrupt requests R can be executed more properly in comparison with handling with uniform delay. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an interrupt processing device that issues an interrupt processing execution command related to an interrupt request to an information processing system.

  2. Description of the Related Art Conventionally, in an information processing apparatus such as a computer, an information processing apparatus that issues an interrupt processing execution instruction related to an interrupt request to an information processing system that executes a main routine has been developed. In such a device, if external interrupt requests continue, the execution of the main routine may be impaired, and the processing performance of the entire device may be reduced. Therefore, in Patent Document 1, an interrupt request delay control circuit that delays a timing for outputting a signal level indicating a state of an interrupt request to the external interrupt control circuit of the MPU by a predetermined time is provided so as to delay the external interrupt request. Thus, an apparatus is disclosed in which execution of external interrupt processing and execution of a main routine can be performed alternately.

JP 2002-366369 A

  However, in the above technique, any interrupt request with any content is uniformly delayed, so that an emergency interrupt process that is not desired to be delayed may not be executed.

  The present invention has been made in view of such circumstances, and an object thereof is to provide an interrupt processing device that causes an information processing system to more appropriately execute interrupt processing related to an interrupt request.

  The present invention relates to an interrupt request input means for inputting an interrupt request, a storage means for storing interrupt request control rule definition data in which two or more different interrupt request control rules are defined, and an interrupt stored in the storage means Interrupt request control rule selection means for selecting an interrupt request control rule for each interrupt request input by the interrupt request input means from any of the interrupt request control rules defined in the request control rule definition data, and interrupt request control rule selection According to the interrupt request control rule selected by the means, there is provided an interrupt processing device comprising interrupt processing execution instruction issuing means for issuing an interrupt processing execution instruction related to an interrupt request to the information processing system.

  According to this configuration, the storage unit stores interrupt request control rule definition data in which two or more different interrupt request control rules are defined, and the interrupt request control rule selection unit stores the interrupt request stored in the storage unit. From any of the interrupt request control rules defined in the control rule definition data, the interrupt request input means selects an interrupt request control rule for each input interrupt request, and the interrupt processing execution instruction issuing means selects the interrupt request control rule. In accordance with the interrupt request control rule selected by the means, an interrupt processing execution command related to the interrupt request is issued to the information processing system. For this reason, the interrupt processing execution instruction related to the interrupt request is issued according to different interrupt request control rules, and the interrupt processing related to the interrupt request can be executed more appropriately than the processing to uniformly delay. It becomes possible.

  In this case, the interrupt request control rule definition data stored in the storage means defines different identification information and interrupt control rules for each interrupt request in association with each other, and the interrupt request control rule selection means It is preferable to select an interrupt control rule corresponding to the identification information attached to the input interrupt request by the input means.

  According to this configuration, in the interrupt request control rule definition data stored in the storage means, different identification information and interrupt control rules are defined in association with each interrupt request, and the interrupt request control rule selection means is In order to select the interrupt control rule corresponding to the identification information attached to the interrupt request input by the interrupt request input means, it is specified by which interrupt control rule the input interrupt request should be processed, Execution of interrupt processing is more reliable.

  Moreover, it is preferable that the interrupt control rule is defined in the interrupt request control rule definition data stored in the storage means according to the importance of the interrupt request.

  According to this configuration, the interrupt request control rule definition data stored in the storage means defines the interrupt control rule according to the importance level of the interrupt request. Control becomes possible.

  Also, the interrupt request control rule definition data stored in the storage means is input with an upper limit of the number of times of issuing an interrupt processing execution command related to an interrupt request input within a predetermined time and exceeding the upper limit within a predetermined time. It is preferable that an interrupt request processing is defined.

  According to this configuration, the interrupt request control rule definition data stored in the storage means includes an upper limit for the number of times that an interrupt processing execution instruction related to an interrupt request input within a predetermined time is issued, and an upper limit within the predetermined time. It defines the action of interrupt requests that are input beyond this. Therefore, for example, for an important interrupt request, it is defined that an interrupt processing execution instruction is issued even if the interrupt request is continuously input up to 3 times in 2 milliseconds. If an interrupt request is input only once in a second, an interrupt processing execution instruction is issued, and an interrupt request exceeding that is discarded, so that the interrupt request depends on the type or usage of the interrupt request. An interrupt processing execution instruction can be issued under conditions suitable for the above.

  The interrupt request control rule definition data stored in the storage means includes the interrupt request input setting time that can be set by changing the length, and the interrupt request input within the interrupt request input setting time. It is preferable that an upper limit of the number of times that the interrupt processing execution instruction is issued and an action of an interrupt request input exceeding the upper limit within the interrupt request input setting time are defined.

  According to this configuration, the interrupt request control rule definition data stored in the storage means is input within the interrupt request input set time that can be set by changing the length and the interrupt request input set time. The upper limit of the number of times that an interrupt processing execution instruction related to an interrupt request is issued and the action of an interrupt request input exceeding the upper limit within the interrupt request input setting time are defined, and the interrupt request input setting time is long. Since the upper limit of the number of times that an interrupt process execution instruction is issued can be adjusted, the time until the next interrupt process execution instruction can be issued can be adjusted, for example, Depending on the importance of the interrupt request, the time that the information processing system executes interrupt processing related to the interrupt request and the information processing system executes normal processing It is possible to adjust the time and.

  Also, it is preferable that the interrupt request control rule definition data stored in the storage means defines a delay time from when the interrupt request is input to when the interrupt processing execution instruction related to the interrupt request is issued. is there.

  According to this configuration, the interrupt request control rule definition data stored in the storage means defines a delay time from when an interrupt request is input to when an interrupt processing execution instruction related to the interrupt request is issued. Therefore, for example, an important interrupt request is defined as issuing an interrupt processing execution instruction without delay, and an unimportant interrupt request is defined as issuing an interrupt processing execution instruction after a predetermined delay. Thus, according to the type or application of the interrupt request, an interrupt processing execution instruction can be issued under conditions suitable for the interrupt request.

  In addition, an interrupt request control status recording unit for recording how the interrupt request input to the interrupt request input unit is processed by the interrupt processing execution command issuing unit is provided. When the interrupt processing execution instruction is issued, it is preferable to record the status of the processing in the interrupt request control status recording unit.

  According to this configuration, the interrupt request control status recording unit records how the interrupt request input to the interrupt request input unit is processed by the interrupt processing execution command issuing unit, and the interrupt processing execution command issuing unit When an interrupt processing execution instruction related to an interrupt request is issued, the interrupt request input by referring to the information of the interrupt request control status recording unit in order to record the status of the processing in the interrupt request control status recording unit It can be confirmed how is controlled.

  Furthermore, it is preferable that the interrupt request control rule definition data stored in the storage means can be dynamically changed by the information processing apparatus.

  According to this configuration, since the interrupt request control rule definition data stored in the storage means can be dynamically changed by the information processing device, for example, according to the status of the information processing device, the interrupt request control rule The definition data can be dynamically changed, and the load on the information processing apparatus can be made appropriate by interrupt processing.

  According to the interrupt processing device of the present invention, it is possible to cause the information processing system to more appropriately execute the interrupt processing related to the interrupt request.

It is a block diagram which shows the structure of the interrupt control apparatus which concerns on embodiment. It is a table | surface which shows an example of the interrupt request control rule which concerns on embodiment.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

  As shown in FIG. 1, in the interrupt control device of this embodiment, an OS (Operating System) 101 and an OS 102 are connected to an interrupt control mechanism 106. The OS 101 inputs an interrupt request R to the interrupt control mechanism 106 in order to cause the OS 102 to execute interrupt processing. In addition to executing the main routine, the OS 102 receives the interrupt process execution instruction I from the interrupt control mechanism 106 and executes the interrupt process related to the interrupt process execution instruction I.

  The interrupt control mechanism 106 includes a control method setting unit 103, an interrupt control unit 104, a status presentation unit 105, and setting data 107. The control method setting unit 103 is for receiving a setting for controlling interrupt processing between the OS 101 and the OS 102. The control method setting unit 103 accepts settings for interrupt processing control from either of the OSs 101 and 102.

  The interrupt control unit 104 receives an interrupt request R from the OS 101 and issues an interrupt processing execution instruction I related to the interrupt request R to the OS 102 according to the setting data 107. Further, the interrupt control unit 104 records in the status presentation unit 105 how each interrupt request R has been processed.

  The status presentation unit 105 records how the interrupt control unit 104 processes each interrupt request R, and presents the current and past status of interrupt processing for each interrupt request R to the OS 101 or the OS 102. belongs to. The setting data 107 is data including an interrupt request control rule for each interrupt request R set by the control method setting unit 103.

  The operation of the interrupt control device according to this embodiment will be described below. In the present embodiment, the interrupt control mechanism 106 uses the control data 107 for each OS interrupt number describing the threshold related to the interrupt between the OSs 101 and 102 and the operation of the interrupt control unit 104 when the threshold is exceeded. Setting is performed using the setting unit 103. This makes it possible to predict the interrupt load of the OS 102 that receives the interrupt processing execution instruction I for the interrupt request R.

  As a result, when the OS 102 is performing real-time processing with severe time constraints, the interrupt control mechanism 106 receives only an interrupt processing execution instruction I equal to or less than a threshold (for example, the number of interrupt processing execution instructions per unit time). When the real-time processing is completed, the interrupt processing execution instruction I that has not been received can be received and the interrupt processing can be resumed.

  FIG. 2 shows an example of threshold values defined as interrupt request control rules. In the example of FIG. 2, the number of interrupts within a unit time (the number of interrupt processing execution instructions) is used as a threshold value. As shown in FIG. 2, for each interrupt factor (such as transmission of a specific event between OSs associated with an OS interrupt number), the unit time for limiting the number of interrupts, and the number of interrupts permitted within the unit time, Can be specified as an interrupt request control rule. These interrupt request control rules can be dynamically specified to the control method setting unit 103 from the OS 102 side which is the receiving side.

  As shown in FIG. 2, for example, if the inter-OS interrupt number “1” is designated to be received up to 3 times in 2 milliseconds, a continuous interrupt processing execution instruction I is sent to the receiving OS 102 up to 3 times. The first time limits processing to 2 milliseconds after the first interrupt. In the interrupt process limiting process, delay, error notification, and the like can be selected by setting by the control method setting unit 103 for each OS interrupt number. In the example shown in FIG. 1, for the interrupt request R1 received for the threshold number of times within the unit time, the interrupt control unit 104 issues the interrupt processing execution instruction I1 as it is. On the other hand, for the interrupt request R2 that has reached the threshold number of times within the unit time, the interrupt control unit 104 issues an interrupt processing execution instruction I2 after performing delay processing.

  As a result, in a situation where interrupts between OSs occur frequently, interrupts that should be prioritized are immediately transmitted to the OS 102 within the range of the threshold, and interrupts that should not be prioritized are delayed or errored, thereby losing interrupts between OSs Therefore, it is possible to keep the interrupt load of the OS 102 on the receiving side constant and to continue necessary processing such as an application program that is the purpose of the system.

  Here, the OS 101 that issues the interrupt request R for the inter-OS interrupt, when the interrupt exceeds a specified threshold such as the upper limit of the number of interrupts per unit time, this is handled as an error interrupt or the status of the interrupt control mechanism 106. This can be known by reading the presentation unit 105.

  As a means for knowing that the OS 101 that issues the interrupt request R has exceeded the interrupt threshold value, if the setting data 107 is set to delay an interrupt that exceeds the threshold value, the OS 101 may issue an interrupt request R after issuing an interrupt request R. When a portion corresponding to the interrupt request R in the status presentation unit 105 of the interrupt control mechanism 106 is read, information such as whether the interrupt request R has been accepted or delayed can be obtained. As described above, the OS 101 that is the issuing source of the interrupt request R repeats the process of reading the status presentation unit 105 again after the unit time set for each interrupt request R has elapsed, as shown in FIG. The end of the delay processing of the interrupt request R can be confirmed.

  On the other hand, as a means for knowing that the OS 101 issuing the interrupt request R has exceeded the interrupt threshold, if the setting data 107 is set to return an error when the setting data 107 exceeds the threshold, the OS 101 issues the interrupt request R. Thereafter, a value indicating an error is stored in a portion corresponding to the interrupt request R in the status presentation unit 105, and an error interrupt is issued to the OS 101 that is the source of the interrupt request R. The OS 101 that has received the error interrupt can know the details of the error by reading the corresponding part of the status presentation unit 105.

  In a conventional multi-OS system, if an interrupt is generated frequently from one OS to the other, the OS on the receiving side is busy with the interrupt processing, and the situation where the function cannot be fully performed or a part of the interrupt request is lost. A situation has occurred. This is because, when interrupts occur frequently between OSs, the frequency of occurrence cannot be controlled by interrupt control, and is controlled only by the OS on the interrupt request issuing side, so the load on the OS on the receiving side increases. Alternatively, it is inevitable that some interrupt requests are lost as a result of the load being reduced by prohibiting interrupts by the receiving OS. Also, the interrupt request issuing OS cannot know whether the load on the receiving OS has increased due to the interrupt request, and can decide to implement countermeasures such as temporarily canceling the interrupt request issue. There wasn't.

  However, in the present embodiment, the setting data 107 in which two or more different interrupt request control rules are defined is stored, and the interrupt control unit 104 can select any of the interrupt request control rules defined in the stored setting data 107. Therefore, an interrupt request control rule for each input interrupt request is selected, and an interrupt processing execution instruction I related to the interrupt request R is issued to the OS 102 according to the selected interrupt request control rule. Therefore, the interrupt process execution instruction I related to the interrupt request R is issued according to different interrupt request control rules, and the interrupt process related to the interrupt request R is more appropriately executed than the process of uniformly delaying. It becomes possible to make it.

  In the present embodiment, the stored setting data 107 defines different interrupt numbers between OSs and interrupt control rules for each interrupt request R, and the interrupt control unit 104 receives the input. In order to select an interrupt control rule corresponding to the interrupt number between OSs attached to the interrupt request R, it is specified by which interrupt control rule the input interrupt request R should be processed. More certain.

  In the present embodiment, since the stored setting data 107 defines an interrupt control rule for each importance level of the interrupt request R, it is possible to appropriately control the interrupt process according to the importance level of the interrupt process R. It becomes.

  In the present embodiment, the stored setting data 107 is input with the upper limit of the number of times of issuing the interrupt processing execution instruction I related to the interrupt request R input within a predetermined time and exceeding the upper limit within the predetermined time. Defined interrupt request R is defined. Therefore, for example, in the case of an important interrupt request R, it is defined that the interrupt processing execution instruction I is issued even if the interrupt request R is continuously input up to three times in 2 milliseconds, and in the case of an unimportant interrupt request R Defines that the interrupt request R is issued when the interrupt request R is input only once in 50 milliseconds, and the interrupt request R exceeding the interrupt request R is discarded. Depending on the application, the interrupt processing execution instruction I can be issued under conditions suitable for the interrupt request R.

  In particular, in the present embodiment, the stored setting data 107 includes a unit time for limiting the input of an interrupt request R that can be set by changing the length, and an interrupt input within the unit time. The upper limit of the number of times that the interrupt processing execution instruction I relating to the request R is issued and the action of the interrupt request R input exceeding the upper limit within the unit time are defined. Since the unit time can be set by changing the length, it is possible to issue the next interrupt processing execution instruction I after reaching the upper limit of the number of times the interrupt processing execution instruction I is issued. The time until the OS 102 executes the interrupt processing related to the interrupt request R and the time when the OS 102 executes the normal processing can be adjusted according to the importance of the interrupt request R, for example. It becomes.

  In the present embodiment, the stored setting data 107 defines a delay time from when the interrupt request R is input to when the interrupt processing execution instruction I related to the interrupt request R is issued. For example, an important interrupt request R is defined as issuing an interrupt processing execution instruction I without delay, and an unimportant interrupt request R is defined as issuing an interrupt processing execution instruction I after a predetermined delay. Thus, according to the type or use of the interrupt request R, the interrupt processing execution instruction I can be issued under conditions suitable for the interrupt request R.

  In the present embodiment, the status presentation unit 105 records how the input interrupt request R is processed by the interrupt control unit 104, and the interrupt control unit 104 executes the interrupt processing related to the interrupt request R. When the instruction I is issued, the status of the processing is recorded in the status presenting unit 105, so that it is confirmed how the interrupt request R input is controlled by referring to the information in the status presenting unit 105. be able to.

  Furthermore, in the present embodiment, since the setting data 107 can be dynamically changed by the receiving-side OS 102, for example, the setting data 107 is dynamically changed according to the situation of the receiving-side OS 102, The load on the OS 102 can be made appropriate by the interrupt processing.

  In particular, in the present embodiment, with the configuration described above, the OS 101 on the issuing side of the interrupt request R can grasp the situation where the interrupt request R issued by itself exceeds the threshold and does not reach the receiving OS 102. It is also possible to deal with such as reissuing after waiting for a certain time. In other words, the OS 101 on the issuing side of the interrupt request R can balance the load of the interrupt including the OS 102 on the receiving side and the urgency of the interrupt request R to be issued, and can perform interrupt control suitable for the situation. It becomes.

  It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention. For example, in the above embodiment, the present invention has been described on the assumption that the present invention is mainly applied to inter-OS interrupts, but the present invention can also be applied to interrupts generated from CPU attached devices such as peripheral devices and timers. Is possible. In this case, even when a large number of interrupts are generated due to the abnormality of these devices, it is possible to prevent the OS operation from being disturbed more than necessary. In this case, regarding the interface of the status presentation unit 105 to the device or the like, various methods are conceivable, such as separately connecting with a communication line or providing a new protocol on an existing bus. It is done.

101, 102 ... OS, 103 ... control method setting unit, 104 ... interrupt control unit, 105 ... status presentation unit, 106 ... interrupt control mechanism, 107 ... setting data.

Claims (8)

An interrupt request input means for inputting an interrupt request;
Storage means for storing interrupt request control rule definition data in which two or more different interrupt request control rules are defined;
The interrupt request input means selects the interrupt request control rule for each of the interrupt requests input from any of the interrupt request control rules defined in the interrupt request control rule definition data stored in the storage means. An interrupt request control rule selection means;
In accordance with the interrupt request control rule selected by the interrupt request control rule selection means, an interrupt processing execution instruction issuing means for issuing an interrupt processing execution instruction related to the interrupt request to an information processing system;
An interrupt processing device. In the interrupt request control rule definition data stored in the storage means, identification information different from each other for each interrupt request and the interrupt control rule are defined in association with each other,
The interrupt processing apparatus according to claim 1, wherein the interrupt request control rule selection unit selects the interrupt control rule corresponding to the identification information attached to the interrupt request input by the interrupt request input unit.   The interrupt processing device according to claim 1 or 2, wherein the interrupt control rule definition data stored in the storage means defines the interrupt control rule according to the importance of the interrupt request.   The interrupt request control rule definition data stored in the storage means includes an upper limit of the number of times of issuing the interrupt processing execution command related to the interrupt request input within a predetermined time, and the upper limit within the predetermined time. The interrupt processing apparatus according to any one of claims 1 to 3, wherein a treatment for the interrupt request input beyond the limit is defined.   The interrupt request control rule definition data stored in the storage means includes an interrupt request input setting time that can be set by changing the length, and the interrupt input within the interrupt request input setting time. The upper limit of the number of times that the interrupt processing execution instruction relating to the request is issued and the action of the interrupt request input exceeding the upper limit within the interrupt request input setting time are defined. The interrupt processing device according to any one of claims.   The interrupt request control rule definition data stored in the storage means defines a time to be delayed from when the interrupt request is input to when the interrupt processing execution instruction related to the interrupt request is issued. The interrupt processing device according to any one of claims 1 to 5. An interrupt request control status recording unit for recording how the interrupt request input to the interrupt request input unit is processed by the interrupt processing execution command issuing unit;
7. The interrupt process execution instruction issuing means, when issuing an interrupt process execution instruction related to the interrupt request, records the status of the process in the interrupt request control status recording unit. The interrupt processing device described in 1.   The interrupt processing apparatus according to claim 1, wherein the interrupt request control rule definition data stored in the storage unit can be dynamically changed by the information processing apparatus.

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