JPH07262022A - Interruption processing system - Google Patents

Abstract

PURPOSE:To provide a flexible interruption processing optimum for a system at all times. CONSTITUTION:An interruption control parameter setting part 111 sets a parameter for optimizing interruption control to an interruption control parameter table 21 by recognizing the configuration of an OS when starting the OS. The interruption asynchronously generated is reported from an external device 30 to a CPU 10. An interruption storage control part 112 registers the reported interruption on an interruption queue stack 22. A software interruption generating part 113 generates interruption (software interruption) at any arbitrary timing. At the timing of software interruption generation, an interruption processing part 114 successively reads non-processed interruption from the interruption queue stack 22, decides the possibility of interruption such as system resource competition while referring to the table 21 and processes the interruption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing method in a computer system in which an interrupt is asynchronously generated and notified.

[0002]

2. Description of the Related Art In a computer system in which an interrupt handling process and other software processes share a system resource such as a register, resource conflict between the interrupt handling process and other software processes occurs asynchronously. Only interrupts that do not occur need to be determined and processed.

In a computer system in which an interrupt is generated and notified asynchronously, in the prior art, a hardware (H / W) mechanism for setting a priority for each interrupt factor and notifying an interrupt according to the interrupt priority in the bus control unit. By providing an instruction to the H / W according to the priority order, the software notifies the OS of interrupts that may occur and processes them one by one to prevent system resource contention.

[0004]

In the prior art, even if the OS has a plurality of interrupts, the OS performs the acceptance process one by one. Therefore, system resource conflict does not occur, but there are multiple interrupts that perform the handling process for the same device type, and system resource conflict does not occur even if the handling processes of different types are performed consecutively. Even if there are a plurality of interrupts, the OS had to execute the overhead part of the pre-processing and post-processing of the interrupt handling processing for each interrupt. Also, if high-priority interrupts occur frequently, even if low-priority interrupts occur, they cannot be processed because the OS cannot recognize them.
So-called subduction could occur.

An object of the present invention is to reduce the overhead associated with interrupt processing and generate interrupts by accepting and storing a plurality of generated interrupts and performing interrupt handling processing of the interrupts stored at any timing. It is to realize flexible interrupt processing that is not restricted by the order.

Another object of the present invention is to set an interrupt priority order according to the system configuration and a parameter for fail-safe to prevent sinking at the time of booting the OS, and refer to these parameters. , Always enabling optimized interrupt processing, speeding up interrupt processing, and improving system performance.

[0007]

In order to achieve the above object, the present invention comprises means for storing interrupts that are asynchronously generated and notified, means for generating the start of interrupt processing at an arbitrary timing, and And a means for processing the stored unprocessed interrupt, triggered by the generated interrupt start timing.

Further, according to the present invention, a means for recognizing the system configuration at the time of system startup and setting an interrupt control parameter is provided, and prior to interrupt processing, the interrupt control parameter is referred to to determine whether or not the interrupt processing is possible. It is characterized by doing.

[0009]

[Function] The interrupts that are generated and notified asynchronously are sequentially stored, the interrupt processing start is newly instructed (software interrupt generation), and the stored unprocessed interrupts are collectively processed at that time. . As a result, it is not necessary to process the notified interrupts sequentially and in the order in which they occur, and flexible interrupt control can be realized. Also,
Realize optimal interrupt control for the system by recognizing the system configuration of devices at system startup and dynamically setting the parameters for optimal interrupt processing according to the device configuration. You can

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing a system configuration of an embodiment of the present invention. This system includes a processing unit (CPU) 10,
It comprises a storage device 20 and a plurality of external devices 30. C
The PU 10 has an OS (Operating System) and constitutes a software system that controls and manages the entire computer system. In the present embodiment, the interrupt control parameter setting unit 111, the interrupt storage control unit 112,
Software interrupt generation unit 113, interrupt processing unit 114
To provide. Further, the storage device 20 is provided with an interrupt control parameter table 21 and an interrupt queue stack 22.

The operation will be described below with reference to FIG. OS1
The interrupt control parameter setting unit 111 of No. 1 recognizes the system configuration of the devices connected to the system when the system is started up, calculates various parameters so that the interrupt control most suitable for the current system is performed, and then interrupt memory control The interrupt control parameter table 2 of the storage device 20 so that the unit 112 and the interrupt processing unit 114 can refer to it.
Set to 11. Interrupts from the external device 30 are notified to the CPU 10 in the order of occurrence. Interrupt storage controller 11
2 sequentially stores the generated interrupts in the interrupt queue stack 212 of the storage device 20 together with the information necessary for the interrupt handling processing based on the information in the interrupt control parameter table 211. The OS 11 follows the parameters set in the interrupt control parameter table 211,
In order to execute the interrupt handling processing stored in the interrupt queue stack 22, the software interrupt generation unit 113 is used to generate an interrupt. When an interrupt is generated by the software interrupt generation unit 113, the interrupt processing unit 114 causes the interrupt control parameter table 2
By referring to 1, it is determined whether the interrupts stored in the interrupt queue stack 22 can be processed, and the interrupts that can be processed are sequentially processed.

FIG. 2 is a processing flowchart of the operation performed by the interrupt control parameter setting unit 111 when the system is started up. In order to set the interrupt control parameter, the interrupt control parameter setting unit 111 first specifies the number of processors of the system and the device type and connection position of the external device 30 currently connected to the system, and sets the temporary table ( Step 201). Next, according to the contents of the table, considering the time required for interrupt handling of the currently connected device, the interrupt frequency, etc., the interrupt priority and sunk that are referenced when queuing interrupts are used as interrupt control optimization parameters. Value for preventing the interrupt, software interrupt generator 11 for processing unprocessed interrupts registered in the interrupt queue stack 22
Information such as a queuing coefficient to be referred to at the time of activation reservation of No. 3 is calculated (step 202) and set in the interrupt control parameter table 21 of the storage device 20 (step 20).
3). Note that in the case of a multiprocessor system, parallel processing of interrupts that does not cause system resource conflicts is possible, so queue information for each processor is also set.

FIG. 5 shows the interrupt control parameter table 2
1 shows an example configuration. Here, all parameters other than the contention prohibited resource name are dynamically set according to the number of device connections. The maximum waiting time for interrupt processing is a parameter for preventing sinking. The maximum queue length is a parameter of the allowable limit of queue length. A software interrupt is activated when the current queue length reaches the maximum queue length or when the maximum waiting time for interrupt processing is exceeded.
Further, in the case of the multiprocessor system configuration, the conflict prohibition resource name enables the interrupts of the devices in which the conflict prohibition resources are not duplicated to be processed in parallel.

FIG. 3 is a flowchart of a process performed by the interrupt storage control unit 112 when an interrupt is notified from the external device 30. When the interrupt is notified to the CPU 10, the interrupt storage control unit 112 provides information about interrupt factors and information necessary for interrupt handling processing, such as the priority order set in the interrupt control parameter table 21 and variable values for preventing sinking. Information is obtained (step 301), and the notified interrupt is registered in the interrupt queue stack 22 (step 302). Next, referring to the information in the interrupt control parameter table 21 (step 303), it is determined whether the interrupt processing stored in the interrupt queue stack 22 needs to be executed (step 304), and it is determined that there is a need. If so, the software interrupt generator 11
The start reservation is made in step 3 and the process ends (step 30).
5).

FIG. 6 shows a configuration example of the interrupt queue stack 22. Here, FIG. 6A shows an example in which interrupts of each device are queued in the order of occurrence regardless of the device type, and FIG. 6B shows each of the device types by paying attention to the device type. This is an example of queuing in the order of interrupt levels for each device type. Note that the example of (a) shows a case where the interrupt queue head pointer points to the interrupt level C because the interrupts of the interrupt levels A and B have not occurred. Interrupt queue stack 22
It is possible to configure either one or a combination of both.

When there is a start reservation, the software interrupt generation section 113 generates an interrupt at an arbitrary timing. A few examples are as follows.

(1) Flag setting method When it becomes necessary to carry out interrupt processing (start reservation), a flag is set. A flag check is performed during a process called by a process switch process, a clock interrupt handler process, and the like at certain intervals, and if the flag is on, an interrupt is generated.

(2) Timer method A timer is started, and it is determined whether or not an interrupt processing request is issued at a certain fixed time. If an interrupt processing start request is issued, an interrupt is generated.

(3) Signal Notification Method A process for performing interrupt processing is generated, and when the interrupt processing is performed, a signal is sent to the process and activated to start the interrupt processing.

FIG. 4 shows the software interrupt generator 113.
5 is a processing flowchart in the interrupt processing unit 114 after a software interrupt due to is generated. When an interrupt is generated by the activation of the software interrupt generation unit 13, the interrupt processing unit 114 takes out an interrupt from the head of the interrupt queue of the interrupt queue stack 22 (step 40
1) With reference to the interrupt control parameter table 402 (step 402), it is determined whether or not interrupt processing is possible, such as whether or not an interrupt causes conflict of system resources (step 403). Then, if the processing of the taken out interrupt is permitted, the interrupt processing is performed (step 404). Less than,
Unless it is determined in step 403 that the processing of the interrupt taken out cannot be executed or it is determined in step 405 that there is no interrupt in the interrupt queue, the interrupt is taken out from the interrupt queue and the interrupt processing is repeated.

[0022]

As described above, according to the present invention, by having a mechanism for storing the generated interrupt and starting the interrupt handling process at an arbitrary timing, the flexible interrupt control does not depend on the interrupt type or the notification order. Can be realized. Further, when the system is started up, the OS recognizes the system configuration of the device and the like and sets the parameters for optimizing the interrupt control, so that the interrupt control most suitable for the system configuration can be always realized.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of an interrupt control system according to the present invention.

FIG. 2 is a processing flowchart of an interrupt control parameter setting unit.

FIG. 3 is a processing flowchart of an interrupt storage control unit.

FIG. 4 is a processing flowchart of an interrupt processing unit.

FIG. 5 is a diagram showing a configuration example of an interrupt control parameter table.

FIG. 6 is a diagram showing a configuration example of an interrupt queue stack.

[Explanation of symbols]

 10 Processing Device 11 Operating System 111 Interrupt Control Parameter Setting Unit 112 Interrupt Storage Control Unit 113 Software Interrupt Generation Unit 114 Interrupt Processing Unit 20 Storage Device 21 Interrupt Control Parameter Table 22 Interrupt Queue Stack 30 External Device

Claims (2)

[Claims] 1. An interrupt processing method in a computer system in which interrupts are asynchronously generated and notified, and means for storing interrupts that are asynchronously generated and notified, and means for generating the start of interrupt processing at arbitrary timing. And an interrupt processing method characterized by having means for processing the stored unprocessed interrupt in response to the generated interrupt start timing. 2. The interrupt processing method according to claim 1, further comprising means for recognizing a system configuration and setting an interrupt control parameter at system startup, and referring to the interrupt control parameter prior to interrupt processing. An interrupt processing method characterized by determining whether or not interrupt processing is possible.