JPH11237885A - Musical sound producing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a musical sound producing apparatus, with which cost-up in the case of extending a sound source can be suppressed in comparison with conventional one in the apparatus enabled in the extension of the sound source. SOLUTION: In the musical sound producing apparatus provided with a waveform memory 6 for storing waveform data and a first sound source 8a having an address generating part 18 for generating an address for each of plural time division channels so as to produce musical sounds for plural time division channels, based on (n) pieces of waveform data for each time division channel read out of the waveform memory 6 corresponding to the generated address, the apparatus is provided with a second sound source 8b, which can be added to the configuration of the apparatus and shares the waveform memory 6 together with the first sound source 8a, and a two-step instructing part 5 for generating an instruction signal for changing the number of pieces of waveform data required to be read out for each time division channel into (m) less than (n) when adding the second sound source 8b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tone generator for generating waveform data read out from a waveform memory in a time-division manner by a plurality of sound sources.

[0002]

2. Description of the Related Art Conventionally, in a tone generator, waveform data is stored in a waveform memory, and when a tone generation instruction is given, the waveform data is read out at a predetermined interval, and a tone is generated by a tone generator in accordance with the read waveform data. It is known to form a waveform and pronounce it as a musical tone. In this musical sound generating apparatus, reading the waveform data from the waveform memory at a predetermined interval means that the waveform data sampled at the first sampling frequency and stored in the waveform memory is
That is, reading at a speed corresponding to the second sampling frequency. Therefore, it is necessary to sequentially estimate discrete signals to be sampled at the second sampling frequency from the waveform data to obtain desired waveform data. The estimation of the discrete signal is obtained by reading a plurality of continuous waveform data from the waveform memory and interpolating the waveform data.

[0003]

By the way, in the above-described conventional tone generating apparatus, the structure for forming a tone in a sound source is operated in a time-division manner to achieve one tone.
Some sound sources can produce a plurality of musical tones. Increasing the number of sounds in the tone generator is performed by increasing the frequency of time division in one sound source and further increasing the number of sound sources themselves. On the other hand, in order to respond to various needs of users in the market, a tone generator capable of adding a sound source later has been developed.

[0004] In such a musical sound generating apparatus to which a conventional sound source can be added, when adding a sound source, the waveform data is read from a waveform memory in order to suppress an increase in the frequency of reading the waveform data accompanying an increase in the number of sounds. In addition to the addition of the configuration for reading and interpolating the waveform data to form a musical tone, the specification also adds a waveform memory itself. Therefore, when adding a sound source, a waveform memory that records the same waveform data as that of an existing sound source must be added, and the resulting cost increase accounts for a large proportion of the total cost increase required for the additional sound source. I was

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and provides a tone generator capable of adding sound sources.
It is an object of the present invention to provide a musical sound generator capable of suppressing an increase in cost when adding a sound source as compared with the related art.

[0006]

In order to solve the above-mentioned problems, according to the first aspect of the present invention, a waveform memory for storing waveform data and an address are generated for each of a plurality of time division channels, and the address is generated by the address. A first method of generating musical tones for a plurality of time division channels based on n waveform data for each time division channel read from the waveform memory;
A second tone generating means that can be added to the configuration of the tone generating apparatus, and that shares the waveform memory with the first tone generating means; When two musical tone generating means are added, the read number changing means for changing the number of waveform data to be read in each time-division channel to m less than n is provided. .

According to the present invention, when the second musical tone generating means sharing the waveform memory is added, the number of waveform data to be read in each time division channel is increased from n by the read number changing means. Change to a small number m.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

(1) Overall Configuration FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, reference numeral 1 denotes a keyboard, which is composed of a white key and a black key. Reference numeral 2 denotes a tone switch, which is provided on the operation panel of the tone generator, sets the tone color of the tone to be generated, and supplies information on the set tone color to the control unit 3. The control section 3 controls each section of the musical sound generating apparatus by a predetermined program, and is composed of, for example, a microcomputer.

Next, when an external circuit 7 described later is mounted, the external instruction section 4 outputs an external instruction signal OP to a sound source. The external instruction signal OP is “0” only when the external circuit 7 is not mounted, and takes a value of “1”, “2” or “3” when the external circuit 7 is mounted. . When "1", 1
A delay of two channels occurs, and when "2", a delay of two channels occurs, and when "3", a delay of three channels occurs. That is,
The external instruction signal OP output from the external instruction section 4 is such that after the address generation section 18 outputs an address to the waveform memory, waveform data corresponding to the address is input to the interpolation section 19 through an external circuit. The setting is made in accordance with the time delay in the external circuit 7 up to.

Next, the two-chip instructing unit 5 outputs a chip signal C2 which becomes "1" when the two sound sources 8 are mounted,
The master signal MC which is "1" for the master sound source (8a in the following description) and "0" for the slave sound source (8b in the following description) is a sound source 8a, 8b.
And to the external circuit 7.

The waveform memory 6 stores compressed waveform data and uncompressed waveform data (hereinafter referred to as uncompressed data). The method of storing the waveform data will be described later. The waveform memory 6
According to the address data supplied from the sound source 8, predetermined waveform data is output to the external circuit 7. When the external circuit 7 is not mounted, the signal is directly output to the interpolation unit 19 of the sound source 8. The external circuit 7 is a circuit that is detachably provided between the waveform memory 6 and the sound source 8. After demodulation in accordance with the increment signal INC supplied from the CPU, the signal is supplied to the sound source 8 at a predetermined timing. Here, the meaning of “detachable” means that the external circuit 7 uses the waveform memory 6 and the interpolation unit 1
9 and the configuration not inserted between them can be selected with the same sound source.

Next, the tone generator 8 is a tone generator for sequentially generating 32 independent musical tones by a common circuit by a time-division 32 channel operation. The tone generator 8 generates the address data and is supplied from the waveform memory 6. The waveform data is subjected to interpolation, envelope assignment, analog conversion, etc., and then supplied to the sound system 10. The sound system 10 emits a tone signal supplied from the sound source 8 as a tone using a speaker or the like.

(2) Configuration of Sound Source Next, a detailed configuration of the above-described sound source 8 will be described with reference to FIG. The sound source 8 includes an interface 11, a group of registers 12 to be time-divisionally controlled, an address generator 18,
Interpolation section 19, envelope generation section 20, envelope multiplication section 21 (the sound source components 11 to 12 perform time-division operations on a plurality of channels to generate a plurality of independent musical tones by time division), and a channel accumulation section 22. , And a digital-analog converter (hereinafter referred to as DAC) 23
It is composed of The interface 11 receives various data supplied from the control unit 3 and supplies the data as a predetermined control signal to each of the register groups 12 to be time-divisionally controlled. The sampling frequency of the digital-to-analog conversion in the DAC is 50 KHz, and the 32 time-division channels operate at 32 × 50K = 1.6 MHz obtained by dividing the 32 into 32.

The register group 12 includes:
A note-on signal NON is generated independently for each time-division channel when a key press is detected, and supplied to each unit. Note-on generation unit 13, an interpolation control signal for instructing either two-point interpolation or four-point interpolation P2, a compressed signal COM indicating whether the waveform to be read is a compressed waveform or an uncompressed waveform
A demodulation control unit 14 for outputting P, an address control unit 15 for outputting an address control signal ADDC for reading out waveform data, and a head address control unit for outputting a head address control signal TADDC for designating a head address of the waveform data. 16 and an envelope generation control unit 17 for generating an envelope control signal EV1 for giving a predetermined envelope to the waveform data.

The demodulation control unit 14 outputs the compression signal COMP to the external circuit 7 and the address generation unit 1 at a timing earlier by the delay indicated by the external instruction signal OP.
, And supplies the interpolation control signal P2 to the address generator 18.
And the interpolation control signal P2 is supplied to the interpolation unit 19 at standard timing. For example, the compressed signal COMP becomes “1” when reading compressed waveform data, and becomes “0” when reading uncompressed data. Further, the interpolation control signal P2 becomes "1" in the case of two-point interpolation and becomes "0" in the case of four-point interpolation. Here, both the compression signal COMP and the interpolation control signal P2 are data independently set by the control unit 3 for each time division channel.

Next, the address generator 18 generates an address control signal ADDC and a head address control signal TADD.
C, the address data ADD is generated in accordance with the external instruction signal OP, the chip signal C2, and the master signal MC, and the address data ADD is supplied to the waveform memory 6 at a timing earlier by the delay indicated by the external instruction signal OP. At the same time, the increment signal INC and the signal ODD are supplied to the external circuit 7, and the decimal part of the address is supplied to the interpolation unit 19 at standard timing.

The interpolating section 19 interpolates the waveform data from the waveform memory 6 by an address decimal part in accordance with the interpolation control signal P2, the external instruction signal OP, the chip signal C2, and the master signal MC, and performs a predetermined read cycle. The corresponding waveform data is output to the envelope generating and multiplying unit 21. The envelope generator 20 generates an envelope signal EV2 for 32 channels according to the envelope control signal EV1, and outputs the envelope signal EV2 to the envelope multiplier 21.

The envelope multiplying section 21 adds a corresponding envelope signal to the waveform data of 32 channels which are sequentially input in a time-division manner, and sequentially outputs this to the channel accumulating section 22. The channel accumulating unit 22 accumulates (mixes) sequentially supplied waveform data for 32 channels and outputs the waveform data to the DAC 23 as one-wave waveform data having a sampling frequency of 50 KHz. The DAC 23 converts the waveform data into a tone signal of an analog signal,
The sound is output to the sound system 10 described above.

(3) Configuration Example of Sound Source and External Circuit Here, the arrangement relationship of the external circuit 7, the sound source 8, and the waveform memory 6, the external instruction signal OP, the chip signal C
2. The relationship with the master signal MC will be described with reference to FIG. FIG. 2A is a block diagram showing a configuration when one sound source 8 is used for one waveform memory 6, and has a configuration similar to that of the related art. 4 for each sound channel
Since slots can be used, it is possible to generate 32 channels by four-point interpolation. In this case, in this embodiment, the external instruction signal OP is “0”, the chip signal C2 is “0”, and the master signal MC is “1”. Next, in FIG.
In this configuration, one waveform memory 6 is shared by two sound sources 8a and 8b. The access time of the waveform memory is shared by the two sound sources, and only two slots can be used for each channel. Therefore, two-point interpolation is performed, but sounding of 64 channels is possible. In this case, the external instruction signal OP of the master sound source 8a is “0”, the chip signal C2 is “1”, the master signal MC is “1”, and the external instruction signal OP of the slave sound source 8b is “0”. , The chip signal C2 is “1”, and the master signal MC is “0”.

Next, in FIG. 2 (c), one sound source 8 corresponds to one waveform memory 6, and an external circuit 7 is interposed. In this case, it is possible to generate 32 channels by four-point interpolation,
Reproduction of a compressed waveform and an uncompressed waveform is possible. In this case, the external instruction signal OP is "1", the chip signal C2 is "0", and the master signal MC is "1". However, with respect to the compressed waveform, the reproduction pitch is limited to four times or more the original pitch. Finally, in FIG. 2D, one waveform memory 6 is shared by the two sound sources 8a and 8b, and external circuits 7a and 7b are interposed between the two sound sources. I have. In this case, the read is
Although there are two slots for each channel, four-point interpolation is possible, resulting in 64 channels of sound. However, the compressed waveform,
For the uncompressed waveform, the four-point interpolation can be performed up to twice the reproduction pitch of the original pitch, and the control is performed so that the two-point interpolation is performed using the signal P2 for the reproduction pitch higher than the original pitch. Also at this time, the upper limit of the playback pitch of the compressed waveform is four times the original pitch. The external instruction signal OP in the master sound source 8a is "2", the chip signal C2 is "1", the master signal MC is "1", the external instruction signal OP in the slave sound source 8b is "2", and the chip The signal C2 becomes "1", and the master signal MC becomes "0".

(4) Configuration of Address Generation Unit Next, the configuration of the above-described address generation unit 18 will be described with reference to FIG.
This will be described with reference to FIG. FIG. 3 is a block diagram showing one configuration of the address generator 18 in the present embodiment. In the figure, reference numeral 30 denotes an F-number generator, which sequentially generates F-numbers corresponding to the pitches of musical tones to be produced in accordance with the pitch data of each time-division channel, and adds an integer part of the F-number to a full adder 31 and The F number is supplied to the half adder 33, and the decimal part of the F number is supplied to the full adder 32. The full adder 31 and the full adder 32 add the F number (integer part, decimal part) to the address data (integer part, decimal part) of each time division channel sequentially supplied from the address RAM 38 described later. , The address data is updated in steps corresponding to the pitch.

The carry (carry) of full adder 32
Is supplied to the full adder 31 and the half adder 3
3. These full adders 3
Address data (integer part,
The decimal part is supplied to the address control unit 34. The address control unit 34 includes the address control register 15 shown in FIG.
In accordance with the address control data supplied from the controller, the control unit controls the waveform readout sequence such as the loop waveform readout after the attack waveform is read once and the multiple loop waveforms sequentially and repeatedly, and also inputs the address data based on the F number into the data in the address RAM. Feed to the end.

On the other hand, the channel counter 35 counts the time-division channels and outputs the count value to the full adder 37.
To one of the input terminals. Also, offset generator 3
6 generates an offset value taking any value of “0”, “1”, “2”, “3”, and “4”, and the full adder 37
Is supplied to the other input terminal. The full adder 37 adds the count value and the offset value, and supplies the result to the address RAM 38 as an address.

The address RAM 38 stores the address data supplied to the data input terminal DI in a time-division manner in units of slots obtained by dividing each of the four time-division channels into four in accordance with the timing at which the addresses are supplied. And the address data stored in the above address is read and output from the data output terminal DO. The address data (integer part, decimal part) is supplied to the full adders 31 and 32 via the latch circuit 39 in the slot for updating the address, and the address integer part is supplied via the latch circuit 45. Adder 47
The address fraction is a read slot for supplying a waveform read address.
The signal is supplied to the interpolation unit 19 shown in FIG.

Here, the time division processing in address generation according to the present embodiment will be described with reference to FIG. FIG. 4 is a time chart for explaining the timing of address generation. As described above, in the present embodiment, each channel is divided into four time slots to perform processing. Depending on the count value of the channel counter 35 and the offset value of the offset generator 36, It specifies whether or not processing is being performed on the channel.

In FIG. 4, the uppermost band indicates the channel on the time axis, and the symbol i is the channel number. In the figure, i-channel is the current channel,
Channels in the past are indicated by negative suffixes, and previous channels are indicated by positive suffixes. Each channel is
As shown in the next stage, the data is divided into four time slots T1 to T4. In each of the time slots T1 to T4, reading and writing of address data to and from the address RAM 38 are performed.

First, in the first time slot T1, the sum of the count value of the channel counter 35 and the offset value, that is, the output value of the full adder 37 is used as a read address, and the address integer part and the decimal part are read from the address RAM 38. The data is read out and latched by the latch circuit 39. The offset value in this time slot T1 is
In this embodiment, the value is always "+4", which means that the address integer part in the channel four channels ahead is read. In other words, the address integer part of the i channel is read out in the processing of the past (i-4) channel.

Next, in the second time slot T2, the sum of the count value of the channel counter 35 and the offset value is used as a read address and the address RAM 38
, The address integer part is read out and latched by the latch circuit 45. The offset value in this time slot T2 takes a different value depending on the presence or absence of the external circuit 7,
When the external circuit 7 is not mounted, the value is “0”. When the external circuit 7 is mounted, “+1”, “+2”, or “+2”, or Takes any value of "+3". In this embodiment,
As described above, the presence / absence of the external circuit 7 is distinguished by the external instruction signal OP. The offset value becomes “0” when the external instruction signal OP is “0”, and the external instruction signal OP becomes “0”. In the case of “2”, “+2” is set, and an example of the external circuit 7 using the values of “+1” and “+3” is not disclosed, but “+1” or “+3” depending on internal processing. An external circuit 7 that requires the value of the signal OP and other signals can be easily considered.

Next, in the third time slot T3, the sum of the count value of the channel counter 35 and the offset value is used as a read address and the address RAM 38
, The address decimal part is read out and latched by the latch circuit 46. In this embodiment, the offset value in the time slot T3 is always "0", which means that the decimal part of the address at the current channel is output. Further, in the fourth time slot T4, the address data updated by the full adders 31, 32 and the address control unit 34 is written using the added value of the count value of the channel counter 35 and the offset value as a write address. The offset value in the time slot T4 is always “+4”, like the first time slot, and the address data in the channel four channels ahead is always read, and the updated address data is written as new data.

Therefore, when the external circuit 7 is not mounted, for example, focusing on the i channel, the address data of the i channel is read in the time slot T1 of the (i-4) channel four channels in the past. Issued and updated address data is written in T4. The address integer part is the second of the i channel.
, And the fractional part of the address is sequentially output from the third time slot T3 of the i channel. On the other hand, when the external circuit 7 is attached and the signal OP is set to “2”, the address data of the i channel is updated in the (i−4) channel four channels in the past, The address integer part is sequentially output from the second time slot T2 of the (i-2) channel two channels before, and the address decimal part is sequentially output from the third time slot T3 of the i channel. As described above, when the external circuit 7 is mounted and “2” is set in the signal OP, the address integer part is output in the (i−2) channel two channels before. .

Next, returning to FIG.
Is calculated by adding the integer part of the F number output from the F number generator 30 and the carry (carry) of the decimal part of the updated address data to calculate the address advance amount ΔI with the maximum value being “4”. Then, the signal is supplied to the delay circuit 40. Delay circuit 4
0, the external instruction signal OP is supplied, the delay time is adjusted in accordance with the external instruction signal OP, and the address advance amount ΔI is adjusted at an appropriate timing by the increment signal generation unit 41 in the subsequent stage. To the generator 42. The delay circuit 40 outputs an integer part of the address data from the address RAM 38 according to the presence or absence of the external circuit 7,
This is to make the timing latched by the latch circuit 45 coincide with the output timing of the address correction value.

The increment signal generator 41 generates increment signals INC1, INC2, INC consisting of 4-bit serial data according to the address advance amount ΔI.
3, INC4 is generated and supplied to a demodulation circuit 64 provided in the external circuit 7. This increment signal IN
C1, INC2, INC3, and INC4 are pulse signals corresponding to the number of compressed waveform data to be reproduced, and the demodulation circuit uses the increment signal INCi (i = 1, 2, 3, 3).
The demodulation operation is performed according to the pulse of 4).

For example, when the address advance amount .DELTA.I is "0", all of the increment signals INC1 to INC4 become "0", and when the address advance amount .DELTA.I is "1", only the increment signal INC1 is "1". Signal IN
C2 to INC4 are "0". Also, the address advance amount Δ
When I is "2", the increment signals INC1 and INC2 are "1" and the other increment signals INC
3, INC4 becomes "0". Further, the address advance amount Δ
When I is "3", the increment signals INC1 to INC1
NC3 becomes “1”, the increment signal INC4 becomes “0”, and when ΔI is “4”, all of the increment signals INC1 to INC4 become “1”.

Address advance amount when reproducing a compressed waveform 圧 縮
Having described the I and INC signals, the case of non-compressed waveform reproduction will now be described. In this case, since the waveform is not compressed, the function of the external circuit 7 for decoding the compressed waveform is not necessary, and only the function of supplying past samples for interpolation is used. This function is used in two sound source configuration (chip signal C2 is "1"),
And with an external circuit 7 (signal OP is not "0"),
In the case of a time-division channel in which four-point interpolation (signal P2 is "0") is selected, in this case, the amount of address advance △
I and INC signals are generated.

In the other cases, the easiest to understand is the case where there is no external circuit 7 (the signal OP is "0"). At this time, the address advance amounts ΔI and IN
Since the C signal is not used, it may be in any manner. On the other hand, with the external circuit 7 (the signal OP is not "0"), the remaining one sound source configuration (the chip signal C2 is "0"),
Alternatively, this is the case of a time division channel in which four-point interpolation (signal P2 is “0”) is selected. In this case, although the external circuit 7 is mounted, the function of the circuit is not required. Therefore, control may be performed so that the waveform read from the waveform memory is directly output from the external circuit 7 with only a predetermined time delay. That is, the access period of the INC signal is irrespective of the value of the address advance amount △ I (the total of four slots in the case of one tone generator configuration, and the first or second half of the second half according to the signal MC in the case of two tone generator configuration). In ()), a pulse is generated unconditionally, and the waveform read in that slot is taken into the external circuit 7.

The return amount generator 42 multiplies the address advance amount ΔI by “−1”, adds “1”, and supplies the result to the selector 43. Therefore,
From the return amount generation unit 42, “1”, “0”, “−1”,
One of the values “−2” and “−3” is output as the return amount. The selector 43 includes the return amount generation unit 42
, And constant values “−3” and “−2” are supplied to the selector 43. In response to the two-point interpolation signal P2 and the chip signal C2, the selector 43 outputs a value supplied from the return amount generation unit 42. , Or "-2" or "-3" is selectively supplied to the bit enlargement unit 44.

Of the three inputs, the return amount generated by the return amount generator is selected when the function of the external circuit 7 is used. That is, with the external circuit 7 (signal OP is not “0”), the sounding channel (signal C
When OMP is “1”, or in a two-sound source configuration (chip signal C2 is “1”) and with an external circuit 7 (signal O
This is the case of a time division channel in which P is not “0”) and four-point interpolation (signal P2 is “0”) is selected. The address advance amount 示 し I indicates how many address integer portions of each time-division channel latched by the latch circuit 45 have advanced by the corresponding address update operation (four channel time ago), while the return amount is The address integer part latched by the latch circuit 45 is stored in the address
A return amount {(-1) * {I + 1}} is generated as a subtraction value for returning to the second address.

On the other hand, the remaining constant values of "-2" and "-3" are selected when the function of the external circuit 7 is not used (that is, when the function is not used). Further, of these two values, “−2” is selected when two-point interpolation is performed in the time division channel (the signal P2 is “1”), and “−3” is selected. Indicates the case where the four-point interpolation is performed (P2 is “0”). The values of “−2” and “−3” are stored in the latch circuit 45 of the interpolated sample by two-point interpolation and four-point interpolation, respectively.
This is a value for making the relative position with respect to the address integer part latched at the same value as the case of the interpolated sample by the four-point interpolation when the external circuit 7 is used.

First, the storage format of the waveform memory 6 for storing 16-bit uncompressed waveform data and compressed waveform data obtained by compressing a 16-bit waveform to 8 bits will be described. The output data width of the waveform memory 6 is 16 bits, and the uncompressed waveform data is sequentially stored at one address and one sample. On the other hand, the storage format of the compressed waveform data is as shown in FIG. 6, and among the successive 8-bit compressed waveform samples, the even-numbered 8-bit sample and the odd-numbered 8-bit sample following it are each 1 bit.
The lower 16 bits and the upper 8 bits of the 6-bit data are combined, and the obtained 16-bit data is stored in the waveform memory 6.
Are sequentially stored at each address. 16 bits to 8
For compression into bits, the secondary LPC method or DPC
The M system is used, and decoding of sequentially supplied compressed waveforms requires decoded playback samples of past compressed waveform samples. That is, in decoding and reproducing the compressed waveform, it is not allowed to skip samples. In the present embodiment, in the case of one sound source configuration, up to four compressed waveform samples can be obtained for each time division channel.
Since only a maximum of three samples can be decoded in the sound source configuration, the value of the above-mentioned F number for the time-division channel for reproducing the compressed waveform is “4” in each case.
Or less and “3” or less. It should be noted that among the addresses in the address RAM 38, the value of the address of the time-division channel from which the compressed waveform is read is not the address of the waveform memory but the number of each sample of the compressed waveform to be read (circled in FIG. 6). Number, 0, 1, 2, ...
.), The read address of the waveform memory advances by “1” each time the address in the RAM 38 advances by “2”. The details will be described later together with the shift-down unit 48.

The address integer part output from the latch circuit 45 shown in FIG. 3 indicates the final address of the waveform data to be read (however, only for two-point interpolation, the phase of the interpolation is matched). Exceptionally not). That is, after the address of a certain time-division channel is latched by the latch circuit 45 and the waveform memory 6 is read, the samples stored before the latched address are already read at least once and reproduced. Have been. As described above, in order to decode a compressed waveform, samples decoded in the past are necessary. In this case, the address of each time-division channel in the address RAM 38 is subjected to the corresponding read decoding. Since the last address of the sample that has already been decoded and played back is shown after
In the processing of the same sounding channel at the time of the next address update, the compressed waveform sample at the address immediately after the address before the update and the compressed waveform sample at the address after the update may be sequentially read and decoded one by one. . The address advance amount △ I output from the half adder 33 indicates how many integer portions of the address of the same sounding channel have advanced in this address update, and corresponds to the number of compressed waveform samples to be decoded in the read after the update. Yes, it is. In accordance with the address advance amount ΔI, the INC generator 41 generates a pulse of the number of samples to be decoded (the number of samples to be updated for an uncompressed waveform) as an increment signal. The integer part of the updated address latched by
, A return amount for returning to the address immediately after the address before update described above is generated. The interpolation in the compressed waveform is performed for four consecutive four samples in the forward direction from the address latched by the latch circuit 45, and the position of the interpolated sample is between the second and third samples.

Next, the value of "-3" selected by the selector 43 when performing four-point interpolation with an uncompressed waveform will be described.
In this case, the address output from the adder 47 is set as the address of the first sample of the four samples, and by the operation of the auxiliary counter 49 and the adder 50 described later, four consecutive samples necessary for the four-point interpolation are divided into one time-division channel. Are sequentially read in four slots. In order to make the relationship between the address integer part latched by the latch circuit 45 and the interpolation sample position the same as the four-point interpolation in the compressed waveform, the latch circuit 45
May be set to be the address of the fourth sample of the four samples. When the value generated by an interpolation counter 49 described later is “0”, “1”, “2”,
Since it is “3”, the addition value in the adder 47 is “−”.
If "3", the output value of the interpolation counter in the adder 50 is combined with "-3", "-2", "-1", "0".
And it will be realized.

On the other hand, the selector 43 selects “−2” for the time division channel of the non-compressed waveform two-point interpolation. In this case, two consecutive samples are needed for interpolation,
Linear interpolation is performed between two consecutive samples sequentially read from the waveform memory 6. As the two samples at this time, it is better to use the middle two of four consecutive samples in the case of four-point interpolation. Because, in the case of four-point interpolation, the position of the sample to be interpolated is between the two middle samples, and the phase of the interpolated sample at the time of two-point interpolation is adjusted to the interpolated sample obtained by the four-point interpolation. Therefore, two-point interpolation is performed on the two samples at the center.
In the case of two-point interpolation, the interpolation counter 49 generates “0” and “1”.
When the two added values are combined, they become "-2" and "-1", which are realized. The reason for adjusting the phase is that the waveform
Since the sample position changes depending on whether the point interpolation or the two-point interpolation is used, for example, when two waveforms are mixed, the timbre is largely prevented from being changed by switching the waveform interpolation method. is there.

The bit number expansion section 44 is a circuit for sign-extending the number of bits of various data (about 4 bits) output from the selector 43 to the number of operation bits (about 16 to 20 bits) in the adder 47.

As described above, the least significant bit (1 bit) of the address integer part corrected by the adder 47 is the signal O.
DD is supplied to the external circuit 7, and all bits including that bit are supplied to the shift-down unit 48. The signal ODD is a signal for instructing whether to extract from the lower 8 bits or the upper 8 bits when extracting 8-bit compressed waveform data from the 16-bit waveform memory 6. The shift-down unit 48 sets the compression signal COMP to “1”.
, The address data is shifted down by one bit and supplied to the adder 50.

In the time-division channel from which the compressed waveform is read, the address integer part output from the adding circuit 47 is shifted down by one bit in the shift-down unit 48. As a result of the downshift, each time the address in the latch circuit 45 or the adder 47 advances by “2”, an address that advances by “1” is generated and output from the downshift unit. That is,
The address indicating each sample number of the compressed waveform is converted into an address for reading out the waveform memory 6 in the shift-down unit 48.

The interpolation counter 49 is used to sequentially read out four points of waveform data (interpolation data),
A counter for advancing the address in order to sequentially read out two points of waveform data for each of two sound sources. When the sound source is one chip, "0", "1", "2", "3"
Are sequentially supplied to the adder 50 in four slots of one channel, and when the sound source is two chips, “0”,
The values “1”, “0”, and “1” are sequentially supplied to the adder 50 in the same four slots.

The adder 50 adds a start address to the address data, and “0”, “1”, “2” supplied from the interpolation counter 49 at the timing of four slots of each time division channel. , "3"
(Or “0”, “1”, “0”, “1”) are added, and address data for four points are sequentially created and supplied to the gate circuit 51. The gate circuit 51 controls the output timing of the address data for the above-mentioned four points.
In the case of a chip, only the first two time slots of the address data are opened for the sound source on the master side,
For the sound source on the slave side, the second half of the address data
Only the time slot is open. Therefore, of the access time of the waveform memory 6, that is, of the four slots for each four channels, the former two slots are used by the master side and the latter two slots are used by the slave side sound source.
The address data thus obtained is stored in the waveform memory 6
Supplied to The waveform data is read from the waveform memory 6 in accordance with the address data and supplied to the external circuit 7.

(5) Configuration of External Circuit Next, the external circuit 7 will be described with reference to FIG.
FIG. 5 is a block diagram showing the configuration of the external circuit 7. In the figure, a delay circuit 55 delays the waveform data (16 bits) read from the waveform memory 6 by one time slot, supplies the delayed data to a delay circuit 56, and a selector 57.
To one of the input terminals. The delay circuit 56 delays the waveform data (for four points) output from the delay circuit 55 by two time slots and sequentially supplies the delayed data to the other input terminal of the selector 57.

The selector 57 normally outputs the output of the delay circuit 56, that is, the waveform data (4) delayed by two time slots (three time slots including the delay of the delay circuit 55).
In the case where a two-chip sound source is used, a delay circuit 55 is provided by the external circuit 7 on the slave side.
, That is, the waveform data (for four points) delayed by one time slot is sequentially output to the subsequent stage. This means that when a two-chip sound source is used, the external circuit on the master
Of the waveform data for the points, the first two points (I, II) are used, and the external circuit on the slave side determines the timing of supplying the first two points of the waveform data for four points by two points. The latter two points (III,
IV). Therefore, the selector 57
Of the four time slots, the master side using the first two time slots outputs the waveform data delayed by the delay circuit 56, and the slave side using the latter two time slots outputs the waveform data output from the delay circuit 55. It is supposed to.

Next, the selector 58 selects one of the upper 8 bits or lower 8 bits of the waveform data supplied directly from the selector 57, or the delay circuits 59, 60, 6
The upper 8 bits or lower 8 bits of the waveform data delayed by one time slot by 1 are selectively output as the lower 8 bits of the final waveform data.

Here, the output selection of the selector 58 will be described with reference to FIG. FIG. 7 is a diagram for explaining the operation when reading out 8-bit compressed waveform data in each time-division channel from the 16-bit waveform memory 6. As shown in FIG. 7A, the 16-bit waveform memory 6 sequentially stores compressed waveform data compressed to 8 bits for each of the lower 8 bits and the upper 8 bits of each address as described above. Have been. The waveform memory 6 stores 16-bit waveform data (2
(Including two compressed waveform data). Therefore, from this waveform memory 6, 8 as shown in FIG.
In order to sequentially take out compressed bit waveform data, it is necessary to distribute the 16-bit length waveform data at a predetermined timing. That is, since the first and second compressed waveform data (16 bits) are supplied to the selector 58 shown in FIG. 5 at the same timing, the signal ODD becomes “0”.
In other words, when the first compressed sample to be decoded is included in the lower 8 bits of the first read data, the input terminal A outputs the first compressed waveform data in the first slot of the time division channel. It is sufficient to output the lower 8 bits of data directly supplied to.

Next, in order to output the second compressed waveform data in the second slot, the upper 8 bits of the same read data delayed by one time slot may be output. Therefore, the delay circuit 5 supplied to the input terminal D
It is sufficient to output the data of the upper 8 bits delayed by one time slot output by 9. Next, since the third compressed waveform data is included in the lower 8 bits of the read data read second from the waveform memory, the data is output by delaying one time slot in the third slot. It is sufficient to output the lower 8 bits of the data, that is, the lower 8 bits of data supplied from the delay circuit 60 to the input terminal C. Further, in order to output the fourth compressed waveform data, the upper 8 bits of data delayed by two time slots in the fourth slot, that is, from the delay circuit 61 to the input terminal E
, The upper 8 bits of the data supplied to the data processor may be output.

On the other hand, when the signal ODD is “1”, that is, when the first compressed sample to be decoded is included in the upper 8 bits of the first read data, the selector 58 sets the signal in FIG. ) To the right of
In the first to fourth slots of each time division channel,
What is necessary is just to output sequentially in the order of the input terminals B, A, D and C. When reading uncompressed waveform data,
With the gate circuit 62 in the open state, the upper 8 bits of data output from the selector 57 are output to the subsequent stage, and the lower 8 bits supplied to the input terminal A by the selector 58 are output.
The bit data may be output to the subsequent stage. By this selection, the data separated into the upper 8 bits and the lower 8 bits at the output of the selector 57 are combined again into 16 bits immediately before the nonlinear extension section 63. The compressed waveform data or the non-compressed waveform data output from the selector 58 is supplied to the non-linear expansion unit 63. The waveform data is
In the case of compressed waveform data, it is 8-bit data output by the selector, and in the case of uncompressed waveform data,
This becomes 16-bit data obtained by adding the upper 8 bits supplied via the gate circuit 62.

Next, when the compressed signal COMP is “1”, that is, when a compressed waveform sample is supplied, the non-linear expansion unit 63 converts the 8-bit compressed waveform data from a log (logarithmic value) to a linear (linear value). )
After the code is expanded and converted into 16-bit length waveform data, it is supplied to the demodulation circuit 64. That is, in addition to the above-described compression by the secondary LPC or DPCM, the residual waveform generated by the secondary LPC or DPCM is further subjected to linear-to-logarithmic conversion, and the compressed 8-bit waveform stored in the waveform memory 6. That is to say. On the other hand, when the compression signal COMP is “0”, the supplied 16-bit uncompressed waveform data is supplied to the demodulation circuit 64 as it is.

Inside the demodulation circuit 64, based on the supplied compressed waveform data and the previously demodulated waveform data,
Waveform data is demodulated. In particular, in the case of compressed waveform data by secondary LPC, when differential data (compressed data) is input, demodulated waveform data delayed by one sampling period (= 32 channel time) and two sampling periods After multiplying the demodulated waveform data delayed by the minute with the coefficients A0 and A1, the result of the multiplication is added to the difference data to demodulate the waveform data.

(6) Configuration of Demodulation Circuit Here, the demodulation circuit 64 will be described with reference to FIG. FIG. 8 is a block diagram illustrating a configuration example of the demodulation circuit. In the figure, a buffer RAM 70 stores demodulated waveform data for four points of each channel supplied to an input terminal DI at a predetermined timing, and sequentially stores the stored waveform data for four points. The data is read out and supplied to the illustrated latch circuits 71, 72, 73, 74.
The waveform data of one sampling cycle before is supplied to the latch circuit 71, the waveform data of two sampling cycles before is supplied to the latch circuit 72, the waveform data of three sampling cycles before, and the latch circuit 74. Is
The oldest waveform data before four sampling periods is supplied. That is, the waveform data of four points demodulated in the past for each channel are sequentially latched by the latches 71 to 74.
The latch circuits 71 to 74 temporarily hold the supplied waveform data, respectively, and supply them to the first input terminals of the selectors 75 to 78.

The read address and write address of the buffer RAM 70 are generated by a channel counter 80, a delay circuit 81, and a selector 82. The channel counter 80 generates a count value indicating a channel “1”, “2”,... At a predetermined timing, and supplies it to one input terminal of the selector 82 and the delay circuit 81. The delay circuit 81 delays the count value by eight slots (= two channels) and supplies the delayed count value to the other input terminal of the selector 82. Also, the selector 82
Supplies the count value directly supplied from the channel counter 80 to the buffer RAM 70 as a read address, and supplies the count value delayed by 8 slots supplied from the delay circuit 81 to the buffer RAM 70 as a write address.

The selectors 75 to 78 include delay circuits 83 and 8
4, 85, 86, and selectively outputs any of the data supplied to the three input terminals in response to the pulses of the first to third slots of the increment signal INC described above. Output to the delay circuit. The outputs of the selectors 75 and 76 are also supplied to multipliers 87 and 88 together with the delay circuits 83 and 84, respectively. Multipliers 87 and 88 have LPC demodulation coefficients A
0 and A1 are supplied. The outputs of the selectors 75 and 76 are multiplied by these LPC demodulation coefficients A0 and A1 and supplied to an adder 89. The adder 89 adds the output data of the multipliers 87 and 88 and outputs the result as the prediction data by the gate circuit 90.
Supply to The gate circuit 90 is opened only when the compression signal COMP is “1”, and supplies the output of the adder 89 to one input terminal of the adder 91. The other input terminal of the adder 91 is supplied with the waveform data output from the above-described non-linear expansion section 63.
Adds the original waveform data and the prediction data and supplies the result to the delay circuit 92. The delay circuit 92 delays the added waveform data by one time slot, and then supplies the delayed waveform data to the second input terminal of the selector 75 described above.

The outputs of the delay circuits 83 to 76 are
These are supplied to the second input terminal of the next-stage selector and the third input terminal of the previous-stage selector, respectively, and the third input terminal of the previous-stage selector and the third-stage input terminal of the next-stage selector shown in the upper part of the drawing. 2 input terminals.
Selectors 93, 94, 95, 96 shown in the upper part of the drawing
Are connected in cascade via delay circuits 97, 98, 99, and 100 in the same manner as the above-described selectors 75 to 78 at the lower stage. 3 in sequential feed operation
One of the data supplied to one input terminal is selectively output to a delay circuit at a subsequent stage. Delay circuit 9
The outputs 7 to 100 are supplied to the first input terminals of the next-stage selector. The output of the delay circuit 100 at the last stage is written into the buffer RAM 70 at the above-described timing, and is also output to the interpolation unit 19 shown in FIG.

(7) Configuration of Interpolator Next, the configuration of the interpolator 19 will be described with reference to FIG. FIG. 9 is a block diagram showing one configuration of the interpolation unit 19 in the present embodiment. In the figure, an address fraction output from an address generator 18 is a subtractor 102
, The bit inverter 104, and the third input terminal of the selector 105. In this embodiment, the interpolation counter 101 has “1”, “2”, “3”,
A cyclic sequence "4" is generated and supplied to the other input terminal of the subtractor 102 at a predetermined timing. The above "1"
Numerical values of “〜” to “4” are output corresponding to each of the waveform data of four points. The subtracter 102 subtracts the decimal part of the address from each value of “1” to “4”, and supplies the result to the coefficient memory 103. The interpolation coefficient shown in FIG. 10A is stored in the coefficient memory 103, and the interpolation coefficient corresponding to the value supplied from the subtracter 102 is supplied to the first input terminal of the selector 105.

Further, the bit inverter 104 inverts the above-mentioned address decimal part in bit units, and
To the second input of The selector 105 controls the first point in accordance with the values of the two-point interpolation signal P2 and the master signal MC.
To the third input terminal to one input terminal of the multiplier 107. In the case of four-point interpolation, the two-point interpolation signal P2 becomes “0”. In this case, the selector 105 outputs the interpolation coefficient supplied from the coefficient memory 103.

When two points are interpolated by each sound source in a two sound source configuration, the two-point interpolation signal P2 is always "1" and the master signal MC is "1" in the time-division channel for the two-point interpolation. In the case of "1", the input timing of the waveform data of the first two slots is used, and in the case of "0", the input timing of the waveform data of the second two slots is used.
In this case, the selector 105 sequentially switches the bit inverters 1 in synchronization with the waveform data of the first half and the waveform data of the second half.
Bit-reversed address fraction supplied from 04,
The directly supplied address decimal part is output to the multiplier 107. By this operation, the coefficient at the time of the two-point interpolation shown in FIG.

The delay circuit 106 sequentially delays the waveform data supplied for each time slot, and
Output to The multiplier 107 multiplies each waveform data by the corresponding data (coefficient, inverted address decimal part or address decimal part), and supplies it to the interpolation accumulator 108. After accumulating the waveform data, the interpolation accumulator 108 outputs one obtained interpolation sample to the envelope multiplying unit 21 shown in FIG. 1 for each time division channel.

(8) Description of Operation Next, the operation of the above-described musical sound generating apparatus of this embodiment will be described with reference to FIGS. When the performer sets a tone using the tone switch 2 and plays the keyboard, performance information such as key codes and touches corresponding to the performance is supplied to the control unit 3. Then, by the control unit 3,
Various information is supplied to the register group 12 via the interface 11. Each of the register groups 12 supplies the above-described various signals to each unit according to the number of sound sources and the presence or absence of an external circuit. Note that the tone color setting and the performance by operating the keyboard are common operations in each case, and the description thereof will be omitted below. In the following, FIGS.
The configuration shown in (d) will be described as cases A, B, C, and D, respectively.

(8-1) Case A First, as shown in FIG. 2A, a case in which the external circuit 7 is not attached and one sound source 8 produces sound will be described. In this case, the external instruction signal OP = 0, the chip signal C2 = 0, and the master signal MC = 1, and the musical sound is generated by 32 channels by four-point interpolation. In this case, no compressed waveform is used.

In the address generator 18, since the external instruction signal OP supplied to the offset generator 36 is "0", the offset values output in the time slots T1 to T4 are "+4", " 0 ”,“ 0 ”,“ + ”
4 ". Accordingly, in the address RAM 38, in the time slot T1, the address data of the channel four channels ahead is read out from the address RAM 38, output from the output terminal DO to the latch circuit 39, and latched (see "External Circuit" in FIG. 4). Is not installed ").

Next, in the time slots T2 and T3, since the offset value is "0", the address data of its own channel is read from the address RAM 38, and the address integer part is latched by the latch circuit 45.
The address decimal part is latched by the latch circuit 46. Between the time slots T2 and T3, the time slot T1
In the address data latched by the latch circuit 39, the address integer part thereof is supplied to the full adder 31 and the address decimal part is supplied to the full adder 32. Then, it is added to and updated with the F number read out from the F number generation unit 30 according to the pitch data, and is supplied to the address control unit 34. The address control unit 34 performs a predetermined process such as a loop reading process on the updated address data (integer part and decimal part) in accordance with the address control data, and then executes address RAM processing.
It is supplied to an input DI at 38.

Then, in the time slot T4, the updated address data supplied from the address control unit 34 is stored in the address of the address RAM 38 corresponding to the channel four channels ahead. That is, in this case, the update of the address data of each channel is
This is performed in time slots T1 and T4 in the future channel processing for four channels, and the address data of each channel is stored in the time slot T in the corresponding channel processing.
2, T3. The integer part of the address data is supplied to the adder 47 via the latch circuit 45.

On the other hand, in this case, chip signals C2 and 2
Since both the point interpolation signals P2 are “0”, the selector 43
Is output as “−3”, the bit is expanded in the bit enlargement unit 44, and then supplied to the adder 47. The adder 47 adds the address correction value to the address integer part. The corrected address integer part is supplied to the shift-down part 48. This is a case where uncompressed waveform data is read, and the compressed signal COMP becomes “0”.
The data is directly supplied to the adder 50 without being shifted down by the shift-down unit 48.

The adder 50 adds the start address and the interpolation count value from the interpolation counter 49 to the address integer part output from the shift-down unit 48, and supplies the result to the gate circuit 51. In this case, since the interpolation is four-point interpolation, the interpolation counter 49 outputs “0”, “1”, “2”,
The count value "3" is sequentially output. Then, the address data for four points of the start address + address integer part + interpolation count value is supplied to the waveform memory 6 via the gate circuit 51. As described above, the address of the waveform data to be read is obtained by adding the start address of each time-division channel and the address latched by the latch circuit 45 to the total values “−3” and “3” supplied from the selector 43 and the interpolation counter 49. -2 "," -1 ", and" 0 ".

The waveform data (for four points) is read from the waveform memory 6 in accordance with the address data and supplied to the interpolation unit 19 of the sound source 8. In this case, the interpolation unit 19
Because of the point interpolation, the coefficients (for four points) output from the coefficient memory 103 are sequentially output from the selector 105 and supplied to the multiplier 107. Further, the delay circuit 1 of the interpolation unit 19
To 06, the waveform data of four points read from the waveform memory 6 described above are sequentially supplied. Therefore, the waveform data read in the four slots of each time-division channel is multiplied by the corresponding coefficient in the multiplier 107, and then accumulated in the interpolation accumulator 108. The resulting waveform data is supplied to the envelope multiplication unit 21 shown in FIG. This timing is shown in "during 4-point interpolation" in FIG.

On the other hand, in the envelope generating section 20, envelopes for 32 channels are sequentially generated in accordance with the envelope control signal supplied from the envelope control register 17, and the envelopes are supplied to the envelope generating and multiplying section 21. Then, the envelope multiplication unit 21 adds the envelope to the interpolated waveform data for each time-division channel, and the channel accumulation unit 22 mixes the waveform data for 32 channels. After being converted into an analog signal by the DAC 23, the sound signal is generated as a musical tone in the sound system 10. In the configuration of Case A described above, there is no limitation on the pitch of the tones to be generated.

(8-2) Case B Next, as shown in FIG. 2 (b), a case where the external circuit 7 is not mounted and two sound sources 8a and 8b emit sound will be described. In this case, the external instruction signal OP = 0 and the chip signal C2 =
1, and the master signal MC = 1, while the external instruction signal OP = 0, the chip signal C2 = 1, and the master signal MC = 0 for the sound source 8b on the slave side. In this case, sound generation for 64 channels is performed by two-point interpolation (the signals P2 of all time division channels are all “1”). Also in this case, the compressed waveform data is not used (all signals COMP are “0”) as in the case A. Also,
The operation up to the latch circuit 45 in the address generator 18 in each of the sound sources 8a and 8b is the same as that in the case described above, and the description is omitted.

As described above, the selector 43 always selects "-2" for the time-division channel of the two-point interpolation (P2 is "1"). Further, since the compressed waveform is not used, the shift-down unit 48 outputs the input address as it is. As a result, the address output from the shift-down unit 48 is a value obtained by adding “−2” output from the selector 43 to the address latched by the latch circuit 45. In the following description of case B, the configuration requirements of each of the two sound source configurations will be distinguished by subscripts a and b.

First, in the master-side sound source 8a, the adder 50a of the address generator 18a adds the start address and the interpolation count value from the interpolation counter to the address integer part, and supplies the result to the gate circuit 51a. In this case, since two-point interpolation is performed, count values of “0”, “1”, “0”, and “1” are output from the interpolation counter 49a. Further, since there are two sound sources (signal C2 is "1"), the gate circuit 51a on the master side is open only during the first two points, and the time slots T1, T2
Are supplied to the waveform memory 6. On the other hand, in the sound source 8b on the slave side, since the gate circuit 51b is open only during the latter two points,
Address data for two points of the time slots T3 and T4 are supplied to the waveform memory 6.

That is, the address inputted to the gate circuits 51a and 51b is the sum of the adder "-" of the adder 47.
The values obtained by adding “−2”, “−1”, “−2”, and “−1” to the address latched by the latch circuit 45, including “2”, are supplied in the time slots T1 to T4. .
In the gate circuit 51a on the master side, the first two
The slot circuit is output, and the gate circuit 51b on the slave side outputs the latter two slots. However, in the access time for the two slots of the waveform memory, which is allowed on both the master side and the slave side, the latch circuit Two addresses "-2" and "-1" are output with respect to the address latched at 45.

From the waveform memory 6, four points of waveform data are read out according to the address data of the four slots before the output on the master side and the two after the output on the slave side. The signal is supplied to the interpolation unit 19a, and is also supplied to the interpolation unit 19b of the sound source 8b on the slave side. In this case, since the master signal MC is “1” in the master-side interpolation unit 19a, the bit-inverted address decimal part output from the bit inverter 104 is output from the selector 105 in the time slot T1. , In the second time slot T2,
The directly supplied address fraction is output. By this operation, the coefficients of the two-point interpolation for the sound source 8a on the master side are supplied, and in the remaining time slots of T3 and T4,
The selector 105 does not select any input (that is, outputs “0”).

Similarly, in the slave-side interpolation unit 19b,
Since the master signal MC is “0”, the first half of T1 and T1
In the time slot T2, "0" is output, and in the time slot T3, the bit-reversed address fraction supplied from the bit inverter 104 is output. In the next time slot T4, the address is directly supplied. The output fractional part is output. By this operation, two-point interpolation coefficients for the sound source 8b on the slave side are supplied in the latter two slots of the four slots of one channel.

On the other hand, the waveform data for the four points read from the waveform memory 6 is sequentially supplied to the delay circuit 106a of the master-side interpolation unit 19a. The multiplier 107a multiplies the waveform data for two points supplied in the first two slots by the corresponding interpolation coefficient, and accumulates the data by the interpolation accumulator 108a.
The interpolated waveform data is supplied to the envelope multiplier 21a shown in FIG. Similarly, on the slave side, among the waveform data read from the waveform memory 6, the multiplier 107 b compares the corresponding interpolation coefficient with the waveform data for two points read in the latter two slots. After being multiplied, they are accumulated by the interpolation accumulator 108b,
The interpolated waveform data is supplied to the envelope multiplier 21b of the sound source 8b.

In each of the sound sources 8a and 8b, the envelope generators 20a and 20b sequentially generate the envelopes for a total of 32 channels (a total of 64 channels) in accordance with the envelope control signals supplied from the envelope control registers 17a and 17b. The generated envelope is supplied to the envelope generating and multiplying units 21a and 21b. Then, in the envelope multiplying units 21a and 21b, the envelope is added to the interpolated waveform data of each time-division channel, and the channel accumulating unit 2
In 2a and 22b, waveform data for 32 channels are mixed and converted into analog signals by the DACs 23a and 23b, and then the sound systems 10a and 1b.
0b is pronounced as a musical tone. In the configuration of Case B described above, there is no limitation on the pitch of the tones to be generated.

(8-3) Case C Next, a case where one external circuit 7 is attached to one sound source 8 as shown in FIG. 2C will be described. In this case, the external instruction signal OP = 1, the chip signal C2 = 0, and the master signal MC = 1, and sound is generated for 32 channels by four-point interpolation. In addition,
In this case, since the external circuit 7 is mounted, it is possible to generate a tone for both the non-compressed waveform data and the compressed waveform data in each time-division channel.

First, in the address generator 18, the external instruction signal OP supplied to the offset generator 36 is “2”.
Therefore, the offset values output in the time slots T1 to T4 are “+4”, “+2”,
"0" and "+4". Therefore, the address RAM
At 38, in a first time slot T1,
The address data of the channel four channels ahead is read from the address RAM 38 and latched by the latch circuit 39 from the output terminal DO.

Next, in the next second time slot T2, since the offset value is "2", the address integer part two channels ahead is read from the address RAM 38 and latched by the latch circuit 45. . And the third
In the time slot T3, since the offset value is "0", the address decimal part of its own channel is read from the address RAM 38, and the latch circuit 4
6 is latched. Between these time slots T2 and T3, the address integer part of the address data four channels ahead latched by the latch circuit 39 in the time slot T1 is supplied to the full adder 31, and the decimal part of the address data is supplied to the full adder 32. Supplied to Then, the F number generating unit 3
The updated address data (integer part, decimal part) added to the F number read from 0 in accordance with the pitch data is subjected to control according to the control data by the address control unit 34, and then updated. Input terminal DI of RAM38
Supplied to

In the fourth time slot T4, the updated address data is stored in the address RAM3.
8 is stored in the address corresponding to the channel four channels ahead. That is, in this case, the update of the address data of each channel is performed in the time slots T1 and T4 in the future channel processing of four channels, and the address integer part of each channel is the time in the future channel processing of two channels. In addition to being output in slot T2, the fractional part of the address is output in the third time slot T3 of the corresponding channel.

In this case, the address correction value supplied from the selector 43 changes depending on whether the waveform read out in each time division channel is a compressed waveform (whether the signal COMP is "1"). In the case of a compressed waveform, the selector 43
Always selects the return amount output from the return amount generation unit 42. On the other hand, in the case of an uncompressed waveform, two-point interpolation can also be selected, so that “−2” may be selected in the selector 43. , And outputs a constant value “−3”.

After the bits are expanded in the bit expansion section 44, the bits are supplied to the adder 47. The address correction value is added to the address integer part by the adder 47. The corrected address integer part is supplied to the shift-down part 48, and the least significant bit is the signal O.
It is supplied to the interpolation unit 19 as DD. When the compressed waveform data is read, the address integer part is supplied to the adder 50 after being shifted down by one bit because the compression signal COMP becomes “1”.

The address integer part two channels before is:
The start address and the interpolation count value from the interpolation counter are added by the adder 50 and supplied to the gate circuit 51. In this case, since the sound source is one chip, the interpolation counter 49 sequentially outputs “0”,
The count values “1”, “2”, and “3” are output. Further, the gate circuit 51 is opened over all time slots, and the start address + address integer part +
The address data for four points, which is the interpolation count value, is supplied to the waveform memory 6 via the gate circuit 51.

As described above, since the address correction value supplied from the selector 43 differs depending on the compression state of the waveform read out in each time-division channel, the address data for four points output here is also different. , Different data is output according to the data. First, there are four addresses that are output on the time-division channel during which the compressed waveform is being reproduced. The sample, that is, four consecutive addresses starting from the address containing the sample to be decoded next.
In other words, one data read in the first slot of each time-division channel contains a sample to be decoded next, and data for the next three addresses is read over the remaining three slots. You. On the other hand, in the case of a time division channel for reproducing an uncompressed waveform,
The four addresses output at this time are the addresses of four samples for four-point interpolation as they are. As described above, these four addresses are consecutive 4
Address.

The waveform data (for four points) is read from the waveform memory 6 in accordance with the address data and supplied to the external circuit 7. In the external circuit 7, since the signal C2 is "0", the output of the delay circuit 56, that is, the waveform data (for four points) delayed by two time slots is output from the selector 57 (see "demodulation" in FIG. 11). Circuit input "). Next, the operation of the selector 58 in the time-division channel where the compressed waveform is being reproduced will be described. From the selector 58, when the signal ODD is "0", the input terminals A, D, C, and E are sequentially output in four time slots of the time division channel.
The waveform data is output in this order. As a result, FIG.
As shown in the figure, the first waveform data (I), the second waveform data (II), and then the third waveform data (II)
I), and the fourth waveform data (IV) is output. On the other hand, when the signal ODD is "1", the selector outputs the input terminals B, A,
Waveform data is output in the order of D and C. The waveform data (8 bits each) output from the selector 58 is sequentially supplied to the non-linear expansion unit 63, converted into 16-bit data, and then supplied to the demodulation circuit 64 shown in FIG.

On the other hand, in the time-division channel in which the non-compressed waveform is output from the selector 57, the selector 58 selects and outputs the input terminal A, and the gate 62 is opened. The high-order 8 bits output from the selector 62 are combined, and the 16-bit data output from the selector 57 is directly used as the nonlinear expansion unit 63.
Supplied to The non-linear expansion unit 63 outputs the 16-bit uncompressed waveform to the demodulation circuit 64 without performing any processing.

The operation of the demodulation circuit 64 in the time division channel for reproducing the compressed waveform of the secondary LPC will be described. In the demodulation circuit 64, the last four points of the already reproduced waveform data are read from the buffer RAM 70 in the reproduction processing of the previous channel, and the latches 71, 72, 73, 74 are sequentially arranged in the newest order. Is held in. Then, in the first time slot of the current channel in the selectors 75 to 78, the lower selectors 75 to 78 are connected to the first input terminal (the upper input terminal),
The waveform data held by 1 to 74 are sequentially output to the subsequent delay circuits 83 to 86 (“selector a” in FIG. 11).
Above). The data output from each of the selectors 75 to 78 is delayed by one time slot by the delay circuits 83 to 86, and then supplied again to the third input terminal of the previous-stage selector. In particular, the outputs of the selectors 75 and 76 are multiplied by coefficients A0 and A1 in multipliers 87 and 88, and then added in an adder 89. And the delay circuit 9
After being delayed by 2, the signal is supplied to the second input terminal of the selector 75.

As described above, the data selectively output by the selector 75 is the waveform data demodulated and reproduced immediately before, and the output data of the selector 76 is the waveform data demodulated immediately before. Are multiplied by the coefficients A0 and A1 and added to the compressed waveform data input by the adder 91 to demodulate the secondary LPC-compressed data. Output sequentially. When the input waveform is a compressed waveform of DPCM compression, the coefficients A0 and A1 of the time division channel are used.
It is sufficient to supply the values of “1” and “0”, respectively.

Then, in the next time slot, each of the selectors 75 to 78 outputs the second signal according to the state of the increment signal INC1 supplied from the address generator 18.
Alternatively, the data supplied to the third input terminal is output to a subsequent circuit (see “x1 of selector a” in FIG. 11).
When the increment signal INC1 is “1”, the second
Is selectively output to the subsequent circuit, and when the increment signal INC1 is "0", the data supplied to the third input terminal is selectively output to the subsequent circuit. . That is, the increment signal IN
When C is "1", it is necessary to update the data, and the data supplied from the delay at the previous stage of each selector is output to the delay at the subsequent stage. on the other hand,
When the increment signal INC1 is "0", there is no need to update the data, and the data output from the delay at the subsequent stage of the selector is returned to that delay again, and the output of each delay was output in the previous time slot. The data will be output again. Hereinafter, the above processing is performed from the increment signal INC1 to the increment signal INC3 according to the state of each increment signal (see “selector a” and “increment signal INC” in FIG. 11).

That is, to the adder 91 of the demodulation circuit 64, the 8-bit compressed waveform data for four samples is sequentially supplied from the non-linear expansion section, while the compressed waveform to be decoded is supplied from the INC generation section 41 of the sound source 8. Since pulses equal to the number of data are supplied as the INC signal, the signal I
Forwarding is performed by the number of signals of “1” among NC1 to NC3, and demodulated samples output from the adder 91 are sequentially taken into the delay groups 83 to 86 after passing through the delay 92. The processing of the time division channel in the lower selectors 75 to 78 ends in the time slot of the signal INC3, and the next time slot shifts to the next time division channel processing. On the other hand, in the upper selectors 93 to 96, the processing of the time division channel is performed for a period of four consecutive time slots from the time slot of the next signal INC4.

When the increment signal INC4 is supplied, the upper selectors 93 to 96 supply the lower delay circuits 83 to 96 to the second or third input terminals in the time slot in accordance with the increment signal INC4.
86 is selectively supplied to the subsequent delay circuit 9
7 to 100 (see "selector b" and "increment signal INC" in FIG. 11). That is, when the increment signal INC4 is "1", the data is updated, and the data supplied to the second input terminal, that is, the lower delays 92, 83, 84, 85
Are selectively output to the subsequent delay circuits 97 to 100, respectively. On the other hand, when the increment signal INC4 is "0", there is no need to update the data, and the data supplied to the third input terminal, that is, the waveform data output from the lower-stage delays 83 to 86 are selectively output. It is output to the delay circuits 97 to 100 at the subsequent stage.

Of the four samples of waveform data taken into the delays 97 to 100 in the time slot of the signal INC4, the same number of samples as the number of slots that were “1” in the four-slot INC signal were used in this time. The data is newly demodulated in the processing of the time division channel, and the rest is the data already demodulated in the processing of the previous simultaneous division channel. The reproduced waveform data of these four samples is supplied to the demodulation circuit 6 over a period of four successive slots.
At the same time as the data output from the channel 4, the data is sequentially written in the waveform sample buffer RAM 70 at a position corresponding to the channel as data of four samples reproduced in the past of the channel.

Therefore, after the next time slot of the signal INC4, the upper selectors 93 to 96 always select the data supplied to the first input terminal (the upper input terminal) and send the data to the subsequent delay circuits 97 to 100. Output sequentially (see "selector b" in FIG. 11). That is, the selector 93 outputs “0”, and the selectors 94 to 96 output the data from the preceding delay circuit to the subsequent delay circuit. Therefore, the last-stage delay circuit 100 sequentially outputs the demodulated waveform data of four points in the order of chronological order.
M70, and is output as output waveform data of the demodulation circuit 64 (“buffer R” in FIG. 11).
AM ").

Next, the operation of the demodulation unit 64 in a time division channel for reproducing an uncompressed waveform will be described. Since four-point interpolation is to be performed, H-compressed waveform data for four points required for interpolation is sequentially supplied to the demodulation unit 64 from the non-linear expansion unit in the time-division channel. In this case, one sound source configuration (signal C2 is "0")
Since the channel has a four-point interpolation (the signal P2 is "0") and an uncompressed waveform (the signal COMP is "0"), the INC signal generator generates all four pulses. The operation of the demodulation circuit 64 is the same as in the case of the above-described channel of the compressed waveform, but in this case, the signal COMP becomes “0”.
Therefore, the gate 90 is closed, and the adder 91 is closed.
Output uncompressed data for four points sequentially supplied to one of the inputs. The uncompressed waveform data that has passed through the adder 91 is first taken in by delays 83 to 85 in order according to the signals INC1 to INC3 in which the preceding three points are all "1", and the subsequent values of "1" In response to the signal INC4, it is taken into the upper-stage delays 97 to 100 together with the last input waveform data of the fourth point. The captured four points of uncompressed waveform data are sequentially output from the delay 100 and written into the buffer RAM 70 at the same timing as the four slots as in the case of the compressed waveform data, and simultaneously as output waveform data of the demodulation circuit 64. Is output.

The waveform data for the four points demodulated by the demodulation circuit 64 is supplied to the interpolation unit 19 of the sound source 8 shown in FIG. In this case, the two-point interpolation signal P2 is "0" because of the four-point interpolation. Therefore, the selector 105 of the interpolation unit 19 outputs the interpolation coefficient from the coefficient memory 103 supplied to the first input terminal (upper input terminal) (“4 point interpolation (P2 = 0)” in FIG. 12). See). Each waveform data is multiplied by the corresponding interpolation coefficient in the multiplier 107, and then accumulated in the interpolation accumulator 108. The multiplied envelope data shown in FIG. It is supplied to the unit 21.

On the other hand, in the envelope generation section 20, envelopes for 32 channels are sequentially generated in accordance with the envelope control signal supplied from the envelope control register 17, and the envelope is supplied to the envelope generation multiplication section 21. Then, in the envelope multiplication unit 21, the envelope is added to the interpolated waveform data for each time-division channel, and the waveform data for 32 channels is mixed in the channel accumulation unit 22 to obtain one sampling period. After each mixing waveform data is generated and converted into an analog signal by the DAC 23, it is generated as a musical tone in the sound system 10.

In the configuration of case C described above, 16
In the case of bit data (uncompressed), there is no limit on the pitch of the tones to be generated. Occurs. This is because, in the present embodiment, only up to four points of compressed waveform data can be decoded for each time-division channel, and skipping is not allowed when decoding compressed waveform data.

(8-4) Case D Next, as shown in FIG. 2D, the two sound sources 8a and 8b
The case where one external circuit 7a, 7b is attached to each of them will be described. In this case, the external instruction signal OP = 2, the chip signal C2 = 1, and the master signal MC = 1 for the master sound source 8a, while the external sound signal 8b for the slave sound source 8b. The attachment instruction signal OP = 2, the chip signal C2 = 1, and the master signal MC = 0. In this case, the sound sources 8a and 8b generate sounds for 32 channels by four-point interpolation, and generate sounds for a total of 64 channels.

First, in the address generation section 18a of the master-side sound source 8a, the external instruction signal OP supplied to the offset generation section 36a is "2". Sequentially become "+4", "+2", "0", and "+4". Therefore, in the time slot T1, the address data of the channel four channels ahead is read from the address RAM 38a and latched by the latch circuit 32a.

Next, in the time slot T2, since the offset value is "2", the address integer part two channels ahead is read from the address RAM 38a and latched by the latch circuit 39a. In the time slot T3, since the offset value is “0”, the address decimal part of its own channel is the address R.
The data is read from the AM 38 a and latched by the latch circuit 46. Between these time slots T2 and T3,
In the time slot T1, the address data of four channels ahead of the address data latched by the latch circuit 39 is supplied to the full adder 31a, and the fractional part of the address is supplied to the full adder 32a. The updated address data (integer part, decimal part) is added to and updated with the F number output by the F number generation unit 30a.
After being processed in the address control section 34a in accordance with the address control data, it is supplied to the input terminal DI of the address RAM 38a.

Then, in the time slot T4, the updated address data is stored in the address corresponding to the channel four channels ahead in the address RAM 38a. That is, in this case, the update of the address data of each channel is performed in the time slots T1 and T4 in the future channel processing for four channels,
The address integer part of each channel is output in the time slot T2 in the future channel processing for one channel, and the address decimal part is output in the time slot T3 of the corresponding channel.

In the case of this configuration, the compressed waveform can be reproduced by the decoding function of the external circuits 7a and 7b. Further, in reproducing the non-compressed waveform, the external circuits 7a and 7b
It is possible to perform a four-point interpolation by supplying a past sample from
Two-point interpolation is not selected). However, if the F number exceeds “2” in the supply of the past sample, the supply of the new sample cannot keep up with the current sample, so that the interpolation of the non-compressed waveform is set to two-point interpolation. Also, for decoding of the compressed waveform, the F number is limited to “3” or less for the same reason as the supply speed of a new sample. Since the operation after the latch circuit 45 is different in each case, each case will be described.

First, in the case of compressed waveform reproduction, the operations of the selector 43a and the shift-down unit 48a at this time are exactly the same as in the case of the one sound source configuration.
“a” selectively outputs the return amount output from the return amount generation unit 42a as a correction value, and the shift-down unit 48a performs one-bit downshift. The value of the address advance amount ΔI calculated by the half adder 33a is limited to “3” or less for the above-described reason. According to the value ΔI, the return amount generation unit 42a generates the return amount. INC generator 41a
Generates the same number of pulses. The adder 50a is supplied with the address of the same value as in the case of the one-sound-source configuration from the shift-down unit. 4
Provide "0", "1", "0", "1" over the slot. On the master side, the waveform memory is accessed in the first two slots, and the address of the 16-bit data including the compressed sample to be decoded next to the already decoded sample and the address next to the address, as described above, Are sequentially input to the gate circuit 5 in the first two slots.
1a and supplied to the waveform memory 6.

Next, in the case of the non-compressed waveform four-point interpolation, unlike the normal four-point interpolation, the selector 43a selects and outputs the return amount generated by the return amount generator 42a.
As in the case of reproducing the immediately preceding compressed waveform, the value of the address advance ΔI calculated by the half adder 33a is limited to “2” or less, and the return amount and I
An NC signal is generated. In the adder 47a, the return amount is added to the address latched by the latch circuit 45a, and the address of the next uncompressed waveform to be read out (the relative address from the start address), which is the calculation result of the adder 47a, is output. Since the signal COMP is "0", the address passes through the shift-down unit 48a without any processing and is input to the adder 50a. From the auxiliary counter 49a, "0", "1", "0",
“1” is sequentially output, and in the gate circuit 51a,
The previous two slots of the addition result in the adder 50a are output.

In the case of four-point interpolation in which the sample is supplied by the external circuit 7a, the buffer RA of the external circuit 7a is used.
The uncompressed waveform data of the past four points read out by the time division channel in the past is stored in M70a as it is. The waveform data of four points required for interpolation is obtained from the waveform data of. Here, the output of the adder 47 is the relative address of the next waveform data following the waveform data for four points stored in the buffer RAM 70a. The master side sound source uses the buffer RAM with the first two slots.
The next waveform data following the waveform data stored in 70a and the next waveform data are read from the waveform memory 6. At the same time, the INC generator 41a outputs an increment signal I according to the address advance amount ΔI.
NC1 to INC4 are sequentially generated. The signals INC1 to IN
C4 is a pulse signal indicating how many of the read waveform data are taken into the external circuit 7. As described above, since the address advance amount ΔI is equal to or less than “2”, the signals INC3 and INC4 always become “0”.

Finally, a case where two-point interpolation is performed on the uncompressed waveform is exactly the same as the case of the two sound source configuration described above. That is, the selector 43a selects and outputs the constant value “−2”, the shift-down unit 48a outputs the input address as it is, and the interpolation counter 49a outputs “0”, “1”,
"0" and "1" are output, and the gate opens only the first two slots on the master side. Therefore, a detailed description of the operation is omitted. However, the INC generating unit is different from the usual one, and the master side sets “1”, “1”, “1”,
“1” is replaced by “0”, “0”, “1”,
"1" is output in each of the four slots of the time-division channel. The increment signal adjusts the output timing of outputting the waveform data from the external circuits 7a and 7b to the interpolation units 19a and 19b at timings suitable for the master side and the slave side.

On the other hand, also in the sound source 8b on the slave side,
Address data for two points is generated by the same operation as that of the tone generator 8a on the master side, and is sequentially supplied to the waveform memory 6. However, in the sound source 8b on the slave side, the gate circuit 51b in the last stage is open only for the latter two time slots, so that the address data for the latter two points is output.

The waveform data is sequentially read from the waveform memory 6 in accordance with the address data (two points for the master and two points for the slave). The waveform data for the latter two points is supplied to the circuit 7a and the slave side sound source 8b
To the external circuit 7b.

In the external circuit 7a on the master side,
The output of the delay circuit 56a is selected by the selector 57a. On the other hand, on the slave side, the selector 57b selects the output side of the delay circuit 55b. This state is shown in the case of two chips (master / slave) in FIG. Assuming that data taken in four time slots of each time division channel of the waveform memory are I, II, III, and IV, respectively, data I and II for the first two slots on the master side, and data I and II for the second half on the slave side. The data III and IV corresponding to the slot are taken in. According to FIG. 11, the timing of data I and II output from the selector 57a and the timing of data III and
The IV timing is controlled so as to be exactly the same timing (the first two slots of the four slots of one time division channel). That is, this selector 5
The master / slave operates at the same timing up to the demodulation circuits 64a and 64b after 7a and 57b.

The data output from the selectors 57a and 57b are connected to the selectors 58a and 58
From 58b to the demodulation circuits 64a and 64b, the signal passes while being subjected to predetermined processing. The processing in this part of the compressed waveform is exactly the same as that already described in the case of the one-sound-source configuration with the external circuit 7, and the description is omitted.

Next, a case of a time division channel for reproducing an uncompressed waveform will be described. The uncompressed waveform data that has passed through the selectors 57a and 57b is
As with the uncompressed waveform described above for the sound source configuration,
The data is input to the demodulation circuits 64a and 64b without any processing. There may be a case of four-point interpolation and a case of two-point interpolation, but both are the same so far.

First, the process of supplying the past samples for the four-point interpolation of the uncompressed waveform in the demodulation circuits 64a and 64b will be described. In this case, the buffer RAMs 70a and 70b store the waveform data of four points that have been read out in the past in the time division channel and used for interpolation. The timing before the data read from the waveform memory 6 in the current time-division channel is input to the adders 91a and 91b (FIG.
At the timing of DO of one buffer RAM), the waveform data of the four points is read from the buffer RAMs 70a and 70b and sequentially latched 71a, 71b to 74a and 74.
b. Each of the latched data is shown in FIG.
The selector 75a at the timing of “upper” of the selector a
75b to 78a, 78b
a, 83b to 86a, 86b.

As shown in FIG. 11, from the timing, new read data is sequentially added to the adders 91a and 91a.
At this time, since the signal COMP is "0", the gates 90a and 90b are closed, and the input uncompressed waveform data is supplied to the delays 90a and 90b as they are. As described above, since pulses are supplied as the increment signal INC by the number of waveform data to be newly acquired, a shift corresponding to the signals INC1 to INC2 is performed at the timing of X1 and X2 of the selector a ( The signals INC3 to INC4 are always "0"), and the selector 93 is set at the timing of the signal INC4.
a, 93b to 96a and 96b are supplied to the delays 97a, 97b to 100a and 100b from the third input terminals, and thereafter, the delays 97a, 97b to 100a and 1
00b, the delay 100a, 1
The output of 00b is again supplied to and written into the buffer RAMs 70a and 70b, and is also supplied to the interpolation units 19a and 19b as the outputs of the demodulation units 64a and 64b, respectively.
This output data is eventually stored in the buffer RA.
The four points of waveform data that were previously used for the four-point interpolation in M70a and 70b and that were updated with the waveform data newly read from the waveform memory 6 in accordance with the signals INC1 to INC2 are used. That is, the waveform data for four points used for the current interpolation is obtained.
b and is written to the buffer RAMs 70a and 70b for the next processing.

Next, in the case where the compressed waveform is being reproduced, as described above, the timing of the input waveform on the slave side is the same as that in the case of the one sound source configuration on the master side by the operation of the selectors 57a and 57b. And the selectors 58a and 58b separate the data into 8-bit data in the same manner as in the case of the one sound source configuration, so that the demodulation circuits 64a and 64b
The form of the compressed waveform to be entered is exactly the same as in the case of the one-sound-source configuration with the external circuit 7 described above. Therefore, the compressed waveforms expanded by the non-linear expansion units 63a and 63b are demodulated and output by the demodulation circuits 64a and 64b in the same manner as in that case.

Finally, a case where two-point interpolation is performed on an uncompressed waveform will be described. As in the above case, the selector 57a,
At 57b, the data on the master side and the data on the slave side are controlled so as to have the same timing.
a, 58b, the gates 62a, 62b, and the non-linear extension units 63a, 63b. Interpolator 1 to which the outputs of demodulation circuits 64a and 64b are input
In 9a and 19b, the processing timing is the same between the case where there is an external device and the case where there is no external device in the two sound source configuration, so that the demodulation circuits 64a and 64b use It is necessary to output again at a different timing. In this case, the demodulation circuits 64a and 64b output “1”, “1”, “1”, “1” on the master side and “0” on the slave side as increment signals INC for four time slots per channel. “0”, “1”, and “1” are supplied. The function itself of each component of the demodulation circuits 64a and 64b is the same as described above, but this increment signal IN
By C, the process of correcting to the different timing is performed.
That is, two points of uncompressed waveform data in the first two slots of the four time slots of each time-division channel are output from the master-side demodulation circuit 64a at the first two slots of each time-division channel and the slave-side demodulation circuit 64b. At the exit, the two slots in the latter half are at different timings.

As described above, FIG. 4 shows a state in which an i-channel address is generated two channels ahead of time when the external circuit 7 is provided. On the other hand, FIG.
1 shows a memory address, which is an address advanced by two channel times, as a memory address.
Is read into the external circuit 7 at this timing. The fetched data is output from the external circuit 7 at the timing depicted as the output in FIG. That is, FIG.
2 shows a state in which a time delay of two channels occurs between the input of the read data of the waveform memory and the output of the waveform data to the interpolation unit 19. The waveform data corresponding to the two-channel advanced address shown in FIG.
The signal is output from the external circuit 7 after the number of channels, that is, at the same timing as the read timing when there is no external circuit in FIG.

The waveform data at each input timing of the four slots of each time-division channel of each of the interpolation units 19a and 19b is obtained when the external circuit is not mounted and when the external circuit is mounted in each case of the above-described interpolation. And does not change. Therefore, the interpolating units 19a and 19b execute the interpolation according to the specified interpolation method without regard to whether the external circuit is mounted or not, and perform one interpolation for each time-division channel. Output the waveform data.

On the other hand, in the envelope generating section 20a, envelopes for 32 channels are sequentially generated in accordance with the envelope control signal supplied from the envelope control register 17a, and the envelopes are supplied to the envelope generating and multiplying section 21a. The envelope multiplication unit 21a adds the envelope to the interpolated waveform data for each time-division channel, and the channel accumulation unit 22a mixes the waveform data for 32 channels, and the analog data is converted by the DAC 23a. After being converted to a signal, the sound system 10
Is pronounced as a musical tone.

Note that, in the configuration of Case D described above, 16
In the case of bit data (uncompressed), a pitch limitation of up to 100 KHz occurs, and in the case of 8-bit data (compression), a pitch limitation of up to 150 KHz occurs. In this configuration, two-point interpolation is also possible. In this case, the pitch limitation is eliminated with 16-bit data (uncompressed). Also,
If the sound source is two chips, only one of them
An external circuit may be attached.

[0125]

As described above, according to the first aspect of the present invention, a waveform memory for storing waveform data, an address is generated for each of a plurality of time division channels, and the address is read from the waveform memory by the address. A first tone generating means for generating musical tones for a plurality of time division channels based on n waveform data output for each of the time division channels. Possible, together with the first musical tone generating means,
A second musical tone generating means sharing the waveform memory, and when the second musical tone generating means is added, the number of waveform data to be read in each time division channel is reduced to m less than n. And a readout number changing means for changing the number of waveforms, so that the waveform memory can be shared by the user without adding a waveform memory, and the number of interpolation points can be reduced when a sound source is added. By reducing the number of accesses to the waveform memory, it is possible to obtain an advantage that the speed of reading the waveform data can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention.

FIG. 2A is a block diagram showing a configuration when one sound source is used for one waveform memory, and FIG.
FIG. 3C is a block diagram illustrating a configuration in which one sound source is shared by two sound sources, and FIG. 3C illustrates a configuration in which one sound source is used for one waveform memory and an external circuit is interposed. FIG. 3D is a block diagram showing a configuration in which one waveform memory is shared by two sound sources and an external circuit is interposed between each sound source.

FIG. 3 is a block diagram illustrating one configuration of an address generator 18 in the present embodiment.

FIG. 4 is a time chart for explaining the timing of address generation in the embodiment.

FIG. 5 is a block diagram showing a configuration example of an external circuit 7 in the embodiment.

FIG. 6 is a conceptual diagram for explaining addressing of a waveform memory in the embodiment.

FIGS. 7A to 7C are diagrams for explaining how to read waveform data compressed to 8 bits from a 16-bit waveform memory 6 in the embodiment.

FIG. 8 is a block diagram illustrating a configuration example of a demodulation circuit 64 according to the embodiment.

FIG. 9 is a block diagram illustrating a configuration example of an interpolation unit 19 according to the embodiment.

10A is a diagram for explaining an interpolation coefficient in four-point interpolation, and FIG. 10B is a diagram for explaining an interpolation coefficient in two-point interpolation.

FIG. 11 is a timing chart for explaining the operation of the musical sound generating device in the embodiment.

FIG. 12 is a timing chart for explaining the operation of the interpolation unit 19 in the embodiment.

[Explanation of symbols]

1 ... keyboard, 2 ... tone switch, 3 ... microcomputer (control unit), 4 ... external instruction unit, 5 ... 2-chip instruction unit (reading number changing means), 6 ... waveform memory, 7, 7
a, 7b ... external circuit, 8, 8a ... sound source (tone generating means, first tone generating means), 8b ... sound source (tone generating means, second tone generating means), 18 ... address generation Section, 19 ... interpolation section, 70 ... reproduced sample buffer R
AM.

Claims (1)

[Claims] 1. A waveform memory for storing waveform data, an address generated for each of a plurality of time division channels, and n waveform data for each time division channel read from the waveform memory by the address. And a first tone generating means for generating a tone for a plurality of time-division channels, wherein the tone generator can be added to the configuration of the tone generator.
A second musical tone generating means sharing the waveform memory with the musical tone generating means, and when the second musical tone generating means is added, the number of waveform data to be read in each time division channel is determined by the a tone generator for changing the number of readings to m less than n.