JPH11234059A - Amplifying circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplifying circuit with a large amplification factor which has a smaller power consumption in the absence of a signal. SOLUTION: Output transistors Q1 and Q2 are connected on a push-pull basis, and 1st and 2nd bias setting circuits 16 and 19 consisting of series circuits of 3rd and 4th diode-connected transistors Q3 and Q4 and 1st and 2nd resistors 17 and 20 are connected between the bases and emitters of the above output transistors. Furthermore 1st and 2nd shunt circuit 18 and 21 which shunt currents equal to the current flowing to the 1st and 2nd bias setting circuit 16 and 19 from the currents flowing to the 2nd or 1st bias setting circuit 19 or 16 are constituted by the use of current mirror circuits. When a small signal is inputted, the 1st bias setting circuit 16 and 1st shunt circuit 18, and 2nd bias setting circuit 19 and 2nd shunt circuit 21 operate complementarily to obtain an amplification factor, which is twice as large as that of the current amplification factor βof the output transistors Q1 and Q2. An idling current is determined by the emitter area ratios of the output transistors Q1 and Q2 and the transistors Q3 and Q4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a push-pull amplifier circuit, and more particularly to an amplifier circuit suitable for an IC for low power consumption.

[0002]

2. Description of the Related Art Conventionally, for example, a circuit as shown in FIG. 3 has been used for a push-pull amplifier for portable audio. In FIG. 3, the input terminal of the driving stage A1 is connected to the non-inverting input terminal T1 of the amplifier circuit 1, and the output terminal is connected to a diode-connected transistor Q3 which forms a current mirror circuit together with the output transistor Q1. On the other hand, the input terminal of the driving stage A2 is connected to the inverting input terminal T2 of the amplifier circuit 1, and the output terminal is connected to the diode-connected transistor Q4 which forms a current mirror circuit together with the output transistor Q2. These output transistors Q1 and Q2 are
3, has an emitter area N times as large as Q4 (N> 1), and is connected in series between the power supply terminal P and the ground terminal G of the amplifier circuit 1. In this case, the transistors Q1, Q2
Have a configuration in which the common connection point is connected to the output terminal T3 of the amplifier circuit 1, that is, a push-pull connection. A coupling capacitor 2 and a load resistor 3 are connected in series between the output terminal T3 and the ground terminal G.

In the above configuration, a signal input S1 is applied to a non-inverting input terminal T1, and a signal input S2 having a phase opposite to that of the non-inverting input terminal T1.
Is applied to the inverting input terminal T2, when the signal input S1 is positive (the signal input S2 is negative), a current proportional to the magnitude of the signal input S1 is supplied to the transistor Q3 by the driving stage A1. An output current determined by a mirror ratio with respect to the current flows to the load resistor 3 through the output transistor Q1. When the signal input S2 is positive (the signal input S1 is negative), a current proportional to the magnitude of the signal input S2 is supplied to the transistor Q4 by the driving stage A2, and the output current is determined by the mirror ratio. Flows from the load resistor 3 to the output transistor Q2.

[0004]

In order to obtain a high degree of amplification in the amplifier circuit 1 having the above-mentioned configuration, the emitters of the transistor Q3 and the output transistor Q1, and the emitters of the transistor Q4 and the output transistor Q2, which are connected in a current mirror, are required. The mirror ratio may be increased by increasing the area ratio. However, when the emitter area ratio is increased, the following problems appear.

That is, in the amplifier circuit 1 configured as a push-pull circuit, in order to reduce crossover distortion, even when there is no signal, the driving transistors A1 and A2 bias the output transistors Q1 and Q2 from the driving stages A1 and A2. A method of supplying a current and flowing a small idling current to these output transistors Q1 and Q2 is used. However, when the mirror ratio increases, the idling current also increases, which causes a problem that power consumption when there is no signal increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an amplifier circuit which consumes less power when there is no signal and has a large amplification degree in all operation regions. is there.

[0007]

In order to achieve the above object, an amplifier circuit according to the present invention comprises a first output transistor grounded to a collector and a second output transistor grounded to an emitter. A connected output stage, a series circuit of a diode-connected third transistor and a first resistor, and first bias setting means connected between a base and an emitter of the first output transistor; A second bias setting means connected between a base and an emitter of the second output transistor, wherein the second bias setting means is a series circuit of a diode-connected fourth transistor and a second resistor; The bias current flowing through the first bias setting means is controlled so that the bias current flowing through the first bias setting means is equal to the current flowing through the first bias setting means. A first shunting means connected to the first bias setting means so as to shunt the bias current, and the shunting current value is controlled so as to match a current value flowing to the second bias setting means. Second
(Claim 1).

According to this structure, a constant bias current and a positive-phase signal current are supplied to the first bias setting means and the first current dividing means, and the second bias setting means and the second current dividing means are supplied. When the bias current equal to the bias current and the signal current having the opposite phase are supplied to the first and second means, the idling current flowing through the first and second output transistors by the first and second bias setting means is set to an arbitrary value. And when the input signal is small, the current flowing through the second bias setting means, that is, the shunt current flowing to the first bias setting means, changes in response to the change in the current flowing through the first bias setting means. It changes in the opposite direction so as to correct the current change. Accordingly, the sum of the current flowing through the first bias setting means and the shunt current thereof is kept substantially equal to the bias current, and all the signal currents are supplied to the base of the first output transistor. A large amplification degree proportional to the current amplification factor is obtained.
The operations of the second bias setting means and the second output transistor are the same.

When the input signal further increases, one of the bias setting means and the output transistor is turned off in accordance with the polarity of the input signal, so that the other bias setting means and the output transistor become equivalent to a Widlar type current mirror circuit. , A larger amplification factor can be obtained.

A first output transistor whose emitter is grounded, a second output transistor whose emitter is complementary to the first output transistor, and which are complementary to the first output transistor. And a push-pull connection to an output terminal.
The same operation can be obtained by a configuration including the same first and second bias setting means and the first and second shunting means as in the amplifier circuit described above.

Furthermore, in the amplifier circuit according to claim 1 or 2, the first shunt means makes a shunt current value for the second bias setting means coincide with a current value flowing to the first bias setting means. A current mirror circuit for performing control, wherein the second shunt means controls the shunt current value for the first bias setting means to be equal to the current value flowing to the second bias setting means. The present invention can be configured to include a current mirror circuit for performing the operation.

With this configuration, the current can be accurately turned back by combining the required number of current mirror circuits in accordance with the configuration of the output stage, so that the shunt current value for the second and first bias setting means can be adjusted. Can be accurately matched with the current value flowing through the first or second bias setting means, respectively.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to FIG. 1 showing an electrical configuration of an amplifier circuit. In FIG. 1, the amplifier circuit 11 is configured as, for example, a monolithic IC, and includes a current amplification stage 12 and driving stages A1 and A2 each composed of, for example, a differential amplifier for driving the current amplification stage 12. I have.

The input terminal of the driving stage A1 is an amplifying circuit 11
And its output terminal is connected to the non-inverting input signal line 13 of the current amplification stage 12.
The input terminal of the driving stage A2 is connected to the inverting input terminal T2 of the amplifier circuit 11, and the output terminal is connected to the inverting input signal line 14 of the current amplifying stage 12. These drive stages A
1, A2 amplifies the input signals S1 and S2, which are input to the non-inverting input terminal T1 or the inverting input terminal T2 of the amplifying circuit 11 and have opposite phases, respectively, and converts the amplified signals into currents. The current is supplied to the current amplification stage 12 together with the bias current.

The current amplification stage 12 has the following configuration. That is, the collector and the emitter of the npn-type first output transistor Q1 are respectively connected to the power supply terminal P to which a positive power supply voltage is applied and the output terminal T3,
The collector and the emitter of the pn-type second output transistor Q2 are connected to the output terminal T3 and the ground terminal G, respectively. As a result, the output transistors Q1 and Q2 form a push-pull circuit, and constitute the output stage 15 of the amplifier circuit 11. The output transistors Q1 and Q2 are connected to the emitter area N of the transistors Q3 and Q4, respectively, which will be described later.
It has an emitter area of 1 time and N2 times (N1> 1, N2> 1). The base of the output transistor Q1 is connected to the non-inverted input signal line 13, and the base of the output transistor Q2 is connected to the inverted input signal line 14.

An npn-type third transistor Q3 diode-connected to a first resistor 17 constituting a first bias setting circuit 16 as first bias setting means is provided between the base and the emitter of the output transistor Q1. Are connected in series, and the base and the emitter of the third transistor Q3 are connected to the base and the emitter of the transistor Q5, respectively. Thus, transistors Q3 and Q5 form a current mirror circuit.

The power terminal P is connected to the emitters of a pair of pnp transistors Q6 and Q7 forming a current mirror circuit, and the ground terminal G is connected to a pair of npn transistors Q8 forming another current mirror circuit. , Q
9 are connected to each other. The collector of the diode-connected transistor Q6 is connected to the collector of the transistor Q5, and the collector of the transistor Q7 is connected to the collector of the diode-connected transistor Q8. The collector of the transistor Q9 is connected to the inverted input signal line 14. These transistors Q5 to Q9 constitute a first shunt circuit 18 as first shunt means. In this case, the emitter areas of the transistors Q5 to Q9 are all formed to be equal, so that in the first shunt circuit 18,
A current equal to the current flowing through the first bias setting circuit 16 can be divided from the inverted input signal line 14 through the transistor Q9.

On the other hand, in the current amplification stage 12, a second bias setting circuit 19 and a second current dividing circuit 21 similar to the first bias setting circuit 16 and the first current dividing circuit 18 described above are provided.
Is provided. That is, between the base and the emitter of the output transistor Q2, an npn-type fourth transistor Q4 diode-connected to a second resistor 20 forming a second bias setting circuit 19 as a second bias setting means is provided. Are connected in series, and the base and the emitter of the fourth transistor Q4 are connected to the base and the emitter of the transistor Q10, respectively. This allows
The transistors Q4 and Q10 form a current mirror circuit.

The power terminal P is connected to the emitters of a pair of pnp transistors Q11 and Q12 forming a current mirror circuit, and the output terminal T3 is connected to a pair of npn transistors Q1 forming another current mirror circuit.
3, the emitters of Q14 are connected. The collector of the diode-connected transistor Q11 is
The collector of the transistor Q10 is connected to the collector of the transistor Q12, and the collector of the transistor Q12 is connected to the collector of the diode-connected transistor Q13. Further, the collector of the transistor Q14 is connected to the non-inverting input signal line 13. These transistors Q10 to Q14 constitute a second shunt circuit 21 as second shunt means. In this case, the emitter areas of the transistors Q10 to Q14 are all formed to be equal, so that in the second shunt circuit 21, a current equal to the current flowing to the second bias setting circuit 19 is set to The current can be shunted from the inverted input signal line 13 through the transistor Q14.

A coupling capacitor 22 and a load resistor 2 are connected between the output terminal T3 and the ground terminal G.
And the capacitor 22 and the load resistor 23 are connected to the output transistors Q1 and Q2 in the positive direction (the direction from the output terminal T3 to the ground terminal G) or in the negative direction (the ground terminal G to the output terminal T3). Current) is supplied.

Next, the operation of the present embodiment will be described in the order of no signal, small signal input, and large signal input. First, the setting of the bias current of the current amplification stage 12 and the setting of the idling current of the output transistors Q1 and Q2 when there is no signal will be described. That is, the driving stages A1 and A2 supply the same level bias currents IA1 and IA2 to the current amplification stage 12 through the non-inverting input signal line 13 and the inverting input signal line 14, respectively. The relationship between the currents flowing through the transistors at this time is as follows: when the resistances of the resistors 17 and 20 are R1 and R2, respectively, the equations (1) to (6)
It looks like an expression. In these equations, the collector currents flowing through the transistors Q1 to Q14 are represented by ICQ1 to ICQ1, respectively.
Expressed as ICQ14.

ICQ1 = N1 × ICQ3 × exp (ICQ3 × R1 / VT) (1) ICQ2 = N2 × ICQ4 × exp (ICQ4 × R2 / VT) (2) ICQ3 = ICQ5 = ICQ6 = IC9 ... (3) ICQ4 = ICQ10 = ICQ11 = ICQ12 = ICQ13 = ICQ14 ... (4) IA1 = ICQ3 + ICQ14 ... (5) IA2 = ICQ4 + ICQ9 ... (6) where N1 is the area of the transistor Q1 to the area of the transistor Q3 to the area of the transistor Q3. Emitter area ratio of transistor Q2 to transistor Q4 VT (thermal voltage): = kT / q (k: Boltzmann constant T: absolute temperature q: electron charge)

Here, the bias currents IA1 and IA2 are set to IA1 =
After setting IA2 = IA, N1 = N2 = N, R1 = R2 =
When the condition of R is added and the bias current of the transistors Q3 and Q14 flowing through the output transistor Q2 is ignored and the idling current IIDOL of the same value flows through the output transistors Q1 and Q2, ICQ3 = ICQ
4 = IA / 2. The result is expressed by the equation (1) and the equation (2).
When substituted into the equation, the idling current IIDOL flowing through the output transistors Q1 and Q2 is as shown in the following equation (7). IIDOL = N × (IA / 2) × exp {(IA / 2) × R / VT} (7)

In other words, the idling current IIDOL flowing through the output transistors Q1 and Q2 when there is no signal is different from the bias current IA supplied from the driving stages A1 and A2 by the output transistors Q1 and Q2 and the transistors Q3 and Q3.
An arbitrary value can be determined by the emitter area ratio to Q4 and the resistance values R1 and R2.

Next, the operation when a minute signal is input in the above-mentioned bias state when there is no signal will be described. A small input signal S1 and an input signal S2 having a phase opposite thereto
Are input from the non-inverting input terminal T1 or the inverting input terminal T2, respectively, the driving stages A1 and A2
1. Amplify S2 and convert it to signal current. Then, a current obtained by adding the signal current is to the bias current IA is output from the driving stage A1 to the non-inverting input signal line 13, and the bias current IA is applied to the inverting input signal line 14 from the driving stage A2.
And the current obtained by adding the signal current −is to the current.

At this time, as shown in the equations (3) and (4), there is a relation of ICQ3 = ICQ9 and ICQ4 = ICQ14.
For example, when the signal current is is positive and the current of the transistor Q3 increases, the current of the transistor Q9 also increases by the same value. On the other hand, the current flowing through the transistors Q4 and Q9 is equal to the current (IA-is) output from the driving stage A2 to the inverting input signal line 14, so that when the current of the transistor Q9 increases, the transistor Q4, and furthermore, the current of the transistor Q14 decreases.

That is, since the transistors Q3 and Q9 and the transistors Q4 and Q14 operate complementarily to compensate for the increase and decrease of the current, all the signal currents | is | are output transistors Q1 (when is is positive), or It flows into the base of the transistor Q2 (when is is negative). Actually, since the signal current is is input to the non-inverting input signal line 13 and the signal current -is, which is a reverse-phase component thereof, is input to the inverting input signal line 14, the output transistor Q
1. The current flowing into the base of Q2 is twice the signal current | is |. Therefore, the output current i flowing through the load resistor 23
out is as shown in equation (8).

Iout = 2 × β × is (8) where β is the current amplification factor of the output transistors Q1 and Q2. Thus, the amplification of the current amplification stage 12 when the input signal is small is determined by the emitter area ratio Irrespective of this, the current amplification factor β of the output transistors Q1 and Q2 is twice as large.

Next, a case where the input signal is further increased will be described. The input signals S1, S2 input from the non-inverting input terminal T1 or the inverting input terminal T2 further increase, and the signal current | i output from the driving stages A1, A2
When s | increases, ICQ3 = IA, ICQ4 = ICQ2 = 0
(When is is positive), or ICQ4 = IA, ICQ3 = ICQ
With the bias point where 1 = 0 (when is is negative) as a boundary, transistors Q3 and Q9 and transistors Q4 and Q1
4 saturates. In this saturated state, the output transistor Q1 and the transistor Q3 or the output transistor Q2 and the transistor Q4 constitute a circuit equivalent to a Widlar type current mirror circuit, and the voltage at the resistor 17 or the resistor 20 generated by the signal current | is | The drop increases the base-emitter voltage of the output transistor Q1 or the output transistor Q2, and increases the collector current of the output transistor Q1 or the output transistor Q2. At this time, the output current iout flowing through the load resistor 23 is as shown in equation (9).

Iout = N × is × exp (is × R / VT) (9) Accordingly, as the input signal increases, the amplification of the current amplification stage 12 increases exponentially according to the equation (9).

As described above, according to the present embodiment, the first and second output transistors Q 1,
A first or second bias setting circuit 16 comprising a series circuit of diode-connected third or fourth transistors Q3, Q4 and first or second resistors 17, 20 between the base and emitter of Q2; 19, and a current equal to the current flowing through the first and second bias setting circuits 16 and 19 is supplied to the second and first bias setting circuits 19 and 1 respectively.
6 is characterized by having first and second shunt circuits 18 and 21 that can shunt current from the current flowing through the circuit 6. As a result, the idling current IIDOL flowing through the output transistors Q1 and Q2 when there is no signal is changed to the bias current IA,
Output transistors Q1, Q2 and transistors Q3, Q4
And the resistance values of the resistors 17 and 20. By setting these to appropriate values, the idling current IIDOL at the time of no signal can be minimized to prevent crossover distortion. Power consumption. In addition, the first bias setting circuit 16 and the first shunt circuit 1
8, and the second bias setting circuit 19 and the second shunt circuit 21 operate complementarily, so that the amplification degree is twice the current amplification factor β of the output transistors Q1 and Q2 regardless of the emitter area ratio. It will be large. Further, the amplification degree when the input signal becomes large increases exponentially with respect to the input signal due to overdrive.
Therefore, the emitter area ratio (output transistor Q1,
A large amplification degree can be obtained without increasing the chip area of Q2).

As described above, in the amplifier circuit 11 of the present embodiment, a large amplification factor (2β times) can be obtained even when the input signal is very small. Therefore, other amplification circuits,
For example, to reduce current consumption when there is no signal, the amplification of the small signal input area is reduced, and the crossover distortion is improved compared to the case where the amplification in the medium current area to the large current area is set higher by overdrive etc. Is done. Also,
In general, when the amplification of the small signal input region is extremely low and the amplification in the small current region to the medium current region is high,
In some cases, the current of the output transistor changes sharply near the zero cross of the output voltage and oscillation occurs. However, in the amplifier circuit 11 of the present embodiment, a large degree of amplification is obtained even near the zero cross, so that oscillation hardly occurs.
Furthermore, even when the drive stages A1 and A2 are misaligned and the bias currents IA1 and IA2 output therefrom are different from each other, compared with other amplifier circuits having small amplification at the time of inputting a small signal. The influence of the error on the input / output characteristics (such as expansion of the nonlinear region) is relatively small.

Second Embodiment Next, a second embodiment of the present invention will be described.
An embodiment will be described with reference to FIG. Here, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. Only components having different configurations will be described.

FIG. 2 shows the electrical configuration of the amplifier circuit 11, and the current amplification stage 24 is configured as follows. That is, the pnp-type first output transistor Q2
1 is connected to the output terminal T3 and the power supply terminal P, respectively, and the collector and emitter of the npn-type second output transistor Q22 are connected to the output terminal T3 and the ground terminal G, respectively. As a result, the output transistors Q21 and Q22 form a push-pull circuit,
The output stage 25 of the amplifier circuit 11 is configured. The output transistors Q21 and Q22 have N1 times and N2 times (N2 times the emitter area of transistors Q23 and Q24, respectively, which will be described later).
1> 1, N2> 1).

A ground terminal is connected to a pair of npn transistors Q31 and Q32 forming a current mirror circuit.
And the collector of the diode-connected transistor Q31 is connected to the non-inverting input signal line 13.
, And the collector of the transistor Q32 is connected to the non-inverting input signal line 26. Thereby, the driving stage A
1 from the non-inverting input signal line 26 to the transistor Q3
2 to the ground terminal. The base of the output transistor Q21 is connected to the non-inverted input signal line 26, and the base of the output transistor Q22 is connected to the inverted input signal line 1.
4, respectively.

Between the base and the emitter of the output transistor Q21, a pnp-type third transistor Q23 diode-connected to a first resistor 28 constituting a first bias setting circuit 27 as first bias setting means. Are connected in series, and the third transistor Q23
Are connected to the base and the emitter of the transistor Q25, respectively. Thereby, transistors Q23 and Q25 form a current mirror circuit.

The ground terminal G is connected to respective emitters of a pair of npn transistors Q26 and Q27 forming a current mirror circuit. The collector of the diode-connected transistor Q26 is connected to the collector of the transistor Q25, and the collector of the transistor Q27 is connected to the inverted input signal line 14. These transistors Q25 to Q27 constitute a first shunt circuit 29 as first shunt means. In this case, the emitter areas of the transistors Q25 to Q27 are all equal, so that the first shunt circuit 29 inverts the current equal to the current flowing to the first bias setting circuit 27. From the input signal line 14 to the transistor Q2
7 can be diverted.

On the other hand, a second bias setting circuit 30 and a second current dividing circuit 32 similar to the first bias setting circuit 27 and the first current dividing circuit 29 described above are provided in the current amplifying stage 24.
Is provided. That is, the output transistor Q22
Is connected in series with a second resistor 31 constituting a second bias setting circuit 30 as a second bias setting means and an npn-type fourth transistor Q24 diode-connected. The base and emitter of the fourth transistor Q24 are
28 are respectively connected to the base and the emitter. Thus, transistors Q24 and Q28 form a current mirror circuit.

The power terminal P is connected to respective emitters of a pair of pnp transistors Q29 and Q30 forming a current mirror circuit. The collector of the diode-connected transistor Q29 is connected to the transistor Q29.
The collector of the transistor Q30 is connected to the non-inverting input signal line 26. These transistors Q28 to Q30 constitute a second shunt circuit 32 as second shunt means. In this case, the emitter areas of the transistors Q28 to Q30 are all formed to be equal, so that in the second shunt circuit 32, a current equal to the current flowing to the second bias setting circuit 30 is applied to the transistors Q28 to Q30. The current can be diverted to the non-inverting input signal line 26 through Q30.

According to the present embodiment having the above configuration, the setting of the bias current IA and the idling current IIDOL and the amplification degree of the current amplification stage 24 in the amplifier circuit 11 are as follows.
It has the same function and effect as the first embodiment. In addition, in the present embodiment, the first and second shunt circuits 2
Since each of the transistors 9 and 32 can be constituted by three transistors, the cost can be reduced and the chip area can be reduced. The current mirror circuit including the transistors Q31 and Q32 can be made unnecessary if the output circuit in the driving stage A1 is configured as a current sink type.

(Other Embodiments) The present invention is not limited to the embodiment described above and shown in the drawings.
For example, a field effect transistor may be used instead of the bipolar transistor.

[0042]

According to the amplifier circuit of the present invention, a diode-connected third or fourth transistor is provided between the base and emitter of each of the first and second output transistors connected in a push-pull manner, which constitute the output stage. And a first or second bias setting means comprising a series circuit of a first resistor and a second resistor, and a current equal to the current flowing through the first and second bias setting means is connected to the second or the second resistor, respectively. The first and second shunting means that can shunt from the current flowing through the first bias setting means are provided, so that the idling current flowing through the output transistor when there is no signal is determined by the bias current and the first or second current. Can be determined arbitrarily by the emitter area ratio of the output transistor to the third or fourth transistor and the resistance values of the first and second resistors. Further, for a minute input signal, the first bias setting means and the first shunting means and the second bias setting means and the second shunting means operate complementarily. The size is proportional to the current amplification factor of the output transistor regardless of the area ratio. When the input signal further increases, overdrive occurs and the amplification degree increases exponentially with respect to the input signal. Therefore, large power can be supplied to the load in the entire operation region without increasing the idling current (power consumption at the time of no signal) of the output transistor. In addition, since it has a large amplification degree even for a minute input signal, crossover distortion is improved, oscillation is less likely to occur in the amplifier circuit, and even if an error occurs in the bias current, the effect on the input / output characteristics will not be affected. Can be smaller.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram of an amplifier circuit showing a first embodiment of the present invention.

FIG. 2 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

FIG. 3 is a diagram corresponding to FIG. 1 showing a conventional example.

[Explanation of symbols]

1 and 11 are amplifier circuits, 15 and 25 are output stages, and 16 and 27.
Is a first bias setting circuit (first bias setting means), 19 and 30 are second bias setting circuits (second bias setting means), and 18 and 29 are first shunt circuits (first bias setting means).
, And 32 are second shunt circuits (second shunt means), 17 and 28 are first resistors, and 20 and 31 are second resistors.
, Q1, Q21 are first output transistors, Q1
2, Q22 is a second output transistor, Q3 and Q23 are third transistors, and Q4 and Q24 are fourth transistors.

Claims (3)

[Claims] An output stage in which a first output transistor whose collector is grounded and a second output transistor whose emitter is grounded are connected to an output terminal by push-pull; a third transistor which is diode-connected; A first bias setting means connected between the base and the emitter of the first output transistor; and a series circuit of a diode-connected fourth transistor and a second resistor. A second bias setting means connected between the base and the emitter of the second output transistor; and a bias current connected to the second bias setting means so as to shunt the bias current. A first shunting means controlled to match a current value flowing to the first bias setting means, and a current flowing to the first bias setting means. An amplifier circuit that is connected so as to be able to shunt the bias current and is controlled so that the shunt current value matches the current value flowing through the second bias setting means. . 2. An output stage in which a grounded first output transistor and a grounded second output transistor which is complementary to the first output transistor are push-pull connected to an output terminal. A first bias setting means connected between a base and an emitter of the first output transistor, wherein the first bias setting means is connected between a diode-connected third transistor and a first resistor; And a second resistor connected between the base and the emitter of the second output transistor, and a bias current flowing through the second bias setting means. And the current is controlled so that the divided current value matches the current value flowing to the first bias setting means. A first shunt means connected to the first bias setting means so as to shunt the bias current, and the shunt current value is controlled so as to match a current value flowing to the second bias setting means. And a second shunt means. 3. The first shunting means includes a current mirror circuit for performing control to make a shunt current value for the second bias setting means coincide with a current value flowing to the first bias setting means. The second shunting means is configured to include a current mirror circuit for performing control for matching a shunt current value to the first bias setting means with a current value flowing to the second bias setting means. 2. The method according to claim 1, wherein
Or the amplifier circuit according to 2.