JPH11233515A - 半導体装置の多層配線平坦化方法 - Google Patents

半導体装置の多層配線平坦化方法

Info

Publication number
JPH11233515A
JPH11233515A JP10232206A JP23220698A JPH11233515A JP H11233515 A JPH11233515 A JP H11233515A JP 10232206 A JP10232206 A JP 10232206A JP 23220698 A JP23220698 A JP 23220698A JP H11233515 A JPH11233515 A JP H11233515A
Authority
JP
Japan
Prior art keywords
layer
dielectric material
metallization level
metallization
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10232206A
Other languages
English (en)
Japanese (ja)
Inventor
Felice Russo
ルッソ フェリス
Alfredo Franchina
フランチナ アルフレド
Giuseppe Miccoli
ミッコリ ジウゼッペ
Natale Nardi
ナルディ ナタール
Marco Ricotti
リコッティ マルコ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Consorzio Eagle
Texas Instruments Inc
Original Assignee
Consorzio Eagle
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Consorzio Eagle, Texas Instruments Inc filed Critical Consorzio Eagle
Publication of JPH11233515A publication Critical patent/JPH11233515A/ja
Pending legal-status Critical Current

Links

Classifications

    • H10D64/011—
    • H10W20/48—
    • H10W20/01—
    • H10W20/092—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP10232206A 1997-07-14 1998-07-14 半導体装置の多層配線平坦化方法 Pending JPH11233515A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT97A000431 1997-07-14
IT97RM000431A IT1293536B1 (it) 1997-07-14 1997-07-14 Procedimento di metallizzazione multilivello ad alta planarizzazione per dispositivi a semiconduttore

Publications (1)

Publication Number Publication Date
JPH11233515A true JPH11233515A (ja) 1999-08-27

Family

ID=11405176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10232206A Pending JPH11233515A (ja) 1997-07-14 1998-07-14 半導体装置の多層配線平坦化方法

Country Status (4)

Country Link
EP (1) EP0897193A3 (enExample)
JP (1) JPH11233515A (enExample)
KR (1) KR19990013850A (enExample)
IT (1) IT1293536B1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN120261401B (zh) * 2025-05-30 2025-09-26 合肥晶合集成电路股份有限公司 半导体结构及其制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5063175A (en) * 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
US5612254A (en) * 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
US5366911A (en) * 1994-05-11 1994-11-22 United Microelectronics Corporation VLSI process with global planarization
JP2836529B2 (ja) * 1995-04-27 1998-12-14 日本電気株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0897193A2 (en) 1999-02-17
KR19990013850A (ko) 1999-02-25
IT1293536B1 (it) 1999-03-01
EP0897193A3 (en) 1999-08-04
ITRM970431A1 (it) 1999-01-14
ITRM970431A0 (enExample) 1997-07-14

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