ITRM970431A0 - - Google Patents
Info
- Publication number
- ITRM970431A0 ITRM970431A0 ITRM970431A ITRM970431A ITRM970431A0 IT RM970431 A0 ITRM970431 A0 IT RM970431A0 IT RM970431 A ITRM970431 A IT RM970431A IT RM970431 A ITRM970431 A IT RM970431A IT RM970431 A0 ITRM970431 A0 IT RM970431A0
- Authority
- IT
- Italy
Links
Classifications
-
- H10D64/011—
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- H10W20/48—
-
- H10W20/01—
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- H10W20/092—
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT97RM000431A IT1293536B1 (it) | 1997-07-14 | 1997-07-14 | Procedimento di metallizzazione multilivello ad alta planarizzazione per dispositivi a semiconduttore |
| KR1019980028388A KR19990013850A (ko) | 1997-07-14 | 1998-07-14 | 반도체 장치에 대한 고 평탄화 멀티 레벨 금속화 방법 |
| EP98305603A EP0897193A3 (en) | 1997-07-14 | 1998-07-14 | Process of making a multilevel metallization scheme with high planarization degree |
| JP10232206A JPH11233515A (ja) | 1997-07-14 | 1998-07-14 | 半導体装置の多層配線平坦化方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT97RM000431A IT1293536B1 (it) | 1997-07-14 | 1997-07-14 | Procedimento di metallizzazione multilivello ad alta planarizzazione per dispositivi a semiconduttore |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ITRM970431A0 true ITRM970431A0 (enExample) | 1997-07-14 |
| ITRM970431A1 ITRM970431A1 (it) | 1999-01-14 |
| IT1293536B1 IT1293536B1 (it) | 1999-03-01 |
Family
ID=11405176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT97RM000431A IT1293536B1 (it) | 1997-07-14 | 1997-07-14 | Procedimento di metallizzazione multilivello ad alta planarizzazione per dispositivi a semiconduttore |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0897193A3 (enExample) |
| JP (1) | JPH11233515A (enExample) |
| KR (1) | KR19990013850A (enExample) |
| IT (1) | IT1293536B1 (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN120261401B (zh) * | 2025-05-30 | 2025-09-26 | 合肥晶合集成电路股份有限公司 | 半导体结构及其制造方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5063175A (en) * | 1986-09-30 | 1991-11-05 | North American Philips Corp., Signetics Division | Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material |
| US5612254A (en) * | 1992-06-29 | 1997-03-18 | Intel Corporation | Methods of forming an interconnect on a semiconductor substrate |
| US5366911A (en) * | 1994-05-11 | 1994-11-22 | United Microelectronics Corporation | VLSI process with global planarization |
| JP2836529B2 (ja) * | 1995-04-27 | 1998-12-14 | 日本電気株式会社 | 半導体装置の製造方法 |
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1997
- 1997-07-14 IT IT97RM000431A patent/IT1293536B1/it active IP Right Grant
-
1998
- 1998-07-14 KR KR1019980028388A patent/KR19990013850A/ko not_active Withdrawn
- 1998-07-14 JP JP10232206A patent/JPH11233515A/ja active Pending
- 1998-07-14 EP EP98305603A patent/EP0897193A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP0897193A2 (en) | 1999-02-17 |
| KR19990013850A (ko) | 1999-02-25 |
| JPH11233515A (ja) | 1999-08-27 |
| IT1293536B1 (it) | 1999-03-01 |
| EP0897193A3 (en) | 1999-08-04 |
| ITRM970431A1 (it) | 1999-01-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted |