JPH11233390A - Manufacture of semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a wafer treatment in operating efficiency by a method, wherein position data on defective chips which occur in a semiconductor manufacturing process are stored as electronic data, and then a wafer is subjected to a wafer treatment. SOLUTION: Defective marks 5 each given to defective elements which occur in a semiconductor manufacturing process are read in, and position data on the defective elements are stored as electronic data. Then, the element defective marks 5 put on a polyimide insulating film 4 of an IC chip are etched and separated off from the wafer 1. The wafer 1 is subjected to a wafer treatment such as wire rearrangement and formation. Thereafter, position data on defective chips stored as electronic data are read out, and first defective marks are given. The projection electrodes of chips with no first defective mark 9 are checked, and chips with defective electrodes occurring in a wafer treatment are detected. Second defective marks 10 are put on chips with respect to defective electrodes. In this way, by not carrying out checking operation of defective chips, operation can be improved in efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor, and more particularly, to a method of manufacturing a wafer having a defective mark.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and high density of semiconductor packages, flip chip bonding has been developed in which bare chips are directly mounted face down on a substrate. With the advent of camera-integrated VTRs and mobile phones, portable devices equipped with a small package having substantially the same dimensions as a bare chip, that is, a so-called CSP (chip size / scale package) are appearing one after another. Recently, CSP development has progressed rapidly, and the market demand has been in full swing.

[0003] CS using flip chip bonding
P is characterized by its small size and thickness. Compared to the conventional CSP using wire bonding, in the case of wire bonding, the wafer completed in the semiconductor manufacturing process can be directly put into the package process starting from the dicing process. In the case of chip bonding, the wafer completed in the semiconductor process goes through the process of attaching semiconductor bumps for external connection on the wafer and then is put into the packaging process. Become.

First, a semiconductor manufacturing process is shown in FIG.
The active element forming step shown in FIG.
An active element (not shown) is formed.

In the aluminum pad forming step shown in FIG. 5B, an aluminum pad 2 is formed on a wafer 1 and a passivation film 3 is formed on an active element surface.

In the step of forming a polyimide film shown in FIG. 5C, a polyimide insulating film 4 is formed on the passivation film 3 as necessary to relieve stress on the chip surface.

In the electric check step shown in FIG. 5D, each IC chip on the completed wafer is electrically checked by a tester using the aluminum pad 2.

[0008] The defect marking step shown in FIG.
An element failure mark 5 is provided on a defective IC chip found in the electric check process. As a method of providing an element failure mark, an electronic data method of recording the position data of the element failure mark on a recording medium such as a floppy disk, an organic ink method of applying an organic ink on a defective IC, and a method of scratching the defective IC with a laser. There is a laser mark method and the like.

Next, with reference to FIG. 4, a description will be given of a conventional manufacturing method for providing a semiconductor bump electrode for external connection on a wafer. In the semiconductor manufacturing process shown in FIG.
In the process shown in FIG. 1A, an active element is formed on a wafer 1, an aluminum pad 2 as an external terminal is formed, and the active element is protected by a passivation film 3. afterwards,
After performing an electrical inspection of each IC chip in the wafer using the aluminum pad 2, an element failure mark 5 is formed on the defective chip.
To form

In the step of forming a polyimide film shown in FIG. 4B, a bump polyimide film 6 is formed on a portion excluding the aluminum pad 2 to protect the active element surface when the bump electrode is formed. The bump polyimide film 6 has a convex shape because the element failure mark 5 has a convex shape.

The UBM (UnderBu) shown in FIG.
mpMetal) deposition step is to form a UBM7 as a common electrode metal to be used later to form a bump electrode on the active element surface side of the wafer completed in the semiconductor manufacturing process.
, Specifically, aluminum, chromium, and copper are formed by a sputtering method or a vapor deposition method.

In the plating resist forming step shown in FIG. 4D, a resist is applied on the UBM, and is exposed and developed so as to open the protruding electrode portion.
To form

In the plating step shown in FIG. 4 (e), a solder which becomes a protruding electrode is deposited by an electroplating method, and a plating bump 1 is formed.
7 is formed.

In the plating resist peeling step shown in FIG. 4 (f), the plating resist 16 that is no longer needed is peeled off with a peeling liquid.

In the UBM etching step shown in FIG. 4G, the UBM 7 used for electroplating is etched except under the protruding electrodes.

In the rounding step shown in FIG. 4H, a round solder bump 8 is formed by applying flux and reflowing the plating bump 17 deposited in a mushroom shape by plating.

The test bad mark applying step shown in FIG. 4 (i) is to inspect the completed bump electrode, and to mark an electrode failure mark 18 on the IC chip which has become defective when the bump electrode is formed. .

[0018]

However, the conventional semiconductor manufacturing method has the following problems. That is,
When the element failure mark is formed by the organic ink method, since the curing temperature of the organic resin is low, the organic ink is degraded by the heat generated during the formation of the UBM. There was a problem that cracks occurred and good electrical continuity could not be obtained. Further, in the photolithography process of polyimide and plating resist, there is a problem that the photolithography mask is damaged or damaged due to the swelling of the element defect mark. When the element failure mark is a laser mark method, there is a problem that a wafer is broken in a projection electrode forming step due to a micro crack caused by the laser mark. Also, when the element failure mark attached in the semiconductor manufacturing process is an electronic data method, since there is no defective chip information on the wafer,
In the electrode defect mark providing step, there is a problem that the same inspection as a non-defective chip must be performed on a defective element chip.

The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide an inexpensive manufacturing method which is excellent in reliability and productivity of a wafer used for a CSP or the like.

[0020]

In order to achieve the above object, a semiconductor manufacturing method according to the present invention is directed to a semiconductor manufacturing method for processing a wafer in which a plurality of IC chips having a plurality of bonding pads are arranged. A defect data recording step of recording position data of a defective chip generated in a semiconductor manufacturing process into electronic data, a wafer processing step of performing the wafer processing, and a first step of forming a defective mark on a defective chip on a wafer based on the electronic data.
It is characterized by comprising a defective mark providing step and a second defective mark providing step of providing a defective mark on a defective chip generated in the wafer processing step.

Further, the wafer processing step includes a rearrangement wiring step of moving the bonding pad to a new bonding pad position having a different position.

Further, the wafer processing step includes a projection electrode forming step of forming a projection electrode on the wafer.

Further, the defective data recording step is a step of reading a defective mark previously attached to a defective chip generated in a semiconductor manufacturing step.

Further, the defect mark is an organic ink.

Further, the defect data recording step includes a defect mark peeling step of peeling the defective mark after the step of reading the defect mark.

Further, the defective mark removing step is characterized in that a polyimide film as a base covering the wafer is removed.

Further, the defect mark used in the first defect marking step is an organic ink.

Further, the defect mark used in the second defect marking step is an organic ink.

The organic ink used in the first defect marking step and the second defect marking step are the same.

[0030]

FIG. 1 shows a method of manufacturing a semiconductor according to the present invention. The semiconductor manufacturing process of FIG. 1A is equivalent to the above-described conventional technology shown in FIG.

In the defective chip data processing step shown in FIG. 1B, the element defective mark 5 on the IC chip of the wafer, which is attached in the defect mark providing step in the above-described semiconductor manufacturing process, is read, and the position data is read. Is recorded as electronic data.

The defective mark peeling step shown in FIG.
In this step, the element failure mark 5 provided on the polyimide insulating film 4 of the IC chip is etched using a polyimide etchant, for example, a hydrazine solution, and the element failure mark 5 is peeled off from the wafer. Other methods of peeling off defective marks include a method of peeling only defective marks using a peeling liquid, and a method of peeling defective marks by ashing.

The wafer processing step shown in FIG.
This is a step of performing wafer processing such as formation of rearranged wiring and formation of bump electrodes on the wafer having no element defect mark.

Next, in a first defect mark assigning step shown in FIG. 1E, the position data of the element defective chip recorded in the above-mentioned electronic data is read out on the wafer on which the above-mentioned wafer processing has been completed, and the first defect mark is formed. This is a step of attaching the mark 9. As the defective mark material, an organic material such as an ink material HX-6880 manufactured by Hugle Electronics Co., Ltd. is used.

In the second defect mark applying step shown in FIG. 1F, the protruding electrodes of the chips excluding the element defective chips attached in the first defect mark applying step are inspected, and the chip is subjected to the wafer processing step. A second defective mark 10 is provided on the generated electrode defective chip. Since this inspection is a visual inspection, work efficiency is greatly improved by not inspecting a defective element chip in a wafer. Also, by using the same material as the above-mentioned first defective mark material for the second defective mark material, the same criterion can be used when performing the defective chip determination in the subsequent assembly process by pattern recognition. The process becomes stable.

FIG. 2 shows a rearrangement wiring forming step which is one of the above-mentioned wafer processing steps. The rearrangement wiring forming step is a step of moving a bonding original pad to a new pad position having a wide pad pitch by performing rearrangement wiring on the wafer. In the polyimide film forming step shown in FIG. 2A, a polyimide is applied on a wafer, and an interlayer polyimide film 12 is formed by photolithography to relieve stress on the chip.

The rewiring metal deposition step shown in FIG. 2B is performed by sputtering the rewiring metal 1 on the wafer.
3. Deposit, for example, 400 mm thick chromium and 8000 mm thick aluminum.

The rearrangement wiring forming step shown in FIG.
Aluminum and chromium are each etched using a photolithography method to form a rewiring pattern 14.

In the process of forming a redistribution polyimide film shown in FIG. 2D, polyimide is applied to the wafer on which the redistribution wiring has been formed, a new pad is opened by a photolithography method, and a redistribution polyimide film 16 is formed. I do. By these wafer processes, relocation wiring for moving the original pad of the IC to the new pad position is completed.

FIG. 3 shows a bump electrode forming step which is an embodiment of another wafer processing step. The protruding electrode forming step includes:
This is a step of forming projecting electrodes on the bonding pads on each IC on the wafer. In the step of forming a polyimide film shown in FIG. 3A, a polyimide is applied on a wafer, and a bump polyimide film 6 is formed by photolithography to relieve stress on the chip.

In the UBM deposition step shown in FIG. 3B, the UBM 7 on the wafer, for example,
Deposit 8000% of aluminum, 100% of chromium and 8000% of copper.

In the step of forming a plating resist shown in FIG. 3C, a plating resist 16 having an opening in the projection electrode portion is formed by a photolithography method in order to form a projection electrode on the pad by electroplating.

In the plating step shown in FIG. 3D, copper and solder are deposited by electroplating to form plated bumps 17.

In the plating resist stripping step shown in FIG. 3E, the plating resist 16 that is no longer needed is stripped with a stripping solution.

In the UBM etching step shown in FIG. 3F, the electroplating UBM which is no longer required
With the exception of the portion under 7, the copper in the UBM 7 is etched and stripped by the copper etching solution, the aluminum in the UBM 7 is etched by the aluminum etching solution, and the chromium in the UBM is lifted off by aluminum using the plating bump 17 as a mask.

In the rounding step shown in FIG. 3G, the solder of the plated bumps 17 is reflowed by using a flux to form the solder bumps 8 serving as the protruding electrodes. By performing these wafer processes, the protruding electrodes are completed.

[0047]

As described above, according to the semiconductor manufacturing method of the present invention, the position data of the defective chip generated in the semiconductor manufacturing process is recorded in advance in the electronic data, and then the wafer processing is performed. In addition to not only preventing defects that occur from element failure marks in the process, but also attaching defect marks to element failure chips,
By providing a defective mark on a defective electrode chip generated by wafer processing, it is possible to provide a semiconductor manufacturing method which is excellent in reliability and productivity.

Further, by applying the rearrangement wiring step to the wafer processing, it is possible to provide a semiconductor manufacturing method excellent in reliability and productivity in the rearrangement wiring step.

Further, by applying the bump electrode forming step to wafer processing, it is possible to provide a semiconductor manufacturing method which is excellent in reliability and productivity in bump electrode formation.

Further, since the defect data recording step is a step of reading a defect mark added in the semiconductor manufacturing step, the present invention can be applied without changing the conventional semiconductor manufacturing step.

Further, since the defective mark formed in the semiconductor manufacturing process is an organic ink, not only the materials generally used in the semiconductor manufacturing process can be used, but also the defective mark can be easily peeled off.

In addition, since the defective mark removing step is provided after the defective mark recording step, the present invention can be applied without changing the conventional semiconductor manufacturing step.

Further, by peeling off the defective mark by peeling off the polyimide film on the wafer, it becomes possible to apply the defective mark regardless of the type of organic ink.

The use of organic ink for the first defective mark is an easy-to-use material.

The use of organic ink for the second defective mark is a material that is easy to use.

Further, since the first defective mark and the second defective mark are made of the same organic ink material, when the IC chip in the wafer is mounted in a later process, the defective mark can be easily recognized and automation can be easily performed. Become.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a semiconductor manufacturing process according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a relocation wiring forming step according to the embodiment of the present invention.

FIG. 3 is an explanatory view showing a protruding electrode forming step according to the embodiment of the present invention.

FIG. 4 is an explanatory view showing a conventional semiconductor manufacturing process.

FIG. 5 is an explanatory view showing a conventional semiconductor manufacturing process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wafer 2 Aluminum pad 3 Passivation film 4 Polyimide insulating film 5 Device failure mark 6 Bump polyimide film 7 UBM 8 Solder bump 9 First failure mark 10 Second failure mark 11 IC chip

Claims (10)

[Claims] In a semiconductor manufacturing method for processing a wafer in which a plurality of IC chips having a plurality of bonding pads are arranged, a defect data recording step of recording position data of a defective chip generated in a semiconductor manufacturing process into electronic data. A wafer processing step of processing the wafer, a first defect mark providing step of providing a defective mark on a defective chip on the wafer based on the electronic data, and a first step of attaching a defective mark to the defective chip generated in the wafer processing step. 2. A method for manufacturing a semiconductor, comprising: two defect mark providing steps. 2. The method according to claim 1, wherein the wafer processing step includes a relocation wiring step of moving the bonding pad to a new bonding pad position having a different position. 3. The semiconductor manufacturing method according to claim 1, wherein said wafer processing step includes a step of forming a bump electrode on said wafer. 4. The method according to claim 1, wherein the defect data recording step is a step of reading a defect mark previously attached to a defective chip generated in the semiconductor production step. 5. The method according to claim 4, wherein the defective mark is an organic ink. 6. The method of manufacturing a semiconductor device according to claim 1, wherein said defective data recording step includes a defective mark peeling step of peeling said defective mark after a step of reading the defective mark. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the step of peeling off the defective mark comprises peeling off an underlying polyimide film covering the wafer. 8. The method according to claim 1, wherein the defect mark used in the first defect marking step is an organic ink.
8. The method for manufacturing a semiconductor according to items 7 to 7. 9. The method according to claim 1, wherein the defect mark used in the second defect marking step is an organic ink. 10. The method of manufacturing a semiconductor according to claim 9, wherein the organic ink used in the first defect marking step and the second defect marking step are the same.