JPH11225137A - Digital signal synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal synchronization circuit that suppresses jitter attended with synchronization detection of a digital signal to enhance performance of a system. SOLUTION: The circuit is provided with a 1st clock sample circuit 101 that samples a synchronizing signal 20 at the leading edge and the trailing edge of a local clock 21, a 2nd clock sample circuit 102 that samples the synchronizing signal 20 at the trailing edge and the leading edge of the local clock 21, and a priority edge selection circuit 103 that samples a change point of the synchronizing signal sampled by the 1st clock sample circuit 101 and the 2nd clock sample circuit 102 based on a faster synchronizing lock edge.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal synchronization circuit, and more particularly, to a digital signal synchronization circuit in which jitter accompanying synchronization detection is always set to one clock or less to improve system performance.

[0002]

2. Description of the Related Art When synchronizing two digital signals operating at different frequencies, it is common practice to sample the digital signal to be operated synchronously with the other clock.

However, the problem with this method is the metastable state of the flip-flop circuit used for sampling. In order to avoid this metastable state, it is inevitable that the clock to be operated synchronously must be operated. Sample is required twice. However, in order to minimize the time required for synchronizing the two samples with this clock, even if each of them is configured as an anti-phase clock, a variation of at least half a clock and a maximum of 1.5 clocks will be obtained. Will have the potential to occur.

Next, a digital signal synchronization detecting method will be described by taking a scanner for reading data line by line as an example.

The circuit block of the scanner can be roughly divided into a main control section for controlling the entire system, a data reading section which operates in accordance with instructions from the main control section, and a processing section for the read data. At this time, the operation in the reading part from the specifications on the system,
When controlled by an operation start command (synchronization signal) for each line from the main control unit, a circuit operation synchronized with this signal is required in the reading section. In order to generate the synchronized timing, it is necessary to sample an operation start instruction (synchronous signal) with a local clock. However, in order to avoid the metastable state of the flip-flop circuit used as a method for realizing the same, Regardless of the state of the clock edge, at least two samples are required.
However, considering two clock samples, synchronization detection time for at least 0.5 clocks and 1.5 clocks at the maximum is required due to sampling at both edges of the local clock. ,
This is an operational jitter after the main control unit and the reading unit that attempts to move in synchronization with the main control unit.

Therefore, there is a problem that the jitter in the operation of the scanner system is a maximum of 1.5 clocks, and only 1.5 clocks are required as the synchronization detection time.

[0007]

As described above, in the conventional digital signal synchronization circuit, when synchronizing two digital signals, a method of using a flip-flop circuit to sample twice with a clock to be operated synchronously is used. Therefore, there is a problem that a maximum of 1.5 clocks of jitter variation may occur.

An object of the present invention is to provide a digital signal synchronization circuit which suppresses jitter accompanying synchronization detection and improves system performance.

[0009]

A first clock sampling circuit samples a synchronization signal at the rising and falling edges of a local clock, and a second clock sampler samples the synchronization signal at the falling edges and rising edges of a local clock. And a priority edge selection circuit that samples a change point of the synchronization signal sampled by the first clock sampling circuit and the second clock sampling circuit at an earlier synchronization clock edge.

The first clock sampling circuit includes a first-stage first flip-flop circuit that samples and outputs a synchronization signal at the rise of the local clock, and a local clock for avoiding metastable of the first-stage first flip-flop circuit. A second flip-flop circuit at the next stage that samples a synchronization signal at the falling edge and outputs a synchronized signal.

The second clock sampling circuit includes a first-stage third flip-flop circuit that samples and outputs a synchronization signal at the fall of the local clock, and a local clock for avoiding metastable of the first-stage third flip-flop circuit. And a fourth flip-flop circuit at the next stage for sampling a synchronization signal at the rising edge and outputting a synchronized signal.

The priority edge selection circuit is an OR logic circuit for inputting output signals generated by the first clock sample circuit and the second clock sample circuit, respectively, and divides the signal from the OR logic circuit to generate an exclusive logic signal. And a logic generation circuit for taking a sum.

The OR logic circuit is characterized in that the same polarity signals of the output signals generated by the first clock sample circuit and the second clock sample circuit are input.

The final synchronizing signal output from the logic generating circuit which divides the signal from the OR logic circuit and takes an exclusive OR is characterized in that the jitter caused by synchronization detection is one clock or less.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a digital signal synchronization circuit 1 according to the present invention.
FIG. 2 is a circuit block diagram showing an embodiment of the present invention.

Referring to FIG. 1, a digital signal synchronizing circuit 100 of the present invention transmits a synchronizing signal 20 to a local clock 2.
A first clock sampling circuit (A) 101 for sampling at the rising and falling edges of the first clock signal;
Clock sampling circuit (B) 1 which samples the clock at the falling and rising of the local clock 21
02, and a priority edge selection circuit (C) that samples a change point of the synchronization signal sampled by the first clock sampling circuit (A) 101 and the second clock sampling circuit (B) 102 at an earlier synchronization clock edge. ) 103, the first clock sampling circuit (A) 1
01 denotes a first-stage first flip-flop circuit (U1A) 31 that samples and outputs the synchronization signal 20 at the rise of the local clock 21 and a first-stage first flip-flop circuit (U1A) 31 for avoiding metastable. A second flip-flop circuit (U1B) 32 at the next stage that samples the synchronization signal 20 at the falling edge of the clock 21 and outputs a synchronized signal.

The second clock sampling circuit 102
Is the synchronization signal 20 at the falling of the local clock 21.
And a synchronizing signal 20 at the rising edge of the local clock 21 for avoiding metastable of the first stage third flip-flop circuit (U2A) 33 and the first stage third flip-flop circuit (U2A) 33 for sampling and outputting A fourth flip-flop circuit (U2B) 34 at the next stage for outputting a synchronized signal.

Further, the priority edge selection circuit 103 includes OR logic circuits 41 and 42 for inputting output signals generated by the first clock sample circuit (A) 101 and the second clock sample circuit (B) 102, respectively. , And a logic generation circuit 51 which divides the signal from the OR logic circuits 41 and 42 and takes an exclusive OR, and the OR logic circuits 41 and 42
Are input with the same polarity signals of the output signals generated by the first clock sample circuit (A) 101 and the second clock sample circuit (B) 102, and output signals from the OR logic circuits 41 and 42. A final synchronization signal 61 is output from the logic generation circuit 51 that divides the frequency and performs an exclusive OR operation.

Next, the operation of the digital signal synchronizing circuit 100 of the present invention configured as described above will be described with reference to a detailed timing chart of a digital signal shown in FIG. 2 and FIG.

Referring to FIGS. 1 and 2, a first clock sampling circuit (A) 101 is provided with a rising clock 21a, a rising clock 21a of a first flip-flop circuit (U1A) 31 at the first stage.
1c, the synchronizing signal 20 is sampled, and a second flip-flop circuit (U1
B) A signal (U1B-9) which is sampled and synchronized with the falling clocks 21d and 21f of 32 is output. Further, the second clock sampling circuit (B) 102 samples the falling clocks 21d and 21e of the first stage third flip-flop circuit (U2A) 33, and further avoids metastable by a fourth flip-flop circuit of the next stage. The signal (U2B-9) sampled and synchronized by the rising clocks 21b and 21c of the circuit (U2B) 34 is output.

Therefore, the first clock sampling circuit (A) 101 and the second clock sampling circuit (B)
The synchronized signal obtained from 102 is synchronized with the falling and rising of the local clock 21, respectively.

Next, a first clock sampling circuit (A)
101 and second clock sample circuit (B) 102
Are input to the OR logic circuit (U4A) 41 and the OR logic circuit (U4B) 42 with the same polarity, and the signals are sampled earlier at the rising edge or the falling edge, respectively, by OR processing. −
3, U4B-6), and a logic generation circuit 5 which divides this signal and takes an exclusive OR.
1, a desired final synchronizing signal (U6A-3) 61 can be obtained, and the final synchronizing signal (U6A-3) 61 has a jitter of one clock or less due to synchronization detection.

The local clock 2 in the present invention
1 is not necessarily the system clock (the highest operating frequency clock in the circuit operation), and the more the high-speed logic or the high-speed sample clock is used in the circuit configuration, the more the synchronization becomes. This has the effect of reducing subsequent jitter.

For example, when the system clock of the local circuit is 10 MHz, if a clock of 40 MHz, which is four times as large as this, can be prepared, the jitter in the present circuit when using 10 MHz can be reduced to 0.25 times of jitter. It becomes possible. That is, the jitter can be logically controlled by selecting the synchronous sample clock or the constituent logic IC.

[0026]

As described above, the digital signal synchronization circuit of the present invention performs synchronization detection on both edges of the sample clock, and further extracts an earlier edge portion from the state of the detected synchronization signal to obtain the final synchronization. By using the signal, the jitter associated with the synchronization detection is always less than one clock, and there is an effect that the performance of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing one embodiment of a digital signal synchronization circuit of the present invention.

FIG. 2 is a detailed timing chart of a digital signal of the digital signal synchronization circuit shown in FIG. 1;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Digital signal synchronization circuit 101 First clock sampling circuit (A) 102 Second clock sampling circuit (B) 103 Priority edge selection circuit (C) 20 Synchronization signal 21 Local clock 21 a, 21 b Rising clock 21 c Rising clock 21 d, 21 e Falling clock 21f Falling clock 31 First flip-flop circuit (U1A) 32 Second flip-flop circuit (U1B) 33 Third flip-flop circuit (U2A) 34 Fourth flip-flop circuit (U2B) 41 OR logic circuit (U4A) 42 OR logic circuit (U4B) 51 Logic generation circuit 61 Final synchronization signal (U6A-3)

Claims (6)

[Claims] A first clock sampling circuit that samples a synchronization signal at the rising and falling edges of a local clock; and a second clock sampling circuit that samples the synchronization signal at the falling and rising edges of the local clock. A priority edge selection circuit that samples a change point of the synchronization signal sampled by the first clock sampling circuit and the second clock sampling circuit at an earlier synchronization clock edge. Signal synchronization circuit. 2. The first clock sampling circuit, wherein: a first stage first flip-flop circuit that samples and outputs the synchronization signal at a rise of the local clock;
A second-stage second flip-flop circuit that samples the synchronization signal at the fall of the local clock and outputs a synchronized signal in order to avoid metastable of the first-stage first flip-flop circuit. 2. The digital signal synchronization circuit according to claim 1, wherein: 3. The first flip-flop circuit, wherein the second clock sampling circuit samples and outputs the synchronization signal at the falling edge of the local clock;
A fourth flip-flop circuit of the next stage which samples the synchronization signal at the rising edge of the local clock and outputs a synchronized signal in order to avoid metastable of the third flip-flop circuit of the first stage. The digital signal synchronization circuit according to claim 1, wherein 4. The priority edge selection circuit includes: an OR logic circuit for inputting output signals generated by the first clock sampling circuit and the second clock sampling circuit; and a signal from the OR logic circuit. 2. The digital signal synchronization circuit according to claim 1, further comprising: a logic generation circuit for dividing and performing an exclusive OR operation. 5. The OR logic circuit according to claim 1, wherein the output signals generated by the first clock sample circuit and the second clock sample circuit have the same polarity as each other. 5. The digital signal synchronization circuit according to 4. 6. The frequency of the signal from the OR logic circuit is divided,
2. The digital signal synchronizing circuit according to claim 1, wherein the final synchronizing signal output from the logic generating circuit that takes the exclusive OR has a jitter of one clock or less due to synchronization detection.