JPH11214691A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely protect a semiconductor element from thermal breakdown, by arranging a heatsensitive element part detecting the state of heat generation of a semiconductor power element, inside a layout pattern of a metal terminal electrode of a semiconductor power element which is stuck on a greater part of one surface of a semiconductor chip. SOLUTION: A heat-sensitive polycrystalline silicon diode 15, is arranged inside a layout pattern of an aluminum electrode 9 (a source S) formed in common with a plurality of power MOS's 13 which is stuck on a greater part of the surface of a semiconductor chip. The aluminum electrode 9 is excellent in thermal conductivity, so that heat generated in the semiconductor chip is made uniform in the chip by the aluminum electrode 9, and quickly transferred to the forming position of the polycrystalline silicon diode 15. As a result, temperature difference in the semiconductor chip is also restrained, so that local element breakdown due to local current concentration or local temperature rise can be restrained.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a temperature detecting function. 2. Description of the Related Art Conventionally, for example, a plurality of M
2. Description of the Related Art A power MOS transistor switch configured so that unit cells having an OS transistor structure are connected in parallel is known. A MOS transistor switch has a limit in power consumption. Exceeding the limit causes overheating and further self-destruction of the MOS transistor switch. MOS
A transistor switch is usually used in connection with a load, and a voltage between the source / drain terminals and a current flowing through the transistor switch under normal operating conditions are determined by the load and the MOS transistor.
Limited to a certain value within the power consumption capacity of the transistor switch. However, if the load is inadvertently shorted, the voltage across the source / drain terminals of the MOS transistor switch will exceed the maximum supply voltage resulting in power consumption capacity, resulting in overheating of the MOS transistor switch and even overheating. It causes destruction. Therefore, in order to avoid destruction due to an abnormal junction temperature rise during the operation of the semiconductor device, the temperature rise of the semiconductor substrate accompanying the heat generation of the semiconductor device by the heat-sensitive device is avoided. It is desirable to detect and control the semiconductor element by the detection signal to protect the semiconductor element from thermal destruction. Accordingly, the present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device capable of reliably protecting a semiconductor element from thermal destruction. In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a semiconductor chip on which a semiconductor power element that generates high heat when a current flows in a conductive state is formed. A heat-sensitive element portion for detecting a heat generation state of the semiconductor power element is arranged inside a layout pattern of metal terminal electrodes of the semiconductor power element which is attached to most of the one surface side of the semiconductor chip. Features. According to the present invention, when the temperature of the semiconductor substrate rises abnormally, that is, when the heat generation temperature of the semiconductor power element becomes abnormally high, the temperature rise of the semiconductor power element can be reduced. It can be detected by the part. here,
The heat-sensitive element portion is arranged inside the layout pattern of the metal terminal electrodes of the semiconductor power element attached to the majority of the one surface side of the semiconductor chip, and the metal terminal electrodes have good thermal conductivity, for example. Since the semiconductor chip is made of metal such as aluminum, the heat generated in the semiconductor chip is quickly transferred to the heat-sensitive element portion in the semiconductor chip while being made uniform by the metal terminal electrodes. Therefore, the temperature difference in the semiconductor chip on which the semiconductor power element is formed can be suppressed, the local element destruction caused by local current concentration or local temperature rise can be suppressed, and the element performance of the semiconductor power element can be sufficiently improved. The heat generation state of the semiconductor chip can be accurately and responsively transmitted to the thermosensitive element portion while exerting the same effect. As a result, the semiconductor power element can be reliably protected from thermal destruction. The present invention will be described below in detail with reference to an embodiment shown in the drawings. 1 and 2 show an example in which the present invention is applied to a vertical power MOS transistor (hereinafter referred to as a power MOS) having a self-overheating protection function. FIG. 1 is a schematic plan view of a semiconductor chip. FIG. 2 is a sectional view taken along line α-α in FIG. A plurality of power MOSs 13 as active elements are connected in parallel to most of the entire semiconductor substrate A to form a multi-source structure, forming a power region M. A plurality of polycrystalline silicon diodes 15 as heat-sensitive elements are formed in series at a central portion of the semiconductor substrate A, in other words, a portion where heat radiation is least likely to occur, and a portion where the temperature is likely to be high. A MOS transistor 14, a polycrystalline silicon resistor 16, and a constant voltage zener diode 17 are formed to form a control region C as a whole. Further, a bonding pad portion B for applying a voltage (V _in ) from outside is formed on the semiconductor substrate A. Each element of the power region M and the control region C and the bonding pad portion B are electrically connected to each other. Next, the configuration will be described in detail with reference to FIG. 1 is an N ^{+ type} silicon substrate, 2 is an N ^{− type} silicon epitaxial layer, 3 and 3a are deeply diffused P type diffusion layers, 4 is a P type diffusion layer, and 5, 5a, 5b and 5c are N ⁺ types.
The diffusion layers 11 and 11 are P ^{+ -type} diffusion layers, and the P-type diffusion layers 3 and 3a and the N ^{+ -type} diffusion layers 5, 5a, 5b and 5c are simultaneously formed in the same diffusion step. The MOS structure of the power MOS 13 includes a drain D including a silicon epitaxial layer 2, a silicon substrate 1, and a drain electrode 12, a gate G including a polycrystalline silicon layer 7 formed via a gate oxide film 6, and an interlayer on the surface. Power M via insulating film 8
The source 13 is composed of an aluminum electrode 9 that covers the entire surface of the OS 13. When a voltage is applied to the gate G, an N-type channel is formed in the portion of channel ch in the drawing, and a current flows between the source S and the drain D. . The reason why the diffusion layer 4 partially overlaps with the diffusion layer 3 and that the diffusion layer 3 is deeply diffused is to protect the overvoltage and to set a predetermined breakdown voltage. Next, the MOS structure of the lateral MOS transistor 14 has a source S1 and a drain D1 formed of aluminum electrodes 9a and 9b on diffusion layers 5a and 5b, respectively, and a gate formed of a polysilicon layer 7a formed via a gate oxide film 6a. G1 in FIG. 3 operates when a voltage is applied to the gate G1.
And an N-type channel is formed in the portion, and a current flows between the source S1 and the drain D1. Constant voltage zener diode 17
Is formed of a diffusion layer 5c and a diffusion layer 11, and aluminum electrodes 9c and 9d are formed on the surface thereof, respectively. Next, a part of the surface of the diffusion layer 3a is thermally oxidized to form an insulating film (SiO 2).
To form a ₂ film) 10. Then, a polycrystalline silicon resistor 16 and a polycrystalline silicon diode 15 as a thermal element are formed on the insulating film 10. Polycrystalline silicon resistor 16
Is formed of a polycrystalline silicon layer 7c, an interlayer insulating film 8, and aluminum electrodes 9g and 9h. The polycrystalline silicon diode 15 selectively diffuses the polycrystalline silicon layer 7b to form a PN junction, and forms aluminum electrodes 9e and 9f thereon with a part of the interlayer insulating film 8 interposed therebetween. The gate oxide films 6 and 6a, the polycrystalline silicon layers 7, 7a, 7b, 7c, and the aluminum electrodes 9, 9 in the configuration of the embodiment described above.
a, 9b, 9c, 9d, 9e, 9g, 9h can be manufactured in the same process. The above-mentioned elements are wired together as shown in the equivalent circuit diagram of FIG. Each element is arranged, for example, as shown in the top view of FIG. That is, the lateral MOS transistor 14 and the polycrystalline silicon diode 1 are provided in the control region C.
5, a resistor 16C and a constant voltage zener diode 17 are arranged, and an aluminum electrode 9 covering the surface of the power region.
And each of them is electrically connected via a connection path C1. In the figure, reference numeral 20 denotes the same point as 20 in FIG. 3 and represents an external connection terminal of the aluminum electrode 9. Here, the external connection terminal 20 electrically connected to the anode of the constant voltage zener diode 17 is fixed to the ground potential which is the source potential.
Therefore, as shown in FIG. 2, the P-type diffusion layer 3a electrically connected to the diffusion layer 11 of the constant voltage zener diode 17 is also fixed to the ground potential which is the source potential. A part of the voltage applied to the bonding pad portion B is supplied to the gate electrode G of the power MOS 13 via the resistor 16b disposed beside the bonding pad portion B.
1 or the drain D1 of the lateral MOS transistor 14
And the others are applied to the gate G1 of the lateral MOS transistor 14 via a resistor 16a or the like arranged horizontally. Next, the overall operation will be described with reference to the equivalent circuit diagram of FIG. In the figure, reference numerals are common to those in FIGS. Here, 16a, 16b and 16c are polycrystalline silicon resistors, _RL is an external load resistance, and _VDD is an external power supply.
When the silicon substrate temperature is normal, that is, when the power MO
When the junction temperature in S13 is the normal temperature, the applied voltage V
_The power MOS 13 is turned on by _in ,
When the silicon substrate temperature is abnormally high,
When the junction temperature in S13 rises abnormally, the forward voltage of the polycrystalline silicon diode 15, which is a heat-sensitive element, drops because it has a constant negative temperature coefficient, and the voltage between the terminals of the resistor 16c (that is, the lateral MOS transistor 14). Gate G
1-source S1). When the voltage exceeds a certain level, the lateral MOS transistor 14 is turned on.
If the resistance value of the resistor 16b is sufficiently larger than the on-resistance value of the lateral MOS transistor 14, the junction is changed as shown in the graph showing the change in the junction temperature between the potential V22 of ₂₂ and the potential V23 of ₂₃ in FIG. When the temperature is around 130 ° C. (protection operation temperature), V ₂₂ rapidly drops to almost 0 V, so that the power MO
S13 is forcibly turned off, so that destruction of the element due to a rise in the junction temperature can be avoided. Here, a polycrystalline silicon diode 15, which is a heat-sensitive element, has a layout pattern of an aluminum electrode 9 (source S) formed in common with a plurality of power MOSs 13 attached to most of the front surface side of the semiconductor chip. It is located inside. The aluminum electrode 9 has good thermal conductivity, and the heat generated in the semiconductor chip is quickly transferred to the position where the polycrystalline silicon diode 15 is formed while being made uniform by the aluminum electrode 9 in the semiconductor chip. Therefore, a temperature difference in the semiconductor chip can be suppressed, a local element destruction caused by a local current concentration or a local temperature rise can be suppressed, and the heat generation of the semiconductor chip can be suppressed while sufficiently exhibiting the element performance of the power MOS 13. The state can be accurately transmitted to the polycrystalline silicon diode 15 which is a thermal element with good responsiveness. Thereby, protection of the power MOS 13 from thermal destruction can be ensured. Further, according to the configuration of the above-described embodiment, by forming the insulating film 10, it is possible to provide a semiconductor device capable of trimming individual elements and having no parasitic operation. An abnormal rise in temperature
Since the heat-sensitive element is arranged in the central control region C where the temperature tends to be high, detection can be performed more accurately. In addition, since the manufacturing process can be performed in the same process at the same time, simplification is achieved, leading to cost reduction, and furthermore, a large number of insulating films are formed. Crystal silicon resistor 16c
And the protection operation temperature can be arbitrarily set according to the resistance value and the number of polycrystalline silicon diodes 15 connected in series. Since the resistance value of the polycrystalline silicon resistor 16c can be individually trimmed, there is an excellent effect that the protection operation temperature can be precisely controlled after manufacturing. Since the silicon epitaxial layer 2 forms a part of the drain of the power MOS 13, its potential changes in accordance with the operation state of the power MOS 13, and the potential of the polycrystalline silicon diode 15 formed on the silicon epitaxial layer 2 changes. According to the present embodiment, a P-type diffusion layer 3a is formed in the silicon epitaxial layer 2 and a polycrystalline silicon diode Since the number 15 is formed, such a problem can be eliminated. To explain this point in detail, assuming a structure without the P-type diffusion layer 3a, the insulating film (SiO ₂ film or the like) 10 is polarized according to the potential of the silicon epitaxial layer 2, and the insulation of the polycrystalline silicon diode 15 is reduced. Electric charges are induced on the surface on the film 10 side. In the case of this embodiment, for example, when the silicon epitaxial layer 2 becomes high potential, the polycrystalline silicon diode 1
5, the impurity concentration at the PN junction changes.
Temperature characteristics at the forward voltage change, and the accuracy of temperature detection deteriorates. In an extreme case, an inversion layer is formed below the P-type region of the polycrystalline silicon diode 15 to perform a parasitic operation like a MOS transistor, so that temperature detection is no longer possible. According to the present embodiment, since the P-type diffusion layer 3a is formed under the polycrystalline silicon diode 15, the PN between the P-type diffusion layer 3a and the silicon epitaxial layer 2 is formed.
Since the junction is formed and can be electrically separated from the drain potential of the power MOS 13, the polysilicon diode 15 is not affected by the drain potential, and the above-described parasitic operation can be eliminated. There is an effect that highly accurate temperature detection can be performed. A constant voltage zener diode 17 for supplying a constant voltage to both ends of the polysilicon diode 15 is formed in the bulk (in the P-type diffusion layer 3a on the surface of the silicon epitaxial layer 2). Therefore, a constant voltage can be provided with higher precision than a constant voltage zener diode formed of a polycrystalline body. In other words, a constant voltage supplied to both ends of the polycrystalline silicon diode 15 can be provided with high precision to a target constant voltage value. It can be adjusted, and the temperature detection by the polycrystalline silicon diode 15 can be made more accurate. In addition, it is possible to further suppress variations in the obtained constant voltage value between chips, wafers, and lots, and it is also possible to suppress variations in protection operation temperature between products. The present invention is not limited to the above embodiment,
Various modifications are possible as follows. (1) The elements in the control region C are all insulating films 10
The lateral MOS transistor 14a may be formed on the insulating film 10 as shown in the second embodiment of FIG.
Only the constant voltage zener diode 17 may be formed in the diffusion layer 3a. Conversely, the lateral MOS transistor 14a
May be formed in the diffusion layer 3a, and the constant voltage zener diode 17 may be formed on the insulating film 10. Alternatively, the polycrystalline silicon resistor 16 may be formed in the diffusion layer 3a. (2) As shown in the sectional view taken along the line α-α in FIG. 1 as a third embodiment of FIG. 6 and an equivalent circuit diagram thereof in FIG. 7, a P-type channel MOS transistor 24 is formed on the insulating film 10. (24a, 24b, 24c) and an N-type channel MOS transistor 25 (25a, 25b) are formed, and a complementary MOS transistor (C-MOS) is formed to amplify the potential V22 of ₂₂ and increase the potential V of 26. _It may be ₂₆ . Further, a C-MOS configuration in which a P-type channel MOS transistor 24 (24a, 24b, 24c) is formed on the insulating film 10 and an N-type channel MOS transistor 25 (25a, 25b) is formed in the diffusion layer 3a may be used. [0019] Since the C-MOS are connected in multiple stages, according to the present embodiment, the input-output characteristics, the product of input-output characteristics of each stage, graph of the junction temperature and the V ₂₃ and V ₂₆ in FIG. 8 As shown in (5), the potential V26 of ₂₆ can be sharply reduced, and therefore, the power MOS 13 can be turned off rapidly with an increase in junction temperature. The number of C-MOS connection stages is not limited, and the larger the number, the sharper the input / output characteristics. In FIGS. 6 and 7, the same reference numerals are used for the same components as those in FIGS. 2 and 3, respectively. (3) The arrangement of the polycrystalline silicon diode 15 as the control region C or the temperature-sensitive element is not limited to the central portion of the semiconductor substrate A as in the above-described embodiment.
For example, as shown in FIGS. 9A to 9E showing schematic plan views of the semiconductor device, the semiconductor devices may be symmetrically arranged at a plurality of locations. According to the experimental results of the present inventors, there is no self-overheating protection function as shown in FIG. 10 showing the relationship between the number of locations and the failure rate when the load is short-circuited and the power MOS 13 is forcibly heated. (0 locations), the defect rate is 100
%, When the polycrystalline silicon diode 15 is arranged only at one location, that is, only at the center of the semiconductor substrate A, the defect rate is greatly reduced.
%. In a case where heat is generated by consuming a large amount of power in a short time such as a load short-circuit, the temperature distribution in the semiconductor substrate A tends to be non-uniform, so that the protection function is insufficient with one arrangement. Therefore, it is effective to arrange a plurality of positions as in this example. (4) In the above embodiment, the power MOS 13 and the lateral MOS transistor 14 are shown as N-type channels, but the present invention is not limited to this, and P-type channels may be used. In this case, the diffusion layer corresponding to the reference numeral 3a in the above embodiment is of the N-type conductivity type. (24
a, 24b, 24c) may be formed in the diffusion layer 3a. Normally, the channel mobility of a MOS transistor in a polycrystalline semiconductor is smaller than that in a single crystal semiconductor, but by forming as described above, the N-channel MOS transistor becomes a P-channel
Since the carriers are electrons compared to the OS transistor, a transistor having high channel mobility can be easily manufactured.
When the configuration is S, mobility is easily balanced. (5) The semiconductor element having the active function is not limited to the power MOS 13, but may be a bipolar transistor, a power IC, or the like. Further, the thermal element is not limited to the polycrystalline silicon diode 15, but may be a thermistor or the like.
Further, it goes without saying that the configuration of the control unit is not limited to the configuration shown in the embodiment. (6) In the embodiment, the polycrystalline silicon resistor 16 is used as the resistor. However, the resistor is not limited to this and may be a resistor such as tantalum nitride.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view of a semiconductor device showing one embodiment of the present invention. FIG. 2 is a sectional view taken along line α-α in FIG. FIG. 3 is an equivalent circuit diagram of FIGS. 1 and 2; 4 is a graph showing the relationship between the junction temperature and the V ₂₂ and V _23. FIG. 5 is a sectional view showing a second embodiment. FIG. 6 is a sectional view taken along the line α-α in FIG. 1 as a third embodiment. FIG. 7 is an equivalent circuit diagram of FIG. 6; 8 is a graph showing the relationship between V ₂₃ and V ₂₆ of the embodiment junction temperature of FIG. FIG. 9 is a schematic plan view of a semiconductor device in which a plurality of polycrystalline silicon diodes are arranged. FIG. 10 is a diagram showing the relationship between the number of locations and the defect rate. FIG. 11 is a top view showing a specific arrangement of the embodiment in FIG. 1; [Explanation of Symbols] 2 Silicon epitaxial layer 3a P-type diffusion layer 9 Aluminum electrode 10 Insulating film (SiO ₂ film) 13 Vertical power MOS transistor 15 Polycrystalline silicon diode as thermal element

Claims (1)

Claims: (1) In a semiconductor chip on which a semiconductor power element which generates high heat when a current flows in a conducting state is formed, most of the one surface side of the semiconductor chip is the semiconductor power element. A semiconductor device, wherein a metal terminal electrode is attached, and a heat-sensitive element portion for detecting a heat generation state of the semiconductor power element is arranged inside a layout pattern of the metal terminal electrode. (2) The semiconductor power element includes a plurality of M connected in parallel.
2. The semiconductor device according to claim 1, wherein the semiconductor device has an OS transistor structure, and the metal terminal electrode is a metal electrode commonly formed in the plurality of MOS transistor structures. (3) The semiconductor device according to claim 1 or 2, wherein the heat-sensitive element section is disposed substantially at a center of the semiconductor chip. (4) The semiconductor device according to any one of claims 1 to 3, wherein the heat-sensitive element portion is formed of polycrystalline silicon disposed on a surface of a semiconductor substrate via an insulating film. (5) A semiconductor region that forms a PN junction with a region of the semiconductor substrate where the semiconductor power element is formed is formed in a surface region of the semiconductor substrate located below the heat-sensitive element unit. The semiconductor device according to claim 4. (6) The semiconductor device according to claim 5, wherein the semiconductor region has the same potential as the metal terminal electrode.