JPH11214549A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

Info

Publication number
JPH11214549A
JPH11214549A JP10008708A JP870898A JPH11214549A JP H11214549 A JPH11214549 A JP H11214549A JP 10008708 A JP10008708 A JP 10008708A JP 870898 A JP870898 A JP 870898A JP H11214549 A JPH11214549 A JP H11214549A
Authority
JP
Japan
Prior art keywords
insulating substrate
semiconductor device
package
semiconductor chip
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10008708A
Other languages
Japanese (ja)
Other versions
JP3339397B2 (en
Inventor
Chikanori Kanemoto
慎典 金元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP00870898A priority Critical patent/JP3339397B2/en
Publication of JPH11214549A publication Critical patent/JPH11214549A/en
Application granted granted Critical
Publication of JP3339397B2 publication Critical patent/JP3339397B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract

PROBLEM TO BE SOLVED: To enhance connection reliability and adapt for a semiconductor chip of a minute size by a method wherein an insulated hollow package is secured onto one main face of an insulated substrate located apart from a connection position of the semiconductor chip so as to seal the semiconductor chip connected to the one main face of the insulated substrate. SOLUTION: A semiconductor chip 3 is connected to an insulated substrate 1 excellent in mechanical strength. A hollow package 6 is secured onto an insulated substrate 1 located apart from a connection position of the semiconductor chip 3 so as to seal the semiconductor chip 3 in a hollow package 6. Thus, as an outer force by the package 6 is not applied on the semiconductor chip 3, connection reliability of a semiconductor device can be enhanced. As a hollow part of the package 6 can be formed with high precision, it can be adapted for the semiconductor chip 3 of a minute size. As a sparse part 7 is formed at a location to which the hollow package 6 is secured, it is possible to secure the package 6 with an excellent close adhesion.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、半導体装置及び
その製造方法に係り、詳しくは、中空状のパッケージを
有する半導体装置及びその製造方法に関する。The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a hollow package and a method for manufacturing the same.

【０００２】[0002]

【従来の技術】半導体装置の代表として知られているメ
モリやマイクロプロセッサ等のＬＳＩ（大規模集積回
路）に用いられるパッケージの１つとして、樹脂等の絶
縁性材料から構成された中空状のものが知られている。
この中空状のパッケージは、半導体チップ上におけるボ
ンディングワイヤ等の配線、あるいは電極パッド等の信
号経路を中空内に配置することにより、寄生容量を低減
することができるので、特に高周波用半導体装置に適用
して効果的である。2. Description of the Related Art One of packages used for LSIs (large-scale integrated circuits) such as memories and microprocessors, which are known as representatives of semiconductor devices, is a hollow package made of an insulating material such as resin. It has been known.
Since this hollow package can reduce parasitic capacitance by arranging wiring such as bonding wires on a semiconductor chip or signal paths such as electrode pads in the hollow, it is particularly applied to a high frequency semiconductor device. It is effective.

【０００３】図１８は、この種の半導体装置の一例を示
すもので、特開昭６２−４２４４０号公報に開示された
構造を示している。同公報記載の半導体装置は、ＩＣチ
ップ５１がダイスボンディングされたリードフレーム５
２の表裏面に中空状の一次封止樹脂シート５３が溶着さ
れ、その一次封止樹脂シート５３は二次封止樹脂５４に
よりモールドされている。ＩＣチップ５１の電極パッド
とリードフレーム５２のリード部との間にボンディング
された金属細線５５は、上記一次封止樹脂シート５３の
中空内に配置されている。FIG. 18 shows an example of this type of semiconductor device, and shows a structure disclosed in Japanese Patent Application Laid-Open No. 62-42440. The semiconductor device described in the publication is a lead frame 5 in which an IC chip 51 is die-bonded.
A primary sealing resin sheet 53 having a hollow shape is welded to the front and back surfaces of the second sealing resin sheet 53, and the primary sealing resin sheet 53 is molded with a secondary sealing resin 54. The thin metal wires 55 bonded between the electrode pads of the IC chip 51 and the lead portions of the lead frame 52 are arranged in the hollow of the primary sealing resin sheet 53.

【０００４】しかしながら、特開昭６２−４２４４０号
公報に記載の半導体装置は、パッケージが一次封止樹脂
シート５３と二次封止樹脂５４との二重構造になってい
るので、構造が複雑なため、製造コストがアップすると
いう欠点がある。However, the semiconductor device described in Japanese Patent Application Laid-Open No. Sho 62-42440 has a complicated structure because the package has a double structure of the primary sealing resin sheet 53 and the secondary sealing resin 54. Therefore, there is a disadvantage that the manufacturing cost increases.

【０００５】そこで、この欠点を解消する手段として、
特開平５−２９１３２２号公報に記載の半導体装置が提
供されている。この公報に記載の半導体装置は、図１９
に示すように、絶縁フィルム６１ｓに貼り付けたリード
パターン６１ｄからなるフィルムキャリア６１上に半導
体チップ６２がフィースダウンボンディングされ、半導
体チップ６２の表面（能動面）側に凹部６３を形成した
封止用樹脂シート６３ａが貼り付けられるとともに、そ
の裏面側には他の封止用樹脂シート６３ｂが貼り付けら
れている。半導体チップ６２の電極パッド６２ａは、封
止用樹脂シート６３ａの凹部６３による中空内に配置さ
れている。[0005] Therefore, as a means for solving this drawback,
A semiconductor device described in JP-A-5-291322 is provided. The semiconductor device described in this publication is shown in FIG.
As shown in FIG. 7, a semiconductor chip 62 is face down bonded on a film carrier 61 composed of a lead pattern 61d attached to an insulating film 61s, and a concave portion 63 is formed on the surface (active surface) side of the semiconductor chip 62 for sealing. The resin sheet 63a is adhered, and another sealing resin sheet 63b is adhered to the back surface side. The electrode pad 62a of the semiconductor chip 62 is arranged in the hollow formed by the concave portion 63 of the sealing resin sheet 63a.

【０００６】特開平５−２９１３２２号公報に記載の半
導体装置を製造するには、図２０に示すように、まず、
フィルムキャリア６１上にフィースダウンボンディング
され半導体チップ６２の表面側に、予め未硬化樹脂の半
導体チップ６２と対向する主面に選択的に光照射を行っ
て、一部分の樹脂のみを硬化させて凹部６３を形成した
封止用樹脂シート６３ａを配置するとともに、半導体チ
ップの裏面側に封止用樹脂シート６３ｂを配置する。次
に、封止用樹脂シート６３ａ及び６３ｂをそれぞれ、半
導体チップ６２の表面側及び裏面側に貼り付けた後、圧
縮成形処理を行うことにより、上記の半導体装置が製造
される。In order to manufacture the semiconductor device described in Japanese Patent Application Laid-Open No. 5-291322, first, as shown in FIG.
On the surface side of the semiconductor chip 62 which is face-down bonded onto the film carrier 61, the main surface facing the semiconductor chip 62 of the uncured resin is selectively irradiated with light in advance, and only a part of the resin is cured to form the concave portion 63. Is formed, and the sealing resin sheet 63b is arranged on the back side of the semiconductor chip. Next, after the sealing resin sheets 63a and 63b are respectively attached to the front side and the back side of the semiconductor chip 62, a compression molding process is performed to manufacture the above semiconductor device.

【０００７】ここで、上記封止用樹脂シート６３ａに部
分的に凹部６３を形成するには、上記の光照射の他に、
紫外線照射、赤外線照射及び熱風吹き付け等の部分架橋
手段が利用されている。Here, in order to partially form the concave portion 63 in the sealing resin sheet 63a, in addition to the above-described light irradiation,
Partial cross-linking means such as ultraviolet irradiation, infrared irradiation, and hot air blowing are used.

【０００８】[0008]

【発明が解決しようとする課題】しかしながら、特開平
５−２９１３２２号公報に記載の従来技術では、半導体
チップが機械的強度に劣るリードパターンにフェースダ
ウンボンディングされ、また、半導体チップに外力が加
わり易い構造になっているので、接続信頼性が低い、と
いう問題がある。すなわち、図１９及び図２０から明ら
かなように、半導体チップ６３がボンディングされるリ
ードパターン６１ｄは絶縁フィルム６１ｓによって支持
されているだけなので、機械的強度の低下は避けられな
い。また、ボンディング部分には封止用樹脂シート６３
ａが接しているので、これによる外力がボンディング部
分に加わり易いため、接続強度に影響を受けるようにな
る。最悪の場合、これらが原因でボンディング部分が剥
離してしまう虞がある。However, in the prior art described in Japanese Patent Application Laid-Open No. 5-291322, a semiconductor chip is face-down bonded to a lead pattern having poor mechanical strength, and an external force is easily applied to the semiconductor chip. Due to the structure, there is a problem that connection reliability is low. That is, as is clear from FIGS. 19 and 20, the lead pattern 61d to which the semiconductor chip 63 is bonded is only supported by the insulating film 61s, so that a decrease in mechanical strength is inevitable. In the bonding portion, a sealing resin sheet 63 is provided.
Since a is in contact, an external force due to this is easily applied to the bonding portion, so that the connection strength is affected. In the worst case, there is a possibility that the bonding portion is peeled off due to these factors.

【０００９】また、微小サイズの半導体チップを用いる
半導体装置には適用困難である、という問題もある。す
なわち、特開平５−２９１３２２号公報に記載の従来技
術では封止用樹脂シート６３ａに凹部６３を形成する方
法として、光照射等の部分架橋手段を利用しているが、
このような方法は例えば上記公報に記載されているよう
な１０×１０mm程度の比較的大きなサイズの半導体チッ
プに適用する場合は問題がない。しかし、数mm程度例え
ば１×１mm程度、あるいはこれ以下の微小サイズの半導
体チップに適用しようとした場合には、上記の手段では
この半導体チップに対応した凹部の形成が精度的に厳し
くなるため、適用困難になる。There is another problem that it is difficult to apply to a semiconductor device using a semiconductor chip of a minute size. That is, in the prior art described in JP-A-5-291322, as a method of forming the concave portion 63 in the sealing resin sheet 63a, a partial cross-linking means such as light irradiation is used.
Such a method has no problem when applied to a semiconductor chip having a relatively large size of about 10.times.10 mm as described in the above publication. However, when it is intended to apply to a semiconductor chip of a small size of about several mm, for example, about 1 × 1 mm or less, since the formation of the concave portion corresponding to the semiconductor chip becomes strict with the above means, It becomes difficult to apply.

【００１０】この発明は、上述の事情に鑑みてなされた
もので、接続信頼性を向上させ、さらに、微小サイズの
半導体チップへの適用を可能にする半導体装置及びその
製造方法を提供することを目的としている。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a semiconductor device and a method of manufacturing the same, which can improve connection reliability and can be applied to a small-sized semiconductor chip. The purpose is.

【００１１】[0011]

【課題を解決するための手段】上記課題を解決するため
に、請求項１記載の発明は、中空状のパッケージを有す
る半導体装置に係り、配線パターンが形成された絶縁基
板の一主面上に半導体チップが接続され、該半導体チッ
プを封止するように絶縁性の中空状のパッケージが、上
記半導体チップの接続位置から離れた位置の上記絶縁基
板の一主面上に固着されていることを特徴としている。According to a first aspect of the present invention, there is provided a semiconductor device having a hollow package, wherein the semiconductor device has a hollow package on one main surface of an insulating substrate on which a wiring pattern is formed. A semiconductor chip is connected, and an insulating hollow package is sealed on one main surface of the insulating substrate at a position away from a connection position of the semiconductor chip so as to seal the semiconductor chip. Features.

【００１２】また、請求項２記載の発明は、中空状のパ
ッケージを有する半導体装置に係り、一主面が凹凸状に
形成された絶縁基板の上記凹部上に配線パターンが形成
され、かつ、凹部上に半導体チップが接続され、該半導
体チップを封止するように絶縁性のシートが上記絶縁基
板の凸部上に固着され、その絶縁基板の凸部と上記シー
トとにより中空状のパッケージが構成されていることを
特徴としている。According to a second aspect of the present invention, there is provided a semiconductor device having a hollow package, wherein a wiring pattern is formed on the concave portion of an insulating substrate having one main surface formed in an uneven shape, and A semiconductor chip is connected thereto, and an insulating sheet is fixed on the protrusion of the insulating substrate so as to seal the semiconductor chip, and a hollow package is formed by the protrusion of the insulating substrate and the sheet. It is characterized by being.

【００１３】また、請求項３記載の発明は、請求項１又
は２記載の半導体装置に係り、上記半導体チップの電極
パッドと、上記絶縁基板の配線パターンとがボール状導
体を通じて接続されていることを特徴としている。According to a third aspect of the present invention, there is provided the semiconductor device according to the first or second aspect, wherein the electrode pads of the semiconductor chip and the wiring pattern of the insulating substrate are connected through a ball-shaped conductor. It is characterized by.

【００１４】また、請求項４記載の発明は、請求項１又
は２記載の半導体装置に係り、上記半導体チップの電極
パッドと、上記絶縁基板の配線パターンとがボンディン
グワイヤを通じて接続されていることを特徴としてい
る。According to a fourth aspect of the present invention, there is provided the semiconductor device according to the first or second aspect, wherein the electrode pad of the semiconductor chip is connected to the wiring pattern of the insulating substrate through a bonding wire. Features.

【００１５】また、請求項５記載の発明は、請求項１乃
至４のいずれか１に記載の半導体装置に係り、上記絶縁
基板の配線パターンが、上記パッケージの外部まで延長
して形成されていることを特徴としている。According to a fifth aspect of the present invention, there is provided the semiconductor device according to any one of the first to fourth aspects, wherein the wiring pattern of the insulating substrate is formed to extend to the outside of the package. It is characterized by:

【００１６】また、請求項６記載の発明は、請求項１乃
至４のいずれか１に記載の半導体装置に係り、上記絶縁
基板の配線パターンが、上記絶縁基板の他主面に形成さ
れた配線パターンに、上記絶縁基板に形成されたスルー
ホール配線を通じて接続されていることを特徴としてい
る。According to a sixth aspect of the present invention, there is provided the semiconductor device according to any one of the first to fourth aspects, wherein the wiring pattern of the insulating substrate is formed on the other main surface of the insulating substrate. It is characterized by being connected to the pattern through a through-hole wiring formed on the insulating substrate.

【００１７】また、請求項７記載の発明は、請求項６記
載の半導体装置に係り、上記絶縁基板の他主面の配線パ
ターンに、ボール状の外部端子が接続されていることを
特徴としている。According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, a ball-shaped external terminal is connected to a wiring pattern on the other main surface of the insulating substrate. .

【００１８】また、請求項８記載の発明は、請求項６記
載の半導体装置に係り、上記絶縁基板の他主面の配線パ
ターンに、ピン状の外部端子が接続されていることを特
徴としている。According to an eighth aspect of the present invention, in the semiconductor device according to the sixth aspect, a pin-shaped external terminal is connected to a wiring pattern on the other main surface of the insulating substrate. .

【００１９】また、請求項９記載の発明は、請求項１乃
至８のいずれか１に記載の半導体装置に係り、上記絶縁
基板の一主面上の上記パッケージが固着される位置に、
あるいは上記シートが固着される位置に、上記パッケー
ジあるいは上記シートが密着性良く固着されるための特
殊加工が施されていることを特徴としている。According to a ninth aspect of the present invention, there is provided the semiconductor device according to any one of the first to eighth aspects, wherein the package is fixed on one main surface of the insulating substrate at a position where the package is fixed.
Alternatively, the package or the sheet is specially processed at a position where the sheet is fixed so that the sheet or the sheet is fixed with good adhesion.

【００２０】また、請求項１０記載の発明は、請求項１
記載の半導体装置を製造する方法に係り、シート状の絶
縁基板に複数の中空部を形成するパッケージ基板形成工
程と、一主面上に半導体チップの電極パッドに対応した
配線パターンを形成する絶縁基板形成工程と、上記絶縁
基板の一主面上に上記半導体チップを接続した後、上記
中空部が対応する半導体チップを封止するように、上記
絶縁基板の一主面上に上記パッケージ基板を固着するパ
ッケージ基板固着工程と、上記パッケージ基板及び上記
絶縁基板を、個々の半導体チップごとに分離する基板分
離工程とを含むことを特徴としている。The invention according to claim 10 is the first invention.
A package substrate forming step of forming a plurality of hollow portions in a sheet-shaped insulating substrate, and an insulating substrate forming a wiring pattern corresponding to an electrode pad of a semiconductor chip on one main surface according to the method for manufacturing a semiconductor device according to the present invention. After forming the semiconductor chip on one main surface of the insulating substrate and connecting the semiconductor chip on one main surface of the insulating substrate, the package substrate is fixed on one main surface of the insulating substrate so that the hollow portion seals the corresponding semiconductor chip. And a substrate separating step of separating the package substrate and the insulating substrate into individual semiconductor chips.

【００２１】また、請求項１１記載の発明は、請求項２
記載の半導体装置を製造する方法に係り、一主面が凹凸
状に形成され、その凹部上に半導体チップの電極パッド
に対応した配線パターンを形成する絶縁基板形成工程
と、上記絶縁基板の一主面の凹部上に上記半導体チップ
を接続した後、上記半導体チップを封止するように、上
記絶縁基板の一主面の凸部上に絶縁性のシートからなる
パッケージ基板を固着するパッケージ基板固着工程と、
上記パッケージ基板及び上記絶縁基板を、個々の半導体
チップごとに分離する基板分離工程とを含むことを特徴
としている。The invention according to claim 11 is the same as the claim 2.
An insulating substrate forming step of forming a wiring pattern corresponding to an electrode pad of a semiconductor chip on one concave surface of the insulating substrate; A package substrate fixing step of connecting the semiconductor chip to a concave portion of a surface and then fixing a package substrate made of an insulating sheet on a convex portion of one main surface of the insulating substrate so as to seal the semiconductor chip; When,
A substrate separating step of separating the package substrate and the insulating substrate into individual semiconductor chips.

【００２２】また、請求項１２記載の発明は、請求項１
０又は１１記載の半導体装置を製造する方法に係り、上
記絶縁基板形成工程において、上記絶縁基板の一主面上
の上記パッケージ基板が固着される位置に、そのパッケ
ージ基板を密着性良く固着するための特殊加工を施すこ
とを特徴としている。The invention according to claim 12 is the first invention.
12. The method for manufacturing a semiconductor device according to item 0 or 11, wherein in the insulating substrate forming step, the package substrate is fixed with good adhesion to a position on one main surface of the insulating substrate where the package substrate is fixed. It is characterized by applying special processing.

【００２３】[0023]

【発明の実施の形態】以下、図面を参照して、この発明
の実施の形態について説明する。説明は、実施例を用い
て具体的に行う。 ◇第１実施例 図１は、この発明の第１実施例である半導体装置の構成
を示す図で、同図（ａ）は同半導体装置の平面図、同図
（ｂ）は同図（ａ）のＡ−Ａ矢視断面図、図２は、同半
導体装置の製造方法を工程順に示す工程図、また、図３
乃至図５は、図２の同半導体装置の製造方法の一部の工
程の置き換えを示す工程図である。この例の半導体装置
は、同図に示すように、プラスチック基板、セラミック
基板等の絶縁基板１の一主面上に配線パターン２が形成
され、その一主面上に半導体チップ３がフェースダウン
ボンディングされて構成されている。一例として、半導
体チップ３は、略１×１ｍｍの微小サイズを有してい
る。半導体チップ３は、具体的には、その電極パッド４
がはんだ、金等のボール状導体５を通じて配線パターン
２に接続されている。Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. First Embodiment FIG. 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view of the semiconductor device, and FIG. 2) is a cross-sectional view taken along the line AA of FIG. 2, FIG. 2 is a process diagram showing a method of manufacturing the same semiconductor device in the order of processes, and FIG.
5 are process diagrams showing replacement of some steps of the method for manufacturing the same semiconductor device of FIG. In the semiconductor device of this example, as shown in the figure, a wiring pattern 2 is formed on one main surface of an insulating substrate 1 such as a plastic substrate or a ceramic substrate, and a semiconductor chip 3 is face-down bonded on one main surface. It is configured. As an example, the semiconductor chip 3 has a minute size of about 1 × 1 mm. Specifically, the semiconductor chip 3 has its electrode pads 4
Are connected to the wiring pattern 2 through a ball-shaped conductor 5 such as solder or gold.

【００２４】絶縁基板１の一主面上には、半導体チップ
３を封止するように、ポリイミド樹脂、エポキシ樹脂等
の熱硬化性樹脂等からなる、例えば平面形状が方形の中
空状のパッケージ６が、半導体チップ３の接続位置から
略５０μｍ離れた位置に固着されている。パッケージ６
を固着する手段としては、熱圧着法を挙げることができ
る。On one main surface of the insulating substrate 1, a hollow package 6 made of a thermosetting resin such as a polyimide resin or an epoxy resin, for example, having a square planar shape is provided so as to seal the semiconductor chip 3. Is fixed at a position approximately 50 μm away from the connection position of the semiconductor chip 3. Package 6
The thermocompression bonding method can be used as a means for fixing the adhesive.

【００２５】絶縁基板１の一主面上の上記パッケージ６
が固着される位置には、パッケージ６が密着性良く固着
されるための疎面部７が形成されている。疎面部７を形
成する手段としては、研磨剤による表面加工法を挙げる
ことができる。また、絶縁基板１の一主面上の配線パタ
ーン２は、パッケージ６の外部まで延長するように形成
されていて、外部端子として使用されるようになってい
る。The package 6 on one main surface of the insulating substrate 1
A sparse surface portion 7 for fixing the package 6 with good adhesiveness is formed at a position where is fixed. As a means for forming the rough surface portion 7, a surface processing method using an abrasive can be cited. The wiring pattern 2 on one main surface of the insulating substrate 1 is formed so as to extend to the outside of the package 6, and is used as an external terminal.

【００２６】次に、図２を参照して、この例の半導体装
置の製造方法について工程順に説明する。まず、同図
（ａ）に示すように、例えばエポキシ樹脂の一種である
クレゾールノボラックタイプの熱硬化性樹脂からなる、
略０．５mmの厚さの樹脂シートを用いて、上型８と下型
９との間にセットする。次に、略１７５℃に加熱しなが
ら、矢印方向に真空吸引して平面形状が方形の複数の中
空部６ａを形成することにより、パッケージ基板６ｂを
形成する。このような真空吸引成形法によれば、中空部
６ａを高精度で形成するのが容易なので、微小サイズの
半導体チップに適用できる中空状のパッケージの形成が
可能となる。Next, a method of manufacturing the semiconductor device of this embodiment will be described in the order of steps with reference to FIG. First, as shown in FIG. 1A, for example, a cresol novolak type thermosetting resin, which is a type of epoxy resin, is used.
It is set between the upper mold 8 and the lower mold 9 using a resin sheet having a thickness of about 0.5 mm. Next, while heating to approximately 175 ° C., vacuum suction is performed in the direction of the arrow to form a plurality of hollow portions 6 a having a square planar shape, thereby forming the package substrate 6 b. According to such a vacuum suction molding method, it is easy to form the hollow portion 6a with high precision, so that it is possible to form a hollow package applicable to a small-sized semiconductor chip.

【００２７】あるいは、真空吸引成形法に代えて、図３
に示したような、プレス成形法によってパッケージ基板
６ｂを形成することもできる。同図において、上記の樹
脂シートは、予め下型９ａ上にセットされた状態で、上
型８ａによりプレスされることにより、複数の中空部６
ｃを有するパッケージ基板６ｄが形成される。このプレ
ス成形方法によっても、中空部６ｃを高精度で形成する
ことができる。Alternatively, instead of the vacuum suction molding method, FIG.
The package substrate 6b can be formed by a press molding method as shown in FIG. In the figure, the resin sheet is pressed by an upper mold 8a in a state where it is set on a lower mold 9a in advance, so that a plurality of hollow portions 6 are formed.
Thus, a package substrate 6d having c is formed. The hollow portion 6c can be formed with high accuracy also by this press molding method.

【００２８】次に、同図（ｂ）に示すように、プラスチ
ック基板、セラミック基板等からなる略０．１〜０．２
mmの厚さの絶縁基板１の一主面上に、スクリーン印刷法
等により配線パターン２を形成する。次に、絶縁基板１
の一主面上の配線パターン２を含む領域を、樹脂等のマ
スク１０で覆った状態で、パッケージ基板６ｂが固着さ
れる位置に、そのパッケージ基板６ｂを密着性良く固着
するための疎面部７を形成する。疎面部７は、特殊加工
を施して形成し、例えばノズル１１から、アルミナ（♯
３２０、最大粒径９８μｍ、平均粒径４０μｍ、最小粒
径２７μｍ）と水との混合液（体積濃度１７±１％）か
らなる研磨剤１２を、マスク１０で覆われていない絶縁
基板１の一主面に噴射して形成する。これにより、表面
粗さＲmax３〜４μｍの疎面部７が形成される。Next, as shown in FIG. 2B, approximately 0.1 to 0.2 made of a plastic substrate, a ceramic substrate or the like.
A wiring pattern 2 is formed on one main surface of the insulating substrate 1 having a thickness of mm by a screen printing method or the like. Next, the insulating substrate 1
In a state where the region including the wiring pattern 2 on one main surface is covered with a mask 10 such as a resin, a sparse surface portion 7 for fixing the package substrate 6b with good adhesion to a position where the package substrate 6b is fixed. To form The rough surface portion 7 is formed by performing a special processing, and for example, an alumina (♯)
320, a polishing agent 12 composed of a mixture of water (volume concentration: 17 ± 1%) with water (maximum particle size: 98 μm, average particle size: 40 μm, minimum particle size: 27 μm). It is formed by spraying on the main surface. As a result, a rough surface portion 7 having a surface roughness Rmax of 3 to 4 μm is formed.

【００２９】あるいは、パッケージ基板６ｂを密着性良
く固着するためには、疎面部７に代えて、接着剤を利用
することもできる。この場合、１つの方法として、図４
に示すように、絶縁基板１の一主面の固着位置にニード
ル１３から部分的に接着剤１４を塗布するようにする。
他の方法として、図５に示すように、まず、同図（ａ）
に示すように、絶縁基板１の一主面の固着位置以外を樹
脂等のマスク１０ａで覆った後、同図（ｂ）に示すよう
に、スクリーン印刷法等で固定位置に接着剤１４ａを塗
布するようにする。いずれの方法による接着剤１４、１
４ａによっても、上記の疎面部７と同様の役割を担わせ
ることができる。Alternatively, in order to fix the package substrate 6b with good adhesion, an adhesive can be used instead of the sparse surface portion 7. In this case, as one method, FIG.
As shown in (1), an adhesive 14 is partially applied from the needle 13 to the fixing position of one main surface of the insulating substrate 1.
As another method, first, as shown in FIG.
As shown in (b), after covering a portion other than the fixing position of one main surface of the insulating substrate 1 with a mask 10a of resin or the like, an adhesive 14a is applied to the fixing position by a screen printing method or the like as shown in FIG. To do it. Adhesive 14, 1 by any method
4a can also serve the same role as the above-described sparse surface portion 7.

【００３０】次に、同図（ｃ）に示すように、絶縁基板
１の一主面上に、略０．３５×０．３５×０．１６mmの
微小サイズの半導体チップ３をフェースダウンボンディ
ングする。このフェースダウンボンディングは、半導体
チップ３の電極パッド４をはんだ、金等のボール状導体
５を通じて配線パターン２に接続する。Next, as shown in FIG. 1C, a minute semiconductor chip 3 of approximately 0.35 × 0.35 × 0.16 mm is face-down bonded on one main surface of the insulating substrate 1. . In this face-down bonding, the electrode pads 4 of the semiconductor chip 3 are connected to the wiring patterns 2 through ball-shaped conductors 5 such as solder and gold.

【００３１】次に、同図（ｄ）に示すように、パッケー
ジ基板６ｂを中空部６ａが半導体チップ３を封止するよ
うに、その基部６ｅを絶縁基板１の疎面部７に熱圧着法
により固着する。この熱圧着法は、温度略１７５℃、圧
力７０〜１２０g／ｃｍ2、硬化時間１５〜２５秒の条件
で行う。このパッケージ基板６ｄの固着は、その固着位
置が半導体チップ３の接続位置から略５０μｍ離れた位
置に固着させるようにする。Next, as shown in FIG. 3D, the base 6e of the package substrate 6b is bonded to the sparse surface 7 of the insulating substrate 1 by a thermocompression bonding method so that the hollow portion 6a seals the semiconductor chip 3. Stick. This thermocompression bonding method is performed at a temperature of about 175 ° C., a pressure of 70 to 120 g / cm 2 , and a curing time of 15 to 25 seconds. The package substrate 6d is fixed at a position approximately 50 μm away from the connection position of the semiconductor chip 3.

【００３２】次に、同図（ｅ）に示すように、パッケー
ジ基板６ｂ及び絶縁基板１を、ダイシングブレードを用
いて個々の半導体チップ３ごとに切断分離することによ
り、図１に示したような半導体装置が製造される。Next, as shown in FIG. 1E, the package substrate 6b and the insulating substrate 1 are cut and separated into individual semiconductor chips 3 using a dicing blade, thereby obtaining the structure shown in FIG. A semiconductor device is manufactured.

【００３３】このように、この実施例の構成によれば、
半導体チップ３が機械的強度に優れた絶縁基板１の一主
面上に接続され、また、中空状のパッケージ６が半導体
チップ３を封止するように、半導体チップ３の接続位置
から離れた位置の絶縁基板１の一主面上に固着されてい
るので、パッケージ６による外力が半導体チップ３に加
わらないため、半導体装置の接続信頼性を向上させるこ
とができる。また、パッケージ６の中空部６ａを高精度
で形成することができるので、微小サイズの半導体チッ
プ３への適用が可能となる。さらに、絶縁基板１の一主
面上の中空状のパッケージ６を固着する位置には、疎面
部７が形成されているので、パッケージ６を密着性良く
固着することができる。また、中空状のパッケージ６
は、絶縁基板１の一主面上のみに設けられているので、
パッケージ６の材料費が少なくなるので、生産性を向上
させることができる。As described above, according to the configuration of this embodiment,
The semiconductor chip 3 is connected to one main surface of the insulating substrate 1 having excellent mechanical strength, and a position away from the connection position of the semiconductor chip 3 so that the hollow package 6 seals the semiconductor chip 3. Is fixed on one main surface of the insulating substrate 1, no external force from the package 6 is applied to the semiconductor chip 3, so that the connection reliability of the semiconductor device can be improved. In addition, since the hollow portion 6a of the package 6 can be formed with high precision, it can be applied to the semiconductor chip 3 having a very small size. Furthermore, since the sparse surface portion 7 is formed at a position on one main surface of the insulating substrate 1 where the hollow package 6 is fixed, the package 6 can be fixed with good adhesion. In addition, the hollow package 6
Is provided only on one main surface of the insulating substrate 1,
Since the material cost of the package 6 is reduced, productivity can be improved.

【００３４】◇第２実施例 図６は、この発明の第２実施例である半導体装置の構成
を概略示す断面図である。この第２実施例の半導体装置
の構成が、上述の第１実施例のそれと大きく異なるとこ
ろは、半導体チップ３が絶縁基板１の一主面上にフェー
スアップボンディングされている点である。すなわち、
半導体チップ３は接着剤によって絶縁基板１の一主面上
に接続され、その電極パッド４は金線、アルミニウム線
等のボンディングワイヤ１５を通じて、絶縁基板１の配
線パターン２に接続されている。なお、上記以外の点で
は、上述の第１実施例と略同様であるので、図６におい
て、図１の構成部分と同一の各部には、同一の符号を付
してその説明を省略する。Second Embodiment FIG. 6 is a sectional view schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention. The configuration of the semiconductor device of the second embodiment is significantly different from that of the first embodiment in that the semiconductor chip 3 is face-up bonded on one main surface of the insulating substrate 1. That is,
The semiconductor chip 3 is connected to one main surface of the insulating substrate 1 by an adhesive, and the electrode pads 4 are connected to the wiring pattern 2 of the insulating substrate 1 through bonding wires 15 such as gold wires and aluminum wires. Except for the points described above, the configuration is substantially the same as that of the first embodiment described above. Therefore, in FIG. 6, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

【００３５】このように、この例の構成によっても、第
１実施例において述べたと略同様の効果を得ることがで
きる。加えて、上述の第１実施例の場合に比べて、ボン
ディングワイヤ１５が半導体チップ３の周囲に配置され
ているので、ボンディングワイヤ１５がパッケージ６に
触れて外力を受ける可能性がより大きくなるが、パッケ
ージ６の中空部６ａを高精度で形成できるため、そのよ
うな可能性を解消することができる。As described above, according to the structure of this embodiment, substantially the same effects as described in the first embodiment can be obtained. In addition, since the bonding wire 15 is arranged around the semiconductor chip 3 as compared with the case of the above-described first embodiment, the possibility that the bonding wire 15 touches the package 6 and receives an external force is increased. Since the hollow portion 6a of the package 6 can be formed with high precision, such a possibility can be eliminated.

【００３６】◇第３実施例 図７は、この発明の第３実施例である半導体装置の構成
を概略示す断面図である。この第３実施例の半導体装置
の構成が、上述の第１実施例のそれと大きく異なるとこ
ろは、絶縁基板１の一主面上の配線パターン２がパッケ
ージ４の外部に延長されておらずに、絶縁基板１の他主
面上に形成された配線パターン２ａに接続されている点
である。すなわち、絶縁基板１の一主面上の配線パター
ン２は、絶縁基板１に形成されたスルーホール配線１６
を通じて、他主面上の配線パターン２ａに接続されてい
る。そして、その配線パターン２ａには外部端子として
働く、はんだ、金等のボール状外部端子１７に接続され
ている。いわゆる、ＢＧＡ（Ball Grid Array）端子構
造になっている。Third Embodiment FIG. 7 is a sectional view schematically showing a configuration of a semiconductor device according to a third embodiment of the present invention. The configuration of the semiconductor device according to the third embodiment is significantly different from that of the first embodiment in that the wiring pattern 2 on one main surface of the insulating substrate 1 is not extended outside the package 4. The point is that it is connected to the wiring pattern 2a formed on the other main surface of the insulating substrate 1. That is, the wiring pattern 2 on one main surface of the insulating substrate 1 is formed by the through-hole wiring 16 formed on the insulating substrate 1.
Through the wiring pattern 2a on the other main surface. The wiring pattern 2a is connected to a ball-shaped external terminal 17 made of solder, gold, or the like, serving as an external terminal. It has a so-called BGA (Ball Grid Array) terminal structure.

【００３７】このように、この例の構成によっても、第
１実施例において述べたと略同様の効果を得ることがで
きる。加えて、上述の第１実施例の場合に比べて、外部
端子として働くボール状の外部端子１７がパッケージ６
の外部でなく、絶縁基板１の他主面上に配置されている
ので、部品としてプリント基板に実装する場合に、実装
面積が節約することができる。As described above, according to the structure of this embodiment, substantially the same effects as described in the first embodiment can be obtained. In addition, a ball-shaped external terminal 17 acting as an external terminal is provided in
Since it is arranged not on the outside but on the other main surface of the insulating substrate 1, when it is mounted on a printed circuit board as a component, the mounting area can be saved.

【００３８】◇第４実施例 図８は、この発明の第４実施例である半導体装置の構成
を概略示す断面図である。この第４実施例の構成が、上
述の第３実施例のそれと大きく異なるところは、絶縁基
板１の他主面上の配線パターン２ａに、ピン状の外部端
子１８を接続するよいにした点である。いわゆる、ＰＧ
Ａ（Pinl Grid Array）端子構造になっている。このよ
うに、この例の構成によっても、第３実施例において述
べたと略同様の効果を得ることができる。Fourth Embodiment FIG. 8 is a sectional view schematically showing a configuration of a semiconductor device according to a fourth embodiment of the present invention. The configuration of the fourth embodiment differs greatly from that of the third embodiment in that a pin-shaped external terminal 18 is preferably connected to the wiring pattern 2a on the other main surface of the insulating substrate 1. is there. So-called PG
A (Pinl Grid Array) terminal structure. As described above, according to the configuration of this example, substantially the same effects as those described in the third embodiment can be obtained.

【００３９】◇第５実施例 図９は、この発明の第５実施例である半導体装置の構成
を概略示す断面図である。この第５実施例の構成が、上
述の第３実施例のそれと大きく異なるところは、半導体
チップ３が絶縁基板１の一主面上にフェースアップボン
ディングされている点である。Fifth Embodiment FIG. 9 is a sectional view schematically showing a configuration of a semiconductor device according to a fifth embodiment of the present invention. The configuration of the fifth embodiment is significantly different from that of the third embodiment in that the semiconductor chip 3 is face-up bonded on one main surface of the insulating substrate 1.

【００４０】このように、この例の構成によっても、第
３実施例において述べたと略同様の効果を得ることがで
きる。加えて、上述の第３実施例の場合に比べて、ボン
ディングワイヤ１５が半導体チップ３の周囲に配置され
ているので、ボンディングワイヤ１５がパッケージ６に
触れて外力を受ける可能性がより大きくなるが、パッケ
ージ６の中空部６ａを高精度で形成できるため、そのよ
うな可能性を解消することができる。As described above, according to the structure of this embodiment, substantially the same effects as described in the third embodiment can be obtained. In addition, since the bonding wires 15 are arranged around the semiconductor chip 3 as compared with the case of the third embodiment described above, the possibility that the bonding wires 15 touch the package 6 and receive an external force is increased. Since the hollow portion 6a of the package 6 can be formed with high precision, such a possibility can be eliminated.

【００４１】◇第６実施例 図１０は、この発明の第６実施例である半導体装置の構
成を概略示す断面図である。この第６実施例の構成が、
上述の第４実施例のそれと大きく異なるところは、半導
体チップ３が絶縁基板１の一主面上にフェースアップボ
ンディングされている点である。Sixth Embodiment FIG. 10 is a sectional view schematically showing a configuration of a semiconductor device according to a sixth embodiment of the present invention. The configuration of the sixth embodiment is as follows.
The major difference from the fourth embodiment is that the semiconductor chip 3 is face-up bonded on one main surface of the insulating substrate 1.

【００４２】このように、この例の構成によっても、第
４実施例において述べたと略同様の効果を得ることがで
きる。加えて、上述の第４実施例の場合に比べて、ボン
ディングワイヤ１５が半導体チップ３の周囲に配置され
ているので、ボンディングワイヤ１５がパッケージ６に
触れて外力を受ける可能性がより大きくなるが、パッケ
ージ６の中空部６ａを高精度で形成できるため、そのよ
うな可能性を解消することができる。As described above, according to the structure of this embodiment, substantially the same effects as described in the fourth embodiment can be obtained. In addition, since the bonding wires 15 are arranged around the semiconductor chip 3 as compared with the case of the above-described fourth embodiment, the possibility that the bonding wires 15 touch the package 6 and receive an external force increases. Since the hollow portion 6a of the package 6 can be formed with high precision, such a possibility can be eliminated.

【００４３】◇第７実施例 図１１は、この発明の第７実施例である半導体装置の構
成を示す図で、同図（ａ）は同半導体装置の平面図、同
図（ｂ）は同図（ａ）のＡ−Ａ矢視断面図、また、図１
２は、同半導体装置の製造方法を工程順に示す工程図で
ある。この例の半導体装置は、同図に示すように、プラ
スチック基板、セラミック基板等の絶縁基板２１の一主
面が、凹部２１ａ及び凸部２１ｂを有する凹凸状に形成
されている。そして、絶縁基板２１の一主面の凹部２１
ａ上には配線パターン２２が形成され、その凹部２１ａ
上に半導体チップ２３がフェースダウンボンディングさ
れている。一例として、半導体チップ２３は、略１×１
ｍｍの微小サイズを有している。半導体チップ２３は、
具体的にはその電極パッド２４がはんだ、金等のボール
状導体２５を通じて配線パターン２２に接続されてい
る。Seventh Embodiment FIGS. 11A and 11B show the structure of a semiconductor device according to a seventh embodiment of the present invention. FIG. 11A is a plan view of the semiconductor device, and FIG. FIG. 1A is a sectional view taken along the line AA, and FIG.
FIG. 2 is a process chart showing a method for manufacturing the same semiconductor device in the order of steps. In the semiconductor device of this example, as shown in the figure, one main surface of an insulating substrate 21 such as a plastic substrate or a ceramic substrate is formed in an uneven shape having a concave portion 21a and a convex portion 21b. Then, the concave portion 21 on one main surface of the insulating substrate 21
a, a wiring pattern 22 is formed thereon,
A semiconductor chip 23 is face-down bonded thereon. As an example, the semiconductor chip 23 is approximately 1 × 1
mm. The semiconductor chip 23
Specifically, the electrode pad 24 is connected to the wiring pattern 22 through a ball-shaped conductor 25 such as solder or gold.

【００４４】絶縁基板２１の一主面の凸部２１ｂ上に
は、半導体チップ２３を封止するように、ポリイミド樹
脂、エポキシ樹脂等の熱硬化性樹脂等からなる例えば平
面形状が方形の樹脂シート２６が熱圧着法等で固着され
ている。そして、絶縁基板２１の凸部２１ｂとシート２
６とによって、中空状のパッケージ２７が構成されてい
る。絶縁基板２１の一主面の凹部２１ａ上の配線パター
ン２２は、パッケージ２７の外部まで延長するように形
成されていて、外部端子として使用されるようになって
いる。A resin sheet made of, for example, a thermosetting resin such as a polyimide resin or an epoxy resin and having a square shape is formed on the convex portion 21 b on one main surface of the insulating substrate 21 so as to seal the semiconductor chip 23. 26 is fixed by a thermocompression bonding method or the like. Then, the convex portion 21b of the insulating substrate 21 and the sheet 2
6 form a hollow package 27. The wiring pattern 22 on the concave portion 21a on one main surface of the insulating substrate 21 is formed so as to extend to the outside of the package 27, and is used as an external terminal.

【００４５】次に、図１２を参照して、この例の半導体
装置の製造方法について工程順に説明する。まず、同図
（ａ）に示すように、プラスチック基板、セラミック基
板等からなり、一主面が凹部２１ａ及び凸部２１ｂを有
する凹凸状に形成され、その凹部２１ａ上に配線パター
ン２２が形成された絶縁基板２１を用意する。凹部２１
ａは略０．１〜０．２mmの厚さに、凸部２１ｂは略０．
２〜０．３mmの厚さに形成される。そのような絶縁基板
２１の形成は、周知のセラミック基板形成技術を利用す
ることにより、容易に形成できるのでその詳細な説明は
省略する。また、セラミック基板形成技術によって凹部
２１ａを高精度で形成することができる。Next, a method of manufacturing the semiconductor device of this example will be described in the order of steps with reference to FIG. First, as shown in FIG. 1A, a main surface is formed in a concave and convex shape having a concave portion 21a and a convex portion 21b, and a wiring pattern 22 is formed on the concave portion 21a. The prepared insulating substrate 21 is prepared. Recess 21
a has a thickness of about 0.1 to 0.2 mm, and the projection 21b has a thickness of about 0.1 mm.
It is formed to a thickness of 2 to 0.3 mm. Such an insulating substrate 21 can be easily formed by using a well-known ceramic substrate forming technique, and thus a detailed description thereof is omitted. Further, the concave portion 21a can be formed with high precision by the ceramic substrate forming technique.

【００４６】次に、同図（ｂ）に示すように、絶縁基板
２１の一主面の凹部２１ａ上に、略０．３５×０．３５
×０．１６mmの微小サイズの半導体チップ２３をフェー
スダウンボンディングする。このフェースダウンボンデ
ィングは、半導体チップ２３の電極パッド２４をはん
だ、金等のボール状導体２５を通じて配線パターン２２
に接続する。Next, as shown in FIG. 3B, approximately 0.35 × 0.35
A semiconductor chip 23 of a minute size of 0.16 mm is face-down bonded. In this face-down bonding, an electrode pad 24 of a semiconductor chip 23 is connected to a wiring pattern 22 through a ball-shaped conductor 25 such as solder or gold.
Connect to

【００４７】次に、同図（ｃ）に示すように、例えばエ
ポキシ樹脂の一種であるクレゾールノボラックタイプの
熱硬化性樹脂からなる、略０．５mmの厚さの樹脂シート
２６を用いて、半導体チップ２３を封止するように、絶
縁基板２１の一主面の凸部２１ｂ上に熱圧着法等により
に固着する。これにより、絶縁基板２１の凹部２１ａと
樹脂シート２６とによって、中空状のパッケージ２７が
構成される。次に、同図（ｄ）に示すように、絶縁基板
２１及び樹脂シート２６を、ダイシングブレードを用い
て個々の半導体チップ２３ごとに分離することにより、
図１１に示したような半導体装置が製造される。Next, as shown in FIG. 3C, a semiconductor sheet 26 having a thickness of about 0.5 mm and made of, for example, a cresol novolac type thermosetting resin, which is a kind of epoxy resin, is used. The chip 23 is fixed on the convex portion 21b on one main surface of the insulating substrate 21 by a thermocompression bonding method or the like so as to seal the chip 23. Thus, the hollow package 27 is configured by the concave portion 21a of the insulating substrate 21 and the resin sheet 26. Next, as shown in FIG. 4D, the insulating substrate 21 and the resin sheet 26 are separated into individual semiconductor chips 23 using a dicing blade, whereby
The semiconductor device as shown in FIG. 11 is manufactured.

【００４８】このように、この第７実施例の構成によれ
ば、半導体チップ２４が機械的強度に優れた絶縁基板２
１の一主面の凹部２１ａ上に接続され、また、樹脂シー
ト２６を半導体チップ２３を封止するようにその凸部２
１ｂ上に固着して、凸部２１ｂと樹脂シート２６とによ
って、中空状のパッケージ２７を構成するようにしたの
で、中空状のパッケージ２７が、半導体チップ２３の接
続位置から離れた位置の絶縁基板２１の一主面上に形成
されているので、パッケージ２７による外力が半導体チ
ップ２３に加わらないため、半導体装置の接続信頼性を
向上させることができる。As described above, according to the structure of the seventh embodiment, the semiconductor chip 24 is made of the insulating substrate 2 having excellent mechanical strength.
1 is connected to the concave portion 21a on one principal surface, and the resin sheet 26 has its convex portion 2 so as to seal the semiconductor chip 23.
1b, the hollow package 27 is constituted by the projection 21b and the resin sheet 26. Therefore, the hollow package 27 is separated from the connection position of the semiconductor chip 23 by the insulating substrate. Since it is formed on one main surface of the semiconductor chip 21, the external force of the package 27 is not applied to the semiconductor chip 23, so that the connection reliability of the semiconductor device can be improved.

【００４９】また、パッケージ２７の中空部となる凹部
２１ａを高精度で形成することができるので、微小サイ
ズの半導体チップ２３への適用が可能となる。また、中
空状のパッケージ２７は絶縁基板２１の一主面上のみに
設けられているので、パッケージ２７の材料費が少なく
なるので、生産性を向上させることができる。Further, since the concave portion 21a serving as the hollow portion of the package 27 can be formed with high precision, it can be applied to the semiconductor chip 23 of a minute size. Further, since the hollow package 27 is provided only on one main surface of the insulating substrate 21, the material cost of the package 27 is reduced, so that productivity can be improved.

【００５０】◇第８実施例 図１３は、この発明の第８実施例である半導体装置の構
成を概略示す断面図である。この第８実施例の半導体装
置の構成が、上述の第７実施例のそれと大きく異なると
ころは、半導体チップ２３が絶縁基板２１の一主面の凹
部２１ａ上にフェースアップボンディングされている点
である。すなわち、半導体チップ２３は接着剤によって
絶縁基板２１の一主面の凹部２１ａ上に接続され、その
電極パッド２４は金線、アルミニウム線等のボンディン
グワイヤ２８を通じて、絶縁基板２１の配線パターン２
２に接続されている。Eighth Embodiment FIG. 13 is a sectional view schematically showing a configuration of a semiconductor device according to an eighth embodiment of the present invention. The configuration of the semiconductor device of the eighth embodiment is significantly different from that of the above-described seventh embodiment in that the semiconductor chip 23 is face-up bonded onto the concave portion 21a on one main surface of the insulating substrate 21. . That is, the semiconductor chip 23 is connected to the concave portion 21a on one main surface of the insulating substrate 21 by an adhesive, and its electrode pad 24 is connected to the wiring pattern 2 of the insulating substrate 21 through a bonding wire 28 such as a gold wire or an aluminum wire.
2 are connected.

【００５１】このように、この例の構成によっても、第
７実施例において述べたと略同様の効果を得ることがで
きる。加えて、上述の第７実施例の場合に比べて、ボン
ディングワイヤ２８が半導体チップ２３の周囲に配置さ
れているので、ボンディングワイヤ２８がパッケージ２
７に触れて外力を受ける可能性がより大きくなるが、パ
ッケージ２７の中空部となる凹部２１ａを高精度で形成
できるため、そのような可能性を解消することができ
る。As described above, according to the structure of this embodiment, substantially the same effects as described in the seventh embodiment can be obtained. In addition, since the bonding wires 28 are arranged around the semiconductor chip 23 as compared with the case of the above-described seventh embodiment, the bonding wires 28
Although the possibility of receiving an external force by touching the touch panel 7 becomes larger, such a possibility can be eliminated because the concave portion 21a serving as the hollow portion of the package 27 can be formed with high precision.

【００５２】◇第９実施例 図１４は、この発明の第９実施例である半導体装置の構
成を概略示す断面図である。この第９実施例の半導体装
置の構成が、上述の第７実施例のそれと大きく異なると
ころは、絶縁基板２１の一主面の凹部２１ａ上の配線パ
ターン２２がパッケージ２７の外部に延長されておらず
に、絶縁基板２１の他主面上に形成された配線パターン
２２ａに接続されている点である。すなわち、絶縁基板
２１の一主面の凹部２１ａ上の配線パターン２２は、絶
縁基板２１の凹部２１ａに形成されたスルーホール配線
２９を通じて、他主面上の配線パターン２２ａに接続さ
れている。そして、その配線パターン２２ａには外部端
子として働く、はんだ、金等のボール状の外部端子３０
に接続されている。いわゆる、ＢＧＡ端子構造になって
いる。Ninth Embodiment FIG. 14 is a sectional view schematically showing a configuration of a semiconductor device according to a ninth embodiment of the present invention. The configuration of the semiconductor device of the ninth embodiment is significantly different from that of the seventh embodiment in that the wiring pattern 22 on the concave portion 21a on one main surface of the insulating substrate 21 is extended outside the package 27. Instead, it is connected to the wiring pattern 22a formed on the other main surface of the insulating substrate 21. That is, the wiring pattern 22 on the concave portion 21a on one main surface of the insulating substrate 21 is connected to the wiring pattern 22a on the other main surface through the through-hole wiring 29 formed in the concave portion 21a of the insulating substrate 21. The wiring pattern 22a has a ball-shaped external terminal 30 made of solder, gold, or the like, serving as an external terminal.
It is connected to the. It has a so-called BGA terminal structure.

【００５３】このように、この例の構成によっても、第
７実施例において述べたと略同様の効果を得ることがで
きる。加えて、上述の第７実施例の場合に比べて、外部
端子として働くボール状の外部端子３０がパッケージ２
７の外部でなく、絶縁基板２１の他主面上に配置されて
いるので、部品としてプリント基板に実装する場合に、
実装面積が節約することができる。As described above, according to the structure of this embodiment, substantially the same effects as described in the seventh embodiment can be obtained. In addition, as compared with the case of the above-described seventh embodiment, a ball-shaped external terminal 30 serving as an external terminal is provided in the package 2.
7 is arranged on the other main surface of the insulating substrate 21 and not on the outside of the insulating substrate 21.
The mounting area can be saved.

【００５４】◇第１０実施例 図１５は、この発明の第１０実施例である半導体装置の
構成を概略示す断面図である。この第１０実施例の半導
体装置の構成が、上述の第９実施例のそれと大きく異な
るところは、絶縁基板２１の他主面上の配線パターン２
２ａに、ピン状の外部端子３１を接続するようにした点
である。いわゆる、ＰＧＡ端子構造になっている。この
ように、この例の構成によっても、第９実施例において
述べたと略同様の効果を得ることができる。FIG. 15 is a sectional view schematically showing a configuration of a semiconductor device according to a tenth embodiment of the present invention. The configuration of the semiconductor device of the tenth embodiment differs greatly from that of the ninth embodiment in that the wiring pattern 2 on the other main surface of the insulating substrate 21 is different.
The point is that a pin-shaped external terminal 31 is connected to 2a. It has a so-called PGA terminal structure. As described above, according to the configuration of this example, substantially the same effects as described in the ninth embodiment can be obtained.

【００５５】◇第１１実施例 図１６は、この発明の第１１実施例である半導体装置の
構成を概略示す断面図である。この第１１実施例の半導
体装置の構成が、上述の第９実施例のそれと大きく異な
るところは、半導体チップ２３が絶縁基板２１の一主面
の凹部２１ａ上にフェースアップボンディングされてい
る点である。このように、この例の構成によっても、第
９実施例において述べたと略同様の効果を得ることがで
きる。Eleventh Embodiment FIG. 16 is a sectional view schematically showing a configuration of a semiconductor device according to an eleventh embodiment of the present invention. The configuration of the semiconductor device of the eleventh embodiment is significantly different from that of the above-described ninth embodiment in that the semiconductor chip 23 is face-up bonded onto the recess 21a on one main surface of the insulating substrate 21. . As described above, according to the configuration of this example, substantially the same effects as described in the ninth embodiment can be obtained.

【００５６】◇第１２実施例 図１７は、この発明の第１２実施例である半導体装置の
構成を概略示す断面図である。この第１２実施例の半導
体装置の構成が、上述の第１１実施例のそれと大きく異
なるところは、絶縁基板２１の他主面上の配線パターン
２２ａに、ピン状の外部端子３２を接続するようにした
点である。いわゆる、ＰＧＡ端子構造になっている。こ
のように、この例の構成によっても、第１１実施例にお
いて述べたと略同様の効果を得ることができる。Twelfth Embodiment FIG. 17 is a sectional view schematically showing a configuration of a semiconductor device according to a twelfth embodiment of the present invention. The configuration of the semiconductor device of the twelfth embodiment is significantly different from that of the above-described eleventh embodiment in that a pin-shaped external terminal 32 is connected to the wiring pattern 22a on the other main surface of the insulating substrate 21. That is the point. It has a so-called PGA terminal structure. As described above, even with the configuration of this example, substantially the same effects as those described in the eleventh embodiment can be obtained.

【００５７】以上、この発明の実施例を図面により詳述
してきたが、具体的な構成はこの実施例に限られるもの
ではなく、この発明の要旨を逸脱しない範囲の設計の変
更などがあってもこの発明に含まれる。例えば、配線基
板１、２１に形成する配線パターン２、２ａ、２２、２
２ａの数や、ボール状の外部端子、ピン状の外部端子の
数等は、任意に増減できる。また、中空状のパッケージ
６、２７の平面形状は、方形に限らずに、円形、多角形
等に変更することができる。Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there are changes in the design without departing from the gist of the present invention. Is also included in the present invention. For example, wiring patterns 2, 2a, 22, 2 formed on the wiring substrates 1, 21
The number of 2a, the number of ball-shaped external terminals, the number of pin-shaped external terminals, and the like can be arbitrarily increased or decreased. Further, the planar shape of the hollow packages 6 and 27 is not limited to a square, but can be changed to a circle, a polygon, or the like.

【００５８】また、パッケージ基板６ｂ、６ｄ、樹脂シ
ート２６等を絶縁基板１、２１の一主面上に固着する手
段としては、熱圧着法に限らずに、超音波併用熱圧着法
を利用することができる。また、絶縁基板１のパッケー
ジ６の固着位置に、接着剤１４、１４ａを塗布した場合
には、光照射を利用して接着剤１４、１４ａを硬化処理
してパッケージ６を固着することもできる。The means for fixing the package substrates 6b and 6d, the resin sheet 26, and the like on one main surface of the insulating substrates 1 and 21 is not limited to the thermocompression bonding method, but also uses an ultrasonic combined thermocompression bonding method. be able to. When the adhesives 14 and 14a are applied to the position where the package 6 is fixed on the insulating substrate 1, the package 6 can be fixed by curing the adhesives 14 and 14a using light irradiation.

【００５９】また、絶縁基板１にパッケージ６を密着す
るための特殊加工処理は、一主面が凹凸状の絶縁基板２
１の凸部２１ｂに対して適用することもできる。また、
半導体チップ３、２３のサイズ、絶縁基板１、２１の厚
さ、パッケージ基板６ｂ、６ｄ、樹脂シート２６の厚さ
等の値、特殊加工処理の条件、熱圧着法の条件などは、
必要に応じて変更することが可能である。In the special processing for bringing the package 6 into close contact with the insulating substrate 1, the insulating substrate 2 whose one main surface has an uneven shape is used.
The present invention can be applied to one convex portion 21b. Also,
The values of the sizes of the semiconductor chips 3 and 23, the thickness of the insulating substrates 1 and 21, the thicknesses of the package substrates 6b and 6d, and the thickness of the resin sheet 26, the conditions of the special processing, and the conditions of the thermocompression bonding method are as follows.
It can be changed as needed.

【００６０】[0060]

【発明の効果】以上説明したように、この発明の構成に
よれば、半導体チップが機械的強度に優れた絶縁基板の
一主面上に接続され、また、中空状のパッケージが半導
体チップを封止するように、半導体チップの接続位置か
ら離れた位置の絶縁基板の一主面上に固着されているの
で、パッケージによる外力が半導体チップに加わらない
ため、半導体装置の接続信頼性を向上させることができ
る。また、パッケージの中空部を高精度で形成すること
ができるので、微小サイズの半導体チップへの適用が可
能となる。また、絶縁基板の一主面上の中空状のパッケ
ージを固着する位置には、特殊処理が施されているの
で、パッケージを密着性良く固着できる。また、中空状
のパッケージは絶縁基板の一主面上のみに設けられてい
るので、パッケージの材料費が嵩ばらず、それゆえ、生
産性の向上を図ることができる。As described above, according to the structure of the present invention, a semiconductor chip is connected to one main surface of an insulating substrate having excellent mechanical strength, and a hollow package seals the semiconductor chip. The semiconductor chip is fixed to one main surface of the insulating substrate at a position away from the connection position of the semiconductor chip so that external force due to the package is not applied to the semiconductor chip, thereby improving the connection reliability of the semiconductor device. Can be. Further, since the hollow portion of the package can be formed with high precision, it can be applied to a semiconductor chip having a very small size. In addition, since a special treatment is applied to a position on one main surface of the insulating substrate where the hollow package is fixed, the package can be fixed with good adhesion. Further, since the hollow package is provided only on one main surface of the insulating substrate, the material cost of the package does not increase, and therefore, the productivity can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】この発明の第１実施例である半導体装置の構成
を示す図で、同図（ａ）は同半導体装置の平面図、同図
（ｂ）は同図（ａ）のＡ−Ａ矢視断面図ある。FIGS. 1A and 1B are diagrams showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view of the semiconductor device, and FIG. It is arrow sectional drawing.

【図２】同半導体装置の製造方法を工程順に示す工程図
である。FIG. 2 is a process chart showing a method for manufacturing the semiconductor device in the order of steps.

【図３】同半導体装置の製造方法の一部の工程の置き換
えを示す工程図である。FIG. 3 is a process chart showing replacement of some steps of the method for manufacturing the semiconductor device.

【図４】同半導体装置の製造方法の一部の工程の置き換
えを示す工程図である。FIG. 4 is a process chart showing replacement of some steps of the method for manufacturing the semiconductor device.

【図５】同半導体装置の製造方法の一部の工程の置き換
えを示す工程図である。FIG. 5 is a process chart showing replacement of some steps of the method for manufacturing the semiconductor device.

【図６】この発明の第２実施例である半導体装置の構成
を示す断面図ある。FIG. 6 is a sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention;

【図７】この発明の第３実施例である半導体装置の構成
を示す断面図である。FIG. 7 is a sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention;

【図８】この発明の第４実施例である半導体装置の構成
を示す断面図である。FIG. 8 is a sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.

【図９】この発明の第５実施例である半導体装置の構成
を示す断面図である。FIG. 9 is a sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention.

【図１０】この発明の第６実施例である半導体装置の構
成を示す断面図である。FIG. 10 is a sectional view showing a configuration of a semiconductor device according to a sixth embodiment of the present invention;

【図１１】この発明の第７実施例である半導体装置の構
成を示す図で、同図（ａ）は同半導体装置の平面図、同
図（ｂ）は同図（ａ）のＡ−Ａ矢視断面図ある。11A and 11B are diagrams showing a configuration of a semiconductor device according to a seventh embodiment of the present invention. FIG. 11A is a plan view of the semiconductor device, and FIG. It is arrow sectional drawing.

【図１２】同半導体装置の製造方法を工程順に示す工程
図である。FIG. 12 is a process chart showing a method of manufacturing the same semiconductor device in the order of steps.

【図１３】この発明の第８実施例である半導体装置の構
成を示す断面図である。FIG. 13 is a sectional view showing a configuration of a semiconductor device according to an eighth embodiment of the present invention;

【図１４】この発明の第９実施例である半導体装置の構
成を示す断面図である。FIG. 14 is a sectional view showing a configuration of a semiconductor device according to a ninth embodiment of the present invention;

【図１５】この発明の第１０実施例である半導体装置の
構成を示す断面図である。FIG. 15 is a sectional view showing a configuration of a semiconductor device according to a tenth embodiment of the present invention;

【図１６】この発明の第１１実施例である半導体装置の
構成を示す断面図である。FIG. 16 is a sectional view showing a configuration of a semiconductor device according to an eleventh embodiment of the present invention;

【図１７】この発明の第１２実施例である半導体装置の
構成を示す断面図である。FIG. 17 is a sectional view showing a configuration of a semiconductor device according to a twelfth embodiment of the present invention;

【図１８】従来における半導体装置の構成を示す断面図
である。FIG. 18 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

【図１９】従来における別の半導体装置の構成を示す断
面図である。FIG. 19 is a cross-sectional view showing a configuration of another conventional semiconductor device.

【図２０】同半導体装置の製造方法を示す断面図であ
る。FIG. 20 is a cross-sectional view showing the method for manufacturing the same semiconductor device.

【符号の説明】[Explanation of symbols]

１，２１ 絶縁基板 ２，２ａ，２２，２２ａ 配線パターン ３，２３ 半導体チップ ４，２４ 電極パッド ５，２５ ボール状導体 ６，２７ 中空状のパッケージ ６ａ，６ｃ 中空部 ６ｂ，６ｄ パッケージ基板 ６ｅ 基部 ７ 疎面部 ８，８ａ 上型 ９，９ａ 下型 １０，１０ａ マスク １１ ノズル １２ 研磨剤 １３ ニードル １４，１４ａ 接着剤 １５，２８ ボンディングワイヤ １６，２９ スルーホール配線 １７，３０ ボール状の外部端子 １８，３１ ピン状の外部端子 ２６ 樹脂シート 1, 21 Insulating substrate 2, 2a, 22, 22a Wiring pattern 3, 23 Semiconductor chip 4, 24 Electrode pad 5, 25 Ball-shaped conductor 6, 27 Hollow package 6a, 6c Hollow portion 6b, 6d Package substrate 6e Base 7 Rough surface 8,8a Upper die 9,9a Lower die 10,10a Mask 11 Nozzle 12 Abrasive 13 Needle 14,14a Adhesive 15,28 Bonding wire 16,29 Through-hole wiring 17,30 Ball-shaped external terminal 18,31 Pin-shaped external terminal 26 resin sheet

Claims (12)

【特許請求の範囲】[Claims] 【請求項１】 中空状のパッケージを有する半導体装置
であって、 配線パターンが形成された絶縁基板の一主面上に半導体
チップが接続され、該半導体チップを封止するように絶
縁性の中空状のパッケージが、前記半導体チップの接続
位置から離れた位置の前記絶縁基板の一主面上に固着さ
れていることを特徴とする半導体装置。1. A semiconductor device having a hollow package, wherein a semiconductor chip is connected to one main surface of an insulating substrate on which a wiring pattern is formed, and an insulating hollow is formed so as to seal the semiconductor chip. A semiconductor device, wherein a semiconductor package is fixed on one main surface of the insulating substrate at a position distant from a connection position of the semiconductor chip. 【請求項２】 中空状のパッケージを有する半導体装置
であって、 一主面が凹凸状に形成された絶縁基板の前記凹部上に配
線パターンが形成され、かつ、前記凹部上に半導体チッ
プが接続され、該半導体チップを封止するように絶縁性
のシートが前記絶縁基板の凸部上に固着され、その絶縁
基板の凸部と前記シートとにより中空状のパッケージが
構成されていることを特徴とする半導体装置。2. A semiconductor device having a hollow package, wherein a wiring pattern is formed on the concave portion of an insulating substrate having one main surface formed in an uneven shape, and a semiconductor chip is connected on the concave portion. An insulating sheet is fixed on the convex portion of the insulating substrate so as to seal the semiconductor chip, and a hollow package is configured by the convex portion of the insulating substrate and the sheet. Semiconductor device. 【請求項３】 前記半導体チップの電極パッドと、前記
絶縁基板の前記配線パターンとがボール状導体を通じて
接続されていることを特徴とする請求項１又は２記載の
半導体装置。3. The semiconductor device according to claim 1, wherein the electrode pads of the semiconductor chip and the wiring pattern of the insulating substrate are connected through a ball-shaped conductor. 【請求項４】 前記半導体チップの電極パッドと、前記
絶縁基板の前記配線パターンとがボンディングワイヤを
通じて接続されていることを特徴とする請求項１又は２
記載の半導体装置。4. The semiconductor device according to claim 1, wherein an electrode pad of the semiconductor chip is connected to the wiring pattern of the insulating substrate through a bonding wire.
13. The semiconductor device according to claim 1. 【請求項５】 前記絶縁基板の前記配線パターンは、前
記パッケージの外部まで延長して形成されていることを
特徴とする請求項１乃至４のいずれか１に記載の半導体
装置。5. The semiconductor device according to claim 1, wherein the wiring pattern of the insulating substrate extends to the outside of the package. 【請求項６】 前記絶縁基板の前記配線パターンは、前
記絶縁基板の他主面に形成された配線パターンに、前記
絶縁基板に形成されたスルーホール配線を通じて接続さ
れていることを特徴とする請求項１乃至４のいずれか１
に記載の半導体装置。6. The wiring pattern of the insulating substrate is connected to a wiring pattern formed on the other main surface of the insulating substrate through a through-hole wiring formed on the insulating substrate. Any one of items 1 to 4
3. The semiconductor device according to claim 1. 【請求項７】 前記絶縁基板の他主面の前記配線パター
ンに、ボール状の外部端子が接続されていることを特徴
とする請求項６記載の半導体装置。7. The semiconductor device according to claim 6, wherein a ball-shaped external terminal is connected to the wiring pattern on the other main surface of the insulating substrate. 【請求項８】 前記絶縁基板の他主面の前記配線パター
ン、ピン状の外部端子が接続されていることを特徴とす
る請求項６記載の半導体装置。8. The semiconductor device according to claim 6, wherein said wiring pattern on the other main surface of said insulating substrate and pin-shaped external terminals are connected. 【請求項９】 前記絶縁基板の一主面上の前記パッケー
ジが固着される位置に、あるいは前記シートが固着され
る位置に、前記パッケージあるいは前記シートが密着性
良く固着されるための特殊加工が施されていることを特
徴とする請求項１乃至８のいずれか１に記載の半導体装
置。9. A special process for fixing the package or the sheet with good adhesion at a position where the package is fixed on one main surface of the insulating substrate or at a position where the sheet is fixed. The semiconductor device according to claim 1, wherein the semiconductor device is provided. 【請求項１０】 請求項１記載の半導体装置を製造する
方法であって、 シート状の絶縁基板に複数の中空部を形成するパッケー
ジ基板形成工程と、 一主面上に半導体チップの電極パッドに対応した配線パ
ターンを形成する絶縁基板形成工程と、 前記絶縁基板の一主面上に前記半導体チップを接続した
後、前記中空部が対応する半導体チップを封止するよう
に、前記絶縁基板の一主面上に前記パッケージ基板を固
着するパッケージ基板固着工程と、 前記パッケージ基板及び前記絶縁基板を、個々の半導体
チップごとに分離する基板分離工程とを含むことを特徴
とする半導体装置の製造方法。10. A method for manufacturing a semiconductor device according to claim 1, wherein: a package substrate forming step of forming a plurality of hollow portions in a sheet-shaped insulating substrate; An insulating substrate forming step of forming a corresponding wiring pattern; and after connecting the semiconductor chip on one main surface of the insulating substrate, the insulating substrate is formed so that the hollow portion seals the corresponding semiconductor chip. A method for manufacturing a semiconductor device, comprising: a package substrate fixing step of fixing the package substrate on a main surface; and a substrate separating step of separating the package substrate and the insulating substrate into individual semiconductor chips. 【請求項１１】 請求項２記載の半導体装置を製造する
方法であって、 一主面が凹凸状に形成され、その凹部上に半導体チップ
の電極パッドに対応した配線パターンを形成する絶縁基
板形成工程と、 前記絶縁基板の一主面の凹部上に前記半導体チップを接
続した後、前記半導体チップを封止するように、前記絶
縁基板の一主面の凸部上に絶縁性のシートからなるパッ
ケージ基板を固着するパッケージ基板固着工程と、 前記パッケージ基板及び前記絶縁基板を、個々の半導体
チップごとに分離する基板分離工程とを含むことを特徴
とする半導体装置の製造方法。11. A method for manufacturing a semiconductor device according to claim 2, wherein one main surface is formed in an uneven shape, and a wiring pattern corresponding to an electrode pad of the semiconductor chip is formed on the concave portion. After connecting the semiconductor chip on the concave portion of the one main surface of the insulating substrate, an insulating sheet is formed on the convex portion of the one main surface of the insulating substrate so as to seal the semiconductor chip. A method of manufacturing a semiconductor device, comprising: a package substrate fixing step of fixing a package substrate; and a substrate separating step of separating the package substrate and the insulating substrate into individual semiconductor chips. 【請求項１２】 前記絶縁基板形成工程において、前記
絶縁基板の一主面上の前記パッケージ基板が固着される
位置に、そのパッケージ基板を密着性良く固着するため
の特殊加工を施すことを特徴とする請求項１０又は１１
記載の半導体装置の製造方法。12. In the step of forming the insulating substrate, a special process for fixing the package substrate with good adhesion is performed at a position on one main surface of the insulating substrate to which the package substrate is fixed. Claim 10 or 11
The manufacturing method of the semiconductor device described in the above.
JP00870898A 1998-01-20 1998-01-20 Method for manufacturing semiconductor device Expired - Fee Related JP3339397B2 (en)

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Application Number Priority Date Filing Date Title
JP00870898A JP3339397B2 (en) 1998-01-20 1998-01-20 Method for manufacturing semiconductor device

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JPH11214549A true JPH11214549A (en) 1999-08-06
JP3339397B2 JP3339397B2 (en) 2002-10-28

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002118191A (en) * 2000-10-10 2002-04-19 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing the same
JP2002118192A (en) * 2000-10-10 2002-04-19 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing the same
JP2009065205A (en) * 2003-10-30 2009-03-26 Kyocera Corp Method of manufacturing electronic apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002118191A (en) * 2000-10-10 2002-04-19 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing the same
JP2002118192A (en) * 2000-10-10 2002-04-19 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing the same
JP4565728B2 (en) * 2000-10-10 2010-10-20 三洋電機株式会社 Medium airtight package type semiconductor device
JP4565727B2 (en) * 2000-10-10 2010-10-20 三洋電機株式会社 Manufacturing method of semiconductor device
JP2009065205A (en) * 2003-10-30 2009-03-26 Kyocera Corp Method of manufacturing electronic apparatus

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