JPH11214546A - Nonvolatile semiconductor memory device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower a voltage applied on a control gate and a drain diffusion layer at the time of data writing and prevent erroneous writing in non-selected memory cells by a method wherein a split gate is provided on a SOI substrate. SOLUTION: On a SOI substrate formed with a silicon substrate 1, a silicon oxide film 2 and a silicon thin film 3, a tunnel oxide film 6 is formed on a part of a channel region neighboring a drain diffusion layer 4, and the SOI substrate excluding a region covered with the tunnel oxide film 6 is covered with a silicon oxide film 11. Further, a floating gate 7 is formed on the tunnel oxide film 6, and a control gate 9 is formed via silicon oxide films 11, 8 on the channel region neighboring a source diffusion layer 5 and the floating gate 7, to attain a split gate structure. Thus, it is possible to write into memory cells by applying a low voltage in the vicinity of a threshold voltage on the control gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a structure of a memory cell of a flash memory and a method of manufacturing the same.

[0002]

2. Description of the Related Art As nonvolatile semiconductor memory devices, EPROMs and flash memories capable of erasing and writing information have been known. However, these nonvolatile semiconductor memory devices are conventionally provided with a tunnel oxide film on the surface of a silicon substrate. , Floating gate electrode layer for charge storage, inter-electrode insulating film,
After forming a control gate electrode layer serving as a word line of each memory cell and processing it into a gate electrode shape of a laminated structure of a laminated structure, a source / drain diffusion layer and a channel region are formed, and then a metal wiring to each electrode is formed. Had formed.

However, as disclosed in Japanese Patent Application Laid-Open No. 4-25077, in a flash memory cell having a stacked gate of such a type that a floating gate and a control gate are stacked, a large amount of substrate current is generated when data is erased. There is a problem that occurs. That is, in a flash memory, electrons in the floating gate are generally extracted to the source region. However, when a voltage is applied to the source diffusion layer, an inter-band tunneling phenomenon occurs on the surface of the source diffusion layer located under the thin gate oxide film. As a result, a large amount of substrate current flows. Erasing data in flash memory
In general, an operation of extracting electrons in the floating gate is performed simultaneously for several thousand or more memory cells. Therefore, current consumption at the time of data erasing becomes several mA or more.

As one method for solving such a situation, Japanese Patent Application Laid-Open No. 4-25077 proposes a flash memory cell using an SOI substrate.

[0005] In addition, a flash memory cell using an SOI substrate is disclosed in Japanese Patent Application Laid-Open No. 9-51043. This is achieved by separating an SOI film for each data line on an island. In addition, cell separation is performed to prevent erroneous erasure (erase disturb) in non-selected cells that occurs when data in the selected memory cell is erased.

The structure and operation of a flash memory cell using this SOI substrate will be described below.

As shown in FIG. 7, a tunnel oxide film 36 having a film thickness of, for example, 10 nm is formed on an SOI substrate including a silicon substrate 31, a silicon oxide film 32, and a silicon thin film 33. Further, a floating gate 37 made of a polysilicon film, for example, a film pressure of 18 n is provided through the tunnel film 36.
The m inter-gate insulating films 38 and the control gates 39 made of a polysilicon film are stacked, and these are processed into a gate shape. Also, using this gate pattern as a mask,
For example, the source diffusion layer 35 and the drain diffusion layer 34 are formed by ion-implanting N-type impurities.

Data erasing in a flash memory cell using this SOI substrate is performed, for example, by applying 12 V to the source diffusion layer 35 and 0 V to the control gate 39 as shown in FIG.
Is applied to extract the electrons stored in the floating gate 37 to the source diffusion layer 35.

For data writing, as shown in FIG. 8, for example, 3 V is applied to the drain diffusion layer 34 and the source diffusion layer 3 is applied.
5 by applying 0V. In a flash memory using an SOI substrate, when a channel current starts to flow, holes are generated in the vicinity of the drain diffusion layer 34 by impact ionization caused by the channel current, and the generated holes flow toward the source diffusion layer 35 and It is stored nearby. As a result, the potential distribution in the vicinity of the source diffusion layer 35 changes, and a positive feedback of the channel current, that is, an increase in the channel current, is applied, the generation of channel hot electrons increases, and electrons are injected into the floating gate 37. That is, by applying a low voltage, such as 1V, near the threshold voltage of the memory cell as described above to the control gate 39 instead of a high voltage, data writing becomes possible due to an increase in channel current.

[0010]

However, a plurality of actual flash memory cells are arranged, for example, as shown in FIG. The control gate of each flash memory cell is connected to word lines 40 and 41, the drain diffusion layer is connected to bit lines 42 and 43, and the source diffusion layer is connected to source lines 44 and 45.

The memory cell 4 in such a memory array
4 is selected and data writing is performed, the word lines 40 and 41 are set to 1 V and 0 V, respectively, and the bit lines 42 and 4
3 is 3V and 0V respectively, and the source lines 44 and 45 are 0V
Set to. In this case, for example, in the memory cell 45 in the data erase state, a voltage of 3 V is applied to the drain diffusion layer and a voltage of 0 V is applied to the control gate. In such a situation, when the threshold voltage of the memory cell varies and becomes close to 0 V, a minute channel current also flows in the memory cell 45. As a result, positive feedback to the channel current occurs, the channel current increases, and electrons are also injected into the floating gate of the memory cell 45. That is, at the time of data writing, an erroneous operation occurs in which data writing is performed even in unselected memory cells.

Accordingly, an object of the present invention is to realize a non-volatile memory which can achieve low power consumption by reducing the power supply voltage at the time of data writing and can prevent a malfunction (erroneous writing) of an unselected cell at the time of data writing. To provide a nonvolatile semiconductor memory device.

[0013]

According to the present invention, there is provided a nonvolatile semiconductor device comprising: a first insulating film provided on a semiconductor substrate of one conductivity type; and a first insulating film provided on the first insulating film. Semiconductor film, a second insulating film selectively provided on the semiconductor film, a third insulating film provided on the semiconductor film adjacent to the second insulating film, A floating gate electrode provided on the second insulating film, and a part provided on the third insulating film adjacent to the floating gate electrode and partly on the floating gate via a fourth insulating film; A control gate electrode covering, a drain diffusion layer of the opposite conductivity type to the semiconductor substrate provided in the semiconductor film adjacent to the floating gate electrode, and provided in the semiconductor film adjacent to the control gate electrode; Having a memory cell having a source diffusion layer of a reverse conductivity type. It is a symptom.

According to such a configuration, writing to a target memory cell can be performed by applying a low voltage near the threshold voltage to the control gate electrode, and the channel current of each memory cell is reduced by the source diffusion. Since it is directly controlled by the control gate electrode on the gate oxide film formed on the channel surface on the layer side, the channel current of the unselected memory cell is completely cut off at the source-side channel surface during data writing, An erroneous operation such as erroneous writing of cells can also be prevented.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described. As shown in FIG. 1, the flash memory cell according to the present invention has an SOI substrate formed of a silicon substrate 1, a silicon oxide film 2 and a silicon thin film 3 on a part of a channel region adjacent to a drain diffusion layer 4. Having a tunnel oxide film 6 in the region other than the region covered with the tunnel oxide film 6.
The OI substrate is covered with a silicon oxide film 11. Furthermore, a floating gate 7 is provided on the tunnel oxide film 6, and a control gate 9 is provided on the channel region adjacent to the source diffusion layer 5 and on the floating gate 7 via silicon oxide films 11 and 8. It has become.

FIG. 5 shows a method of manufacturing the memory cell structure.
(A) to (C). First, as shown in FIG. 5A, a silicon oxide film 2 is formed on a silicon substrate 1 to a thickness of, for example, 20 nm (the thickness can be set in a range of 10 nm to 50 nm). An SOI substrate is obtained by forming a silicon thin film 3 having a thickness setting range: 100 nm to 300 nm. After performing an element isolation process on the SOI substrate by, for example, a LOCOS method using thermal oxidation at 1000 ° C., an island method of processing the silicon film 3 by dry etching, or the like, for example, 900
Tunnel oxide film 6 having a film thickness of 10 nm by thermal oxidation
(Thickness setting range: 8 nm to 12 nm). Subsequently, 150 nm is formed on the tunnel oxide film 6 by the CVD method.
Floating gate polysilicon film 7 (thickness setting range: 10
(0 nm to 200 nm). Next, the polysilicon film 7 and the tunnel oxide film 6 are processed into an island shape by photolithography and dry etching. Silicon substrate 1
After impurity implantation for threshold adjustment into
As shown in FIG. 3B, the silicon oxide film 8 having a film pressure of 18 nm (film pressure setting range: 15 n) is formed on the surface of the polysilicon film 7 and the surface of the silicon thin film 3 by thermal oxidation at 900 ° C.
m-30 nm) and 30 nm silicon oxide film 11
(Thickness setting range: 15 nm to 30 nm) is formed. Furthermore, a control gate polysilicon film 9 is formed on the entire surface by a CVD method to a thickness of 150 nm (thickness: 100 nm to 200 nm).
Then, the polysilicon film 9, the silicon oxide film 8, and the polysilicon film 7 are processed into a control gate shape by photolithography and dry etching. At this time, the control gate is processed so that a part of the control gate polysilicon film 9 is in direct contact with the silicon thin film 3 via the silicon film 11. Then, as shown in FIG.
Using the control gate polysilicon film 9 as a mask, for example, arsenic is ion-implanted as an N-type impurity (implantation conditions are, for example, an implantation energy of 30 keV and an implantation amount of 3E15 cm −).
According to 2), the drain diffusion layer 4 is formed on the side where the floating gate 7 and the control gate 9 are stacked, and the source diffusion layer 5 is formed on the side where only the control gate 9 is provided. At this time, the impurity distribution at the junction between the channel and the drain diffusion layer 5 is controlled to be steep so that channel hot electrons are generated efficiently at the time of data writing. For example, the concentrations of the source diffusion layer 5 and the drain diffusion layer 4, the silicon thin film 3 and the silicon substrate are 1E20 cm−3, 5
E16cm-3. Finally, by performing a wiring forming process on the control gate 9, the source diffusion layer 5, and the drain diffusion layer 4, the split gate type flash having the floating gate 7 only on the drain diffusion layer 4 side in the channel region of the memory cell. A memory cell is formed (the wiring is not shown). The threshold voltage of the source diffusion layer 5 side directly controlled by the control gate 9 of the split gate type flash memory cell is, for example, 1 V by the impurity implantation for adjusting the threshold voltage. The threshold voltage is set to match the threshold voltage of the memory cell in the erased state. Next, write and erase operations of the split gate flash memory cell will be described.

First, as shown in FIG. 1, the data erasing operation is performed by applying a negative voltage of, for example, -12 V to the control gate electrode 9 and a positive voltage of, for example, 3 V to the drain diffusion layer 4. At this time, the source diffusion layer 5 is in a floating state. As a result, the electrons accumulated in the floating gate 7 are discharged to the drain diffusion layer 4 by the FN tunnel phenomenon, and the threshold voltage of the memory cell is changed from a high threshold in the written state to a low level of about 1 V in the erased state. It becomes a threshold.

As shown in FIG. 2, for example, the data write operation is performed by applying 1 V to the control gate 9, 3 V to the drain diffusion layer 4, and 0 V to the source diffusion layer 5 and the substrate 1. Since the threshold voltage of the memory cell in the erased state before data writing is 1 V as described above, the channel current starts to flow by application of these voltages. As a result, holes are generated near the drain diffusion layer 4 by impact ionization caused by the channel current, and the generated holes flow toward the source diffusion layer 5 and are accumulated near the source diffusion layer 5. As a result, the potential distribution near the source diffusion layer 5 changes, and a positive feedback to the channel current that the channel current increases increases. This positive feedback phenomenon further increases the channel current and increases the generation of channel hot electrons. Then, the channel hot electrons are injected and accumulated in the floating gate 7.
As described above, data can be written by applying a low voltage of 3 V to the drain diffusion layer 4 and 1 V to the control gate 9.

When such data writing is performed on the memory cell 14 of the memory cell array shown in FIG. 4, 1 V is applied to the word line 10 connected to the memory cell 14.
3 V is applied to the bit line 12, and 0 V is applied to the other word lines 11, bit lines 13, source lines 14, 15 and silicon substrate 1. In this case, the selected memory cell 14
And unselected memory cell 1 connected to common bit line 12
5, 0 V is applied to the control gate 9, 3 V is applied to the drain diffusion layer 4, and 0 V is applied to the source diffusion layer 5 and the silicon substrate 1, as shown in FIG. At this time, the threshold voltage of the memory cell in the erased state varies, and the non-selected memory cell 15
Even if the threshold voltage below the floating gate 7 is close to 0 V, the threshold voltage on the source diffusion layer 5 side directly controlled by the control gate 9 is 1 V as described above. No channel current flows through the memory cell 15, and thus erroneous writing of data is prevented.

Here, in a normal split gate structure, a split gate is generally formed on the drain diffusion layer side, as shown in Japanese Patent Application Laid-Open No. 147336/1995, whereas in the present invention, The point that the split gate portion is formed on the source diffusion layer 5 side and the floating gate is formed on the drain diffusion layer 4 side will be described.

Usually, the split gate is formed on the side of the drain diffusion layer because the source erase method is used for data erase. This is because erasing flash memory involves erasing data from a certain number of memory cells at once.
This is because it is easier to apply a voltage to a commonly connected source diffusion layer than to activate all bit decoders and apply a voltage to each drain diffusion layer. Nevertheless, the reason why the split gate portion is formed on the source diffusion layer side in the present invention is to provide a memory cell in which data can be written with low power consumption. is there. That is, the channel hot electrons are most efficiently generated at the junction between the channel and the drain diffusion layer 4, and the location where the efficiency of injecting electrons into the floating gate is the highest is also the junction between the channel and the drain diffusion layer 4. In the present invention, a part of the floating gate electrode is arranged so as to be located immediately above the junction between the channel and the drain diffusion layer 4, and the split gate portion is located on the source side. With this configuration, as described above, writing can be performed by applying a low voltage, and erroneous writing can be prevented.

In a structure in which a normal split gate portion is located on the side of the drain diffusion layer, channel hot electrons tend to jump into the gate oxide film of the split gate portion at the time of data writing, leading to deterioration of the gate oxide film. According to the invention, such a problem can be prevented.

As described above, in the present invention, since the floating gate is provided on the side of the drain diffusion layer 4, in the first embodiment, the electrons accumulated in the floating gate are extracted to the drain diffusion layer 4. However, in the present memory cell, since the impurity distribution at the junction between the channel and the drain diffusion layer 4 is made steep so that channel hot electrons are generated efficiently, the diffusion layer breakdown voltage of the drain diffusion layer 4 is low. For this reason, in the first embodiment, a sufficient voltage cannot be applied to the drain diffusion layer 4, and the data erasing speed is reduced.

FIG. 6 shows a second embodiment for solving this problem. In this embodiment, the structure of the memory cell and the data write operation are the same as in the first embodiment, but the method of the data erase operation is different. In this embodiment, data is erased by applying a voltage of, for example, -16 V to the control gate 29 and a voltage of 0 V to the silicon substrate 21. By applying these voltages, the electrons accumulated in the floating gate 27 are discharged to the channel region of the memory cell by the FN tunnel phenomenon. According to the data erasing method of this embodiment, it is not necessary to consider the withstand voltage of the drain diffusion layer 4, and high-speed erasing can be performed.

In this embodiment, the thickness of the oxide film 22 of the SOI substrate is important, and it is preferable that the thickness be 10 nm to 50 nm. This is because when this film thickness increases,
At the time of data erasing, a sufficient voltage cannot be applied between the floating gate 27 and the silicon thin film 23 because of the capacitance division between the control gate 29, the floating gate 27, the silicon thin film 23, and the silicon substrate 21, and the data erasing speed is deteriorated. This is because it occurs.

[0026]

As described above, according to the nonvolatile semiconductor memory device of the present invention, since the split gate is provided on the SOI substrate, the data is applied to the control gate and the drain diffusion layer at the time of data writing. There is an effect that the voltage can be reduced, and erroneous writing in unselected memory cells can be prevented.

In addition, by forming a floating gate on the drain diffusion layer side, channel hot electron injection efficiency is improved, and there is also an effect that high-speed writing becomes possible.

[Brief description of the drawings]

FIG. 1 is a sectional view for explaining a data erasing operation according to a first embodiment of the present invention.

FIG. 2 is a sectional view for explaining a data write operation according to the first embodiment of the present invention.

FIG. 3 is a sectional view for explaining the operation of the first embodiment of the present invention.

FIG. 4 is a circuit diagram for explaining the first embodiment of the present invention.

FIG. 5 is a process sectional view for explaining the manufacturing method according to the first embodiment of the present invention.

FIG. 6 is a sectional view for explaining a data erasing operation according to the second embodiment of the present invention.

FIG. 7 is a sectional view for explaining a data erasing operation according to a conventional example of the present invention.

FIG. 8 is a cross-sectional view for explaining a data write operation according to a conventional example of the present invention.

FIG. 9 is a circuit diagram for explaining a conventional example.

[Explanation of symbols]

1,21,31 silicon substrate 2,6,8,11,22,23,27,32,36,3
8 Silicon oxide film 3,23,33 Silicon thin film 7,27,37 Polycrystalline silicon film for floating gate electrode 9,29,39 Polycrystalline silicon film for control gate electrode 12,13,42,43 Bit line 10,11, 40,41 Word line 4,24,34 Drain diffusion layer 5,25,35 Source diffusion layer

Claims (8)

[Claims] A first insulating film provided on a semiconductor substrate of one conductivity type; a semiconductor film of one conductivity type provided on the first insulating film; A second insulating film provided on the semiconductor film adjacent to the second insulating film; a third insulating film provided on the semiconductor film adjacent to the second insulating film;
A floating gate electrode provided on the insulating film, and a portion provided on the third insulating film adjacent to the floating gate electrode and partially covering the floating gate via a fourth insulating film. A control gate electrode, a drain diffusion layer of the opposite conductivity type to the semiconductor substrate provided in the semiconductor film adjacent to the floating gate electrode, and a reverse conductivity type provided to the semiconductor film adjacent to the control gate electrode. A nonvolatile semiconductor memory device comprising a memory cell having a source diffusion layer. 2. The threshold voltage of a region under the control gate electrode in a channel region sandwiched between a source diffusion layer and a drain diffusion layer on a surface of the semiconductor film is such that carriers are not injected into the floating gate. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the threshold voltage in a state below the floating gate is equal to a threshold voltage in a region below the floating gate. 3. The film thickness of the first insulating film is 10 nm to 5 nm.
2. The nonvolatile semiconductor memory device according to claim 1, wherein the thickness is 0 nm. 4. The nonvolatile semiconductor memory device according to claim 1, wherein an impurity concentration distribution at a junction between said semiconductor film and said drain diffusion layer changes rapidly. 5. A memory cell comprising a plurality of memory cells, wherein the memory cells are arranged in a matrix, and data writing to a specific memory cell of the plurality of memory cells is performed by controlling a control gate electrode of the specific memory cell. 3. The non-volatile semiconductor memory device according to claim 2, wherein the operation is performed by applying a voltage approximately equal to the threshold voltage to a connected word line. 6. A memory cell comprising a plurality of memory cells, wherein the memory cells are arranged in a matrix, and data erasing of a specific memory cell among the plurality of memory cells is performed by controlling a control gate electrode of the specific memory cell. 2. The non-volatile semiconductor memory device according to claim 1, wherein the operation is performed by applying a negative voltage to a connected word line and grounding the semiconductor substrate. 7. A memory cell having a plurality of memory cells, wherein the memory cells are arranged in a matrix, and data erasing of a specific memory cell among the plurality of memory cells is performed by controlling a control gate electrode of the specific memory cell. 2. The non-volatile semiconductor device according to claim 1, wherein a negative voltage is applied to a connected word line, and a positive voltage is applied to a bit line to which a drain diffusion layer of the specific memory cell is connected. Storage device. 8. A step of forming a first insulating film on a semiconductor substrate of one conductivity type; a step of forming the semiconductor film of one conductivity type on the first insulating film; Selectively forming a second insulating film, forming a first polysilicon film on the second insulating film, and forming a third polysilicon film on the first polysilicon film and the semiconductor film. Forming an insulating film; forming a second polysilicon film on the third insulating film; forming the third polysilicon film on the silicon film;
Forming the control gate electrode by processing the first polysilicon film, the third insulating film, and the second polysilicon film so that the insulating film remains, and forming the semiconductor using the control gate electrode as a mask. Ion-implanting impurities of a conductivity type opposite to that of the substrate into the film.